Experimental determination of magnitude of selfheating and its influence on breakdown in silicon-on-insulator transistors

When silicon-on-insulator transistors are operated at high power levels significant selfheating is known to occur. The associated increase in the operating temperature can result in a change in the breakdown voltage through the temperature dependence of the multiplication process. Here, the maximum temperature rise, which occurs in the drain depletion region, is measured by monitoring the thermally generated leakage current. The dependence of the multiplication process on temperature is also measured. The work demonstrates that device selfheating together with the temperature dependence of the multiplication process must be accounted for if drain current/drain voltage breakdown is to be accurately predicted.<>     

Novel phenomenon of avalanche breakdown saturation with negativeresistance in a bipolar transistor

A breakdown saturation phenomenon of negative resistance has been observed in a bipolar transistor. The collector current becomes saturated and reaches a critical current (I_CC) after avalanche breakdown. At this critical current, a negative resistance appears. I_CC is determined by the thermal condition of the transistor, as obtained from pulse measurements and temperature dependence. For the multiplication factor (M), it is clear that there are two distinct regions: 1) low voltage (Region I) and 2) higher voltage (Region II). In Region I, the multiplication factor begins to increase with increasing applied voltage and is fixed almost constant for temperature, whereas in Region II, the multiplication factor decreases with increasing temperature. As a result, (∂M/∂V) _T≃0 is realized at about 20 V and 124°C, corresponding to the saturation of avalanche breakdown     

A novel 4H-SiC MESFET by lateral insulator region to improve the DC and RF characteristics

In this paper, a novel recessed gate metal–semiconductor field-effect transistor (RG-MESFET) is presented by modifying the depletion region and the electric field. The proposed structure improves the breakdown voltage, drain current and high frequency characteristics by embedding a lateral insulator region between drain and gate while is placed laterally into the metal gate and a silicon well exactly under the insulator region. We called this new structure as modified recess gate MESFET (MRG-MESFET). The radio frequency and direct current (DC) characteristics of the proposed structure is studied using numerical simulations and compared with a conventional MESFET (C-MESFET). The breakdown voltage, drain current DC transconductance and maximum power density of the proposed structure increase by 27%, 16.5%, 15% and 48%, respectively, relative to the C-MESFET. Also, the gate-source capacitance and the minimum noise figure of the proposed structure improve relative to the C-MESFET. The proposed structure can be used for high breakdown voltage, high saturation drain current, high DC transconductance, high power, high frequency, and low noise applications.     

Breakdowns in Si JFET's

A two-dimensional numerical analysis to clarify the breakdown phenomena in Si n-type JFET is described. In this analysis, the continuity equation for minority carriers is introduced to consider the effect of avalanche multiplication. The heat conduction equation is also taken into account to include the thermal effect on the breakdown voltage. The results obtained are: 1) the mechanisms of excess gate current (EGC), current-mode second breakdown (CSB), and thermal-mode second breakdown (TSB). 2) The effects of how channel impurity concentration Nc, drain current ID, and applied drain voltage VDGaffect EGC, CSB, and TSB are also reported.     

Visible light emission from silicon MOSFETS

We observe visible light emission from Si MOSFET beyond source-drain breakdown. The intensity as well as location varies with gate bias. For zero gate-voltage (V_g) light is seen from four sides of the drain region. But for positive V_g values the location of the light emission shifts to the drain-gate boundary and has a peak in emission intensity at a certain gate bias beyond which it decreases. The initial increase in light intensity is attributed to minority-carrier injection and the decrease at higher gate bias is due to a reduction of lateral field beyond pinch off, which causes a decrease in carrier multiplication. For negative gate-bias, the source-drain breakdown voltage decreases and hence the light intensity increases. A theoretical model for the drain current beyond breakdown is presented and compared with experimental light-intensity curves. The substrate current, which is a measure of the avalanche mechanism by an electron-hole pair generation in the drain depletion region, is measured and compared with light-intensity values.     

Process and device design of a 1000-V MOS IC

High-voltage MOS devices and logic N-MOS circuits have been integrated on the same chip by using a silicon-gate isoplanar process that is compatible with present N-MOS LSI technology. The electrical characteristics of high-voltage MOS devices are modeled and characterized in terms of channel length, drift-layer length, drift-layer ion dose, and extended source field-plate effect. The theoretical calculations of on-resistanee, saturation drain current, and pinchoff voltage agree well with the experimental results. Based on the experimental and theoretical results, the device structure and the process parameters are optimized to obtain maximum drain saturation current with a low on-resistance and a drain breakdown of 1000 V. The optimized high-voltage MOS device can perform with a saturation drain current as high as 84 mA with an on-resistance as low as 300 Ω within an area of 520 µm × 1320 µm while maintaining a drain breakdown of 1000 V.     

A new gate current extraction technique for measurement of on-statebreakdown voltage in HEMTs

We present a new simple three-terminal technique for measuring the on-state breakdown voltage in HEMTs. The gate current extraction technique involves grounding the source, and extracting a constant current from the gate. The drain current is then ramped from the off-state to the on-state, and the locus of drain voltage is measured. This locus of drain current versus drain voltage provides a simple, unambiguous definition of the on-state breakdown voltage which is consistent with the accepted definition of off-state breakdown. The technique is relatively safe and repeatable so that temperature dependent measurements of on-state breakdown can be carried out. This helps illuminate the physics of both off-state and on-state breakdown     

( NH4) 2Sx 溶液改善GaAs MESFETs 击穿特性的机理研究

使用（NH4）2Sx溶液对GaAs MESFETs进行处理。处理后，器件各栅偏压下的源漏饱和电流降低了，栅漏击穿电压有了显著提高。我们认为负电荷表面态影响着栅边缘的电场，负电荷表面态密度的增大会提高器件的击穿电压，这就是（NH4）2Sx溶液处理可改善GaAs MESFET击穿电压的原因。     

Back-channel hot-electron effect on the front-channelcharacteristics in thin-film SOI MOSFETs

The front-channel I-V characteristics in thin-film SOI MOSFETs have been studied before and after back-channel hot-electron stress. As a result of electron trapping in the buried oxide near the drain junction, this stress causes the following changes: (1) a reduction of the channel current for a given gate voltage; (2) the appearance of the kink effect when measured in the reverse mode (with source and drain interchanged); and (3) an increased breakdown voltage when measured in the reverse mode. Both the kink effect and the change in the breakdown behavior can be attributed to the increased barrier height of the drain-body junction resulting from the localized electron trapping in the buried oxide     

4H-SiC MESFET的特性研究

对4H-SiC MESFET的特性研究发现,在室温下4H-SiC MESFET饱和漏电流的值为0.75A/mm,随着温度的上升,器件的饱和漏电流和跨导一直下降;栅长越短,沟道层掺杂浓度越高,饱和漏电流就越大.300K时器件的击穿电压为209V,计算出来的最大功率密度可达19.22W/mm.这些结果显示了4H-SiC在高温、高压、大功率器件应用中的优势.     

Noise studies in internal field emission diodes

The breakdown process of a zener diode in reverse direction is governed by internal field emission at low voltage and by impact ionization at higher voltage. For breakdown voltage in the transition range between 3 and 6 V, both physical processes appear in combination. Measuring the I–V characteristic and the noise current fluctuations spectral density it is possible to show the zener current multiplication by the multiplication effect described by Tager. In addition the I–V characteristic can be written empirically I = Vⁿ.     

Single-electron effect in PtSi/porous Si Schottky junctions

PtSi/porous Si schottky junctions exhibit a breakdown type current-voltage (I-V) curve in reverse bias mode. Below breakdown their current density is much less than regular PtSi/Si junctions. The breakdown voltage decreases with application of infrared radiation for both n and p-type junctions. N-type junctions are sensitive to IR wavelengths of up to 7 /spl mu/m even at room temperature. The small reverse bias current, the change of breakdown voltage with radiation, and IR sensitivity at room temperature can all be explained by single-electron effect. Numerical results show that representative porous schottky junctions exhibit depletion capacitances in 10/sup -19/ f range which is enough to observe single-electron effect at room temperature. Single-electron effect and avalanche multiplication can explain existing experimental data.     

Preparation and properties of Zn delta-doped GaAs/AlGaAs heterojunction phototransistor

We have prepared, characterized and discussed the performance of AlGaAs/GaAs heterojunction bipolar phototransistor (HPT) including Zn delta-doped base. Due to the existence of δ-doped sheets located in the middle of undoped GaAs base the δ-doped HPT devices exhibit low dark current, nearly zero offset voltage, saturation voltage ∼0.4 V, and rise and fall times in ns range at wavelength of 850 nm up to 6 V of applied voltage. Due to avalanche multiplication behavior at the collector junction, an increased optical gain G>10 can be reached for applied voltages in the range of 6-12 V. For voltages higher than the device breakdown voltage (∼12 V) switching and negative differential resistance (NDR) effect is measurable in the inverted mode of operation.     

EEPROM as an analog storage device, with particular applications inneutral networks

The use of EEPROM as a compact, high-precision, nonvolatile, and reconfigurable analog storage element is investigated, with particular consideration given to the modifiable weight storage and analog multiplication problems in the hardware implementation of a neural network. Industry-standard digital EEPROM cells can be programmed to any analog value of threshold voltage, but programming characteristics of different devices on the same chip vary. The programming window of a single device also narrows with cycling. These phenomena necessitate the use of a feedback-based programming scheme. Stressing at high temperature suggests that charge retention is good even at 175°C. The linear variation of threshold voltage with temperature implies that temperature compensation of EEPROM is no more complicated than its conventional MOSFET counterpart. The drain current in the saturation region is found to be a quadratic function of drain voltage when the floating-gate-to-drain overlap capacitance is adequately large. A differential circuit that uses this property to generate the multiplication function required of neural net synapses is proposed     

TiA1和TiPtAu栅GaAs MESFET稳定性研究

在高温和大栅电流下 ,对 Ti Al栅和 Ti Pt Au栅 MESFET的稳定性进行了比较研究 ,结果表明 :( 1)两种器件的击穿电压稳定 ,栅 Schottky接触二极管理想因子 n变化不明显 ;( 2 ) Ti Al栅的 MESFET的栅特性参数 (栅电阻 Rg,势垒高度 Φb)变化明显 ,与沟道特性相关的器件参数 (如最大饱和漏电流 Idss,栅下沟道开路电阻 R0 ,夹断电压 Vp0 等 )保持相对不变 ;( 3)对 Ti Pt Au栅MESFET来说 ,栅 Schottky二极管特性 (栅电阻 Rg,势垒高度 Φb)保持相对稳定 ,与沟道特性相关的器件参数 (如最大饱和漏电流 Idss,栅下沟道开路电阻 R0 ,夹断电压 Vp0 、跨导 gm 等 )明显变化 ,适当退火后 ,有稳定的趋势。这两种器件的参数变化形成了鲜明的对比。     

Normally Off AlGaN/GaN Low-Density Drain HEMT (LDD-HEMT) With Enhanced Breakdown Voltage and Reduced Current Collapse

We report a low-density drain high-electron mobility transistor (LDD-HEMT) that exhibits enhanced breakdown voltage and reduced current collapse. The LDD region is created by introducing negatively charged fluorine ions in the region between the gate and drain electrodes, effectively modifying the surface field distribution on the drain side of the HEMT without using field plate electrodes. Without changing the device physical dimensions, the breakdown voltage can be improved by 50% in LDD-HEMT, and the current collapse can be reduced. No degradation of current cutoff frequency (f_t) and slight improvement in power gain cutoff frequency (f_max) are achieved in the LDD-HEMT, owing to the absence of any additional field plate electrode     

基于HfO2栅介质的Ga2O3 MOSFET器件研制

采用金属有机化学气相沉积(MOCVD)方法在(010) Fe掺杂半绝缘Ga2O3同质衬底上外延得到n型β-Ga2O3薄膜材料,材料结构包括400 nm的非故意掺杂Ga2O3缓冲层和40 nm的Si掺杂Ga2O3沟道层.基于掺杂浓度为2.0×1018 cm-3的n型β-Ga2O3薄膜材料,采用原子层沉积的25 nm的HfO2作为栅下绝缘介质层,研制出Ga2O3金属氧化物半导体场效应晶体管(MOSFET).器件展示出良好的电学特性,在栅偏压为8V时,漏源饱和电流密度达到42 mA/mm,器件的峰值跨导约为3.8 mS/mm,漏源电流开关比达到108.此外,器件的三端关态击穿电压为113 V.采用场板结构并结合n型Ga2O3沟道层结构优化设计能进一步提升器件饱和电流和击穿电压等电学特性.     

Off-state breakdown and leakage current transport analysis of AlGaN/GaN high electron mobility transistors

Off-state breakdown characteristics of AlGaN/GaN high-electron-mobility transistors have been studied based on drain current injection method. It is found that at low drain current injection level, the observed premature breakdown is caused by excess gate-to-drain leakage current. Nevertheless, at high drain injection current level, buffer-leakage-dominated breakdown proceeds gate-leakage-dominated breakdown as the gate bias increases from pinch-off voltage to deep-depletion voltage. In both breakdown regions, the breakdown voltages show negative temperature coefficients. The buffer-leakage-induced breakdown should be defect-related, which is confirmed by temperature-dependent buffer leakage measurements.     

Single-transistor-latch-induced degradation of front- andback-channel thin-film SOI transistors

The front- and back-channel transistor characteristics in thin-film silicon-on-insulator (SOI) MOSFETs have been studied before and after front-channel hot-carrier stress resulting from single-transistor latch. This stress causes the following significant changes: (a) a reduction of the front-channel current for a given gate voltage, (b) an increase in front-channel drain-source breakdown voltage when measured in the reverse mode, and (c) a decrease in the back-channel transconductance. These changes can be attributed to the hot-carrier induced interface traps on both front and back interfaces near the drain junction     

Improvement of breakdown voltage in SOI n-MOSFETs using thegate-recessed (GR) structure

A gate-recessed structure is introduced to SOI MOSFETs in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage can be seen compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain