Analytical modeling and analysis of Al m Ga1−m N/GaN HEMTs employing both field-plate and high-k dielectric stack for high-voltage operation

In this paper, a new high-voltage Al _m Ga_1?m N/GaN HEMT (High Electron Mobility Transistors) with Field-Plate and high-k dielectric stack, Graded two-dimensional electron gas (2DEG) Channel Field-Plate Stack dielectric (GCFPS) HEMTs structure has been reported. The proposed structure has shown enhancements of the performances of the GaN-based HEMTs taking into account the effects of spontaneous and piezoelectric polarization fields. In order to analyze this structure, a 2D analytical model has been developed where the expressions for 2D channel potential and electric field distribution have been derived. It was shown that the GCFPS design exhibits significantly reduction of the electric field peaks along the 2DEG channel. Therefore, the breakdown voltage (BV) is greatly improved in comparison with the standard AlGaN/GaN FP-HEMTs. The developed model is validated by the good agreement with the 2D simulated data.     

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano‐circuit simulation. The FinFET used in this work is designed using careful engineering of source–drain extension, which simultaneously improves maximum frequency of oscillation ƒ_max because of lower gate to drain capacitance, and intrinsic gain A_V0 = g_m/g_ds, due to lower output conductance g_ds. The framework for the ANN‐based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I_d on drain–source V_ds and gate–source V_gs is derived by a simple two‐layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low‐noise amplifier. At low power (J_ds∼10 µA/µm) improvement was observed in both third‐order‐intercept IIP₃ (∼10 dBm) and intrinsic gain A_V0 (∼20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first‐order to third‐order derivative of I_d with respect to gate voltage and lower g_ds in FinFET compared to bulk MOSFET. Copyright © 2009 John Wiley & Sons, Ltd.     

Output characteristics model for an a‐Si ISFET pH sensor

A mathematical model for the calculation of the output characteristics of amorphous silicon hydrogenated (a‐Si:H) ion‐sensitive field‐effect transistors (ISFET) is developed, which depends on the integration of the conductivity channel versus gate voltage curve at fixed drain voltage. Single curve integration was changed to integration with many simple lines to obtain the I_D − V_D characteristics using computer programming. The results of this model were tested with those of experiments. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Electrothermal Monte Carlo simulation of submicron wurtzite GaN/AlGaN HEMTs

We present results from the simulation of the electrothermal behaviour of submicron wurtzite GaN/AlGaN High Electron Mobility Transistors (HEMTs). The simulator uses an iterative procedure which couples a Monte Carlo simulation with a fast Fourier series solution of the Heat Diffusion Equation (HDE). The results demonstrate the dependence of the extent of the thermal droop observed in the I_ds-V_ds characteristics and the device peak temperature on the device bias. The paper also investigates the effect of the inclusion of thermal self-consistency on the device microscopic properties and studies the dependence of the device electrothermal characteristics on the type of substrate material used.     

Simulation of slow current transients and current collapse in GaN FETs

Two-dimensional transient simulations of GaN MESFETs are performed in which a three-level compensation model is adopted for a semi-insulating buffer layer, where a shallow donor, a deep donor and a deep acceptor are considered. When the drain voltage V _D is raised abruptly (while keeping the gate voltage V _G constant), the drain current I _D overshoots the steady-state value, and when V _D is lowered abruptly, I _D remains a low value for some periods, showing drain-lag behavior. These are explained by the deep donor’s electron capturing and electron emission processes. We also calculate a case when both V _D and V _G are changed abruptly from an off point, and quasi-pulsed I-V curves are derived from the transient characteristics. It is shown that the drain currents in the pulsed I-V curves are rather lower than those in the steady state, indicating that so-called current collapse could occur due to deep levels in the semi-insulating buffer layer. It is also shown that the current collapse is more pronounced when V _D is lowered from a higher voltage during turn-on, because the trapping effects become more significant.     

An analytical study of undoped symmetric double gate MOSFET (SDG)

In the present paper, compact analytical models for the threshold voltage, threshold voltage roll‐off and subthreshold swing of undoped symmetrical double‐gate MOSFET have been developed based on analytical solution of two‐dimensional Poisson's equation for potential distribution. The developed models include drain‐induced barrier lowering (DIBL) through the V_ds‐dependent parameter. The calculated threshold voltage value, obtained from the proposed model, shows a good agreement with the experimental and published results. The simulation results for potential show that the conduction is highly confined to the surfaces. The threshold voltage sensitivity to the thickness is found to be approximately 0.2%. Model prediction indicates that subthreshold slope is not linearly related to DIBL parameter for thick silicon film. The proposed analytical models not only provide useful insight into behavior of symmetrical DG MOSFETs but also serve as the basis for compact modeling. Copyright © 2010 John Wiley & Sons, Ltd.     

High performance 1 mm AlGaN/GaN HEMT based on SiC substrate

This is our first report on the high performance 1 mm AlGaN/GaN high electron mobility transistor (HEMT) which was developed using home-made AlGaN/GaN epitaxy structures based on SiC substrate. Metal-organic chemical vapor deposition (MOCVD) was used to generate the epitaxy layers. Corresponding experiments show that the device has a gate length of 0.8 μm exhibiting drain current density of 1.16 A/mm, transconductance of 241 ms/mm, a gate-drain breakdown voltage larger than 80 V, maximum current gain frequency of 20 GHz and maximum power gain frequency of 28 GHz. In addition, the power gain under the continues wave condition is 14.2 dB with a power density of 4.1 W/mm, while under the pulsed wave condition, power gain reaches 14.4 dB with power density at 5.2 W/mm. Furthermore, the two-port network impedance characteristics display great potential in microwave application. __________ Translated from Chinese Journal of Semiconductors, 2006, 27(11): 1981–1983 [译自: 半导体学报]     

Modeling the back gate effects of AlGaN/GaN HEMTs

This letter reports the design and simulation of novel AlGaN/GaN double-gate high electron mobility transistors (DG HEMTs) featuring enhanced back gate-control of the two dimensional electron gas in AlGaN/GaN heterostructures. A comparison study was carried out to reveal the difference between the performance of the AlGaN/GaN DG HEMTs and single-gate devices. The results show that the DG GaN-HEMTs can potentially offer a higher transconductance gain and better immunity of the short channel effects of drain induced barrier lowering and subthreshold swing than traditional single-gate HEMTs.     

Threshold voltage modeling for dual‐metal quadruple‐gate (DMQG) MOSFETs

In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Q_inv) at the ‘virtual‐cathode’ reaches to a critical charge Q_th. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.     

Design, fabrication and characterization of dual-channel real space transfer transistor

In this paper, using a δ-doping dual-channel structure and GaAs substrate, a real space transfer transistor (RSTT) is designed and fabricated successfully. It has the standard Λ-shaped negative resistance I–V characteristics as well as a level and smooth valley region that the conventional RSTT has. The negative resistance parameters can be varied by changing gate voltage (V _GS). For example, the PVCR varies from 2.1 to 10.6 while V _GS changes from 0.6 V to 1.0 V. The transconductance for I _P (ΔI _P/ΔV _GS) is 0.3 mS. The parameters of V _P, V _V and threshold gate voltage (V _T) for negative resistance characteristics arising are all smaller than the value reported in the literature. Therefore, this device is suitable for low dissipation power application. __________ Translated from Journal of Semiconductors, 2008, 29(1): 136–139 [译自: 半导体学报]     

A design guideline of parasitic inductance for preventing oscillatory false triggering of fast switching GaN‐FET

Gallium nitride field‐effect transistors (GaN‐FETs) are attractive devices because of its low on‐state resistance and fast switching capability. However, they can suffer from false triggering caused by fast switching. Particularly, a disastrous oscillation of repetitive false triggering can occur after a turn‐off, which may deteriorate the reliability of power converters. To address this issue, we give a design guideline to prevent this phenomenon. We analyze a simple circuit model to derive the condition of occurrence of this phenomenon, which is then verified experimentally. Results show that the parasitic inductance of the gating circuit, L_g, and that of the decoupling circuit, L_d, should be designed so that the LC resonance frequency of L_g and the gate–source capacitance of the GaN‐FET does not coincide with that of L_d and the drain–source capacitance, respectively. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Impact of channel length,gate insulator thickness,gate insulator material,and temperature on the performance of nanoscale FETs

Aggressive technology scaling as per Moore’s law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, application of high-k gate insulator, and temperature change in a double-gate metal–oxide–semiconductor field-effect transistor (DG MOSFET) and carbon nanotube field-effect transistor (CNTFET) were investigated in this work. Computational simulations were performed to investigate SCEs, viz. the threshold voltage (V_th) roll-off, subthreshold swing (SS), and I_on/I_off ratio, in the DG MOSFET and CNTFET while reducing the channel length. The CNTFET showed better performance than the DG MOSFET, including near-zero SCEs due to its pure ballistic transport mechanism. We also examined the threshold voltage (V_th), subthreshold swing (SS), and I_on/I_off ratio of the DG MOSFET and CNTFET with varying gate insulator thickness, gate insulator material, and temperature. Finally, we handpicked almost similar parameters for both the CNTFET and DG MOSFET and carried out performance analysis based on the simulation results. Comparative analysis of the results showed that the CNTFET provides 47.8 times more I_on/I_off ratio than the DG MOSFET. Its better control over the threshold voltage, near-zero SCEs, high on-current, low leakage power consumption, and ability to operate at high temperature make the CNTFET a viable option for use in enhanced switching applications and low-voltage digital applications in nanoelectronics.     

1/f Noise: threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps

Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation—two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO₂ interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO₂ interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.     

Characterization of defect density created by stress in the gate to?drain overlap region using GIDL current model in n-channel MOSFET

In this paper we study the impact of stress on gate induced drain leakage (GIDL) current variations in MOS transistors, which manifested by tunneling in the gate to drain overlap region. The oxide thickness of n-channel transistor used is 8.5?nm. We show that this phenomenon is accentuated in high stress accumulation V _g=?3?V, V _d=3?V, but more less for stress V _g=V _d=3?V. In both cases, any constraint corresponds to an increase in accumulated charges in the transistor and hence the current GIDL.     

Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors

In this paper we numerically examine the electrical characteristics of surrounding-gate strained silicon nanowire field effect transistors (FETs) by changing the radius (R_SiGe) of silicon-germanium (SiGe) wire. Due to the higher electron mobility, the n-type FETs with strained silicon channel films do enhance driving capability (∼8% increment on the drain current) in comparison with the pure Si one. The leakage current and transfer characteristics, the threshold-voltage (V_t), the drain induced barrier height lowering (DIBL), and the gate capacitance (C_G) are estimated with respect to different gate length (L_G), gate bias (V_G), and R_SiGe. For short channel effects, such as V_t roll-off and DIBL, the surrounding-gate strained silicon nanowire FET sustains similar characteristics with the pure Si one.     

A novel efficiency‐enhancement topology: GaN high‐electron mobility transistors with waveform‐modulation structure composed of Schottky diodes

To improve the power‐added efficiency (PAE) of the gallium nitride (GaN) high‐electron mobility transistor (HEMT) in radio frequency applications, this paper studies the relationship between the nonlinearity of the gate capacitance and the PAE of the GaN HEMTs. The theoretical analysis and simulation results demonstrate that the nonlinearity of the gate capacitance modulates the signal phase at the GaN HEMT input and increases the average drain current, leading to increased power consumption and reduced PAE. Then, an efficiency‐enhancement topology for GaN HEMTs that employs the waveform‐modulation effect of Schottky diodes to reduce power consumption and improve efficiency is presented. The efficiency‐enhancement topology for a 4 × 100‐μm GaN HEMT with waveform‐modulation diodes is then fabricated. Results of load‐pull test demonstrate that the novel topology can increase the PAE of the 4 × 100‐μm GaN HEMT by more than 5% at 8 GHz. The novel efficiency‐enhancement topology for GaN HEMTs proposed in this paper will be suitable for applications that demand high‐efficiency GaN HEMTs or circuits.     

Enhancing the design and performance of a gate-all-around (GAA) charge plasma nanowire field-effect transistor with the help of the negative-capacitance technique

A gate-all-around charge plasma nanowire field-effect transistor (GAA CP NW FET) device using the negative-capacitance technique is introduced, termed the GAA CP NW negative-capacitance (NC) FET. In the face of bottleneck issues in nanoscale devices such as rising power dissipation, new techniques must be introduced into FET structures to overcome their major limitations. Negative capacitance is an efficient effect that can be incorporated into a device to enhance its performance for low-power applications and help to reduce the operating voltage. The Landau–Khalatnikov equation can be applied in such cases to obtain the effective bias. To determine the effects of negative capacitance, lead zirconate titanate (PZT) ferroelectric material, a ceramic material with perovskite properties, is adopted as a gate insulator. This approach diminishes the supply voltage and reduces the power dissipation in the device. Excluding their polarization properties, ferroelectric materials are similar to dielectric materials, and PZT offers abundant polarization with improved reliability and a higher dielectric capacitance. Without proper tuning of the thickness of the PZT material, hysteresis behavior mat occur. Hence, the thickness of the PZT material (t_FE) is an essential parameter to optimize the device performance and achieve a reduced threshold voltage for the GAA CP NW NC-FET device proposed herein. Furthermore, varying the thickness of the PZT ferroelectric material can also enhance the performance. When using the highest values of t_FE, improved outcomes with an analogously lower operating voltage are observed. The effects of varying t_FE on the performance characteristics of the device including the drain current, transconductance, polarized charge, etc. are also interpreted herein.

     

选择区域外延槽栅结构GaN常关型MOSFET的研究

高性能GaN常关型功率开关器件的实现是目前研究的热点。槽栅结构GaN常关型MOSFET以其栅压摆幅冗余度大、栅极漏电流小等优势受到广泛关注。制备槽栅结构GaN常关型MOSFET需要的刻蚀方法会在栅极沟道引入缺陷,影响器件的稳定性。首先,提出选择区域外延方法制备槽栅结构GaN常关型MOSFET,期望避免刻蚀对栅极沟道的损伤;再通过改进选择区域外延工艺(包括二次生长界面和异质结构界面的分离及抑制背景施主杂质),使得二次生长的异质结构质量达到标准异质结构水平。研究结果表明,选择区域外延方法能够有效保护栅极导通界面,使器件具备优越的阈值电压稳定性;同时也证明了选择区域外延方法制备槽栅结构GaN常关型MOSFET的可行性与优越性。     

A numerical simulation tool for nanoscale ion‐sensitive field‐effect transistor

In this work, a self‐contained numerical simulation tool for nanoscale Ion‐Sensitive Field‐Effect Transistor (ISFET) is developed. The tool is based on merging nanoscale ballistic MOSFET analytical equations with the Gouy–Chapman–Stern model equations of ISFET to form a system of nonlinear equations that can be solved iteratively to yield ISFET output current. The numerical solution is accomplished using Newton–Raphson method with efficient trust‐region‐dogleg algorithm using MATLAB software coding. The tool is used to optimize the sensitivity and linearity of nanoscale ISFETs, and to study their dependence on reference voltage, drain current level, and gate‐insulator thickness. Moreover, a comparison between three types of insulators, SiO₂, Si₃N₄, and Al₂O₃, has been made. The tool is given the name: NIST (Nanoscale ISFET Simulation Tool). It can be used as a guide for design and optimization of nanoscale ISFETs and can be applied for both single‐gate and double‐gate structures. Copyright © 2016 John Wiley & Sons, Ltd.     

Simulation of slow current transients and current compression in AlGaAs/GaAs HFETs

Two-dimensional transient simulations of AlGaAs/GaAs HFETs are performed in which substrate traps and surface states are considered. When the drain voltage is raised abruptly, the drain current overshoots the steady-state value, and when it is lowered abruptly, the drain current remains at a low value, showing drain-lag behavior. Turn-on characteristics are also calculated when both the gate voltage and the drain voltage are changed abruptly, and quasi-pulsed I-V curves are derived from them. It is shown that the drain lag due to substrate traps could become a cause of so-called current compression of the HFETs. It is also shown that gate lag due to surface states could become a major cause of the current compression.