Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behavior of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended source/drain region. It is found that optimal source/drain-to-gate non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and drain induced barrier lowering characteristic with a slight degradation in source/drain series resistance and effective gate capacitance.     

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO₂‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.     

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

1/f Noise: threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps

Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation—two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO₂ interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO₂ interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.     

Power·delay product in COSMOS logic circuits

In this simulation work, we use COSMOS logic devices—a novel single gate CMOS architecture recently announced [1]—in multi-input logic gates, assessing its performance in terms of power·delay product. We consider three different multi-input logic circuits: a two-input NOR gate, a three-input NOR gate, and a three-input composite NOR/NAND (NORAND) gate. For this power·delay analysis, the transient TCAD simulations are employed in a mixed-mode approach where circuit and device simulations are coupled together, culminating in the delay response of the circuits as well as the static/dynamic current components. The analysis shows that all circuits, except the 3-input NOR gate, has acceptable characteristics at low-power applications and static leakage limits all COSMOS circuits at high-bias conditions.     

Analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with $${N}^{+}{-}{P}^{-}$$ junction

We propose herein a new dual-gate metal–oxide–semiconductor field-effect transistor (MOSFET) with just a unipolar junction (UJ-DG MOSFET) on the source side. The UJ-DG MOSFET structure is constructed from an \({N}^{+}\) region on the source side with the rest consisting of a \({P}^{-}\) region over the gate and drain, forming an auxiliary gate over the drain region with appropriate length and work function (named A-gate), converting the drain to an \({N}^{+}\) region. The new structure behaves as a MOSFET, exhibiting better efficiency than the conventional double-gate MOSFET (C-DG MOSFET) thanks to the modified electric field. The amended electric field offers advantages including improved electrical characteristics, reliability, leakage current, \({I}_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio, gate-induced drain leakage, and electron temperature. Two-dimensional analytical models of the surface potential and electric field over the channel and drain are applied to investigate the drain current in the UJ-DG MOSFET. To confirm their accuracy, the MOSFET characteristics obtained using the 2D Atlas simulator for the UJ-DG and C-DG are analyzed and compared.     

Asymmetric halo and symmetric Single‐Halo Dual‐Material Gate and Double‐Halo Dual‐Material Gate n‐MOSFETs characteristic parameter modeling

This paper presents an analytical subthreshold surface potential model of novel structures called asymmetric pocket‐implanted Double‐Halo Dual‐Material Gate (DHDMG) and Single‐Halo Dual‐Material Gate (SHDMG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which combines the advantages of both the channel engineering (halo) and the gate engineering techniques (dual‐material gate) to effectively suppress the short‐channel effects (SCEs). The model is derived using the pseudo‐2D analysis by applying the Gauss's law to an elementary rectangular box in the channel depletion region, considering the surface potential variation with the channel depletion layer depth. The asymmetric pocket‐implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends. The inner fringing field capacitances are also considered in the model for accurate estimation of the subthreshold surface potential at the two ends of the MOSFET. The same model is used to find the characteristic parameters for dual‐material gate with single‐halo and double‐halo implantations. It is concluded that the DHDMG device structure exhibits better suppression of the SCEs and the threshold voltage roll‐off than a pocket‐implanted and SHDMG MOSFET after investigating the characteristics parameter improvement. In order to validate our model, the modeled expressions have been extensively compared with the simulated characteristics obtained from the 2D device simulator DESSIS. A nice agreement is achieved with a reasonable accuracy over a wide range of device parameter and bias condition. Copyright © 2012 John Wiley & Sons, Ltd.     

An analytic drain current model for long‐channel undoped gate stack surrounding‐gate MOSFETs including interface fixed charges

On the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long‐channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat‐band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding‐gate MOSFETs of the charge‐trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.     

Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator

Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-κ gate dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon and in the high-κ dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains in the high-κ gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow. At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the 25 nm gate length MOSFET.     

Capacitance fluctuations in bulk MOSFETs due to random discrete dopants

Accuracy of timing in circuits and systems using nanoscale transistors is crucial and is dependent, to first order, on the capacitances of the load transistors. It is accepted that variation in parameters will be intrinsic to such devices due to, among other factors, the discrete nature of the doping. It is likely that one such parameter exhibiting variation will be capacitance. Here we investigate, using 3-dimensional simulation, the fluctuation in gate and drain capacitance in a 30 nm MOSFET due to random discrete doping.     

MOSFET开关过程的研究及米勒平台振荡的抑制

设计功率MOSFET驱动电路时需重点考虑寄生参数对电路的影响。米勒电容作为MOSFET器件的一项重要参数,在驱动电路的设计时需要重点关注。重点观察了MOSFET的开通和关断过程中栅极电压、漏源极电压和漏源极电流的变化过程,并分析了米勒电容、寄生电感等寄生参数对漏源极电压和漏源极电流的影响。分析了栅极电压在米勒平台附近产生振荡的原因,并提出了抑制措施,对功率MOSFET的驱动设计具有一定的指导意义。     

Analytical model of hot carrier degradation in uniaxial strained triple-gate FinFET for circuit simulation

The triple-gate (TG) SOI FinFET has well suppressed short-channel effects compared to planar MOSFET due to increased gate voltage controllability. However, the hot carrier injection (HCI) is a serious reliability issue for nanoscale FinFET and this should be taken care for reliable circuit design. The introduction of uniaxial strain in the channel of FinFET to enhance the performance further limits the reliable design of VLSI circuits. Hence, there is a great need to capture these device-level variations in circuits through physics-based models. In this paper, one such analytical model of hot carrier (HC) degradation in uniaxial strained TG FinFET based on reaction–diffusion mechanism is developed, considering various geometrical aspects of the device, for the first time. The developed model is validated using experimentally calibrated Sentaurus TCAD simulation results. The results show that the strain in the channel worsens the degradation of threshold voltage due to HCI. The developed model is integrated in Cadence circuit simulator, and the impact of HC degradation in strained TG FinFET-based CMOS NAND logic circuit is analyzed.     

A novel approach to extracting extrinsic resistances for equivalent circuit model of nanoscale MOSFET

A novel extrinsic resistance extraction method of MOSFET at V_gs = V_ds = 0 V from S‐parameter measurements is presented in this paper. Simulated and measured results of 90‐nm gatelength MOSFET device with a 8 × 0.6 × 12 µm gatewidth (number of gate finger × unit gate width × cells) are compared, and good agreement has been obtained up to 50 GHz. Furthermore, comparisons between the proposed approach and other three methods published are also made in this paper. Copyright © 2016 John Wiley & Sons, Ltd.     

The impact of high-k gate dielectric and FIBL on performance of nano DG-MOSFETs with underlapped source/drain regions

The impact of high-k gate dielectrics and fringing induced barrier lowering (FIBL) effects on a nano double gate MOSFET is studied over a wide range of dielectric permittivity using ballistic quantum simulation. The simulations are based on self-consistent solution of 2D Poisson equation and Schrödinger equation with open boundary conditions, within the Non-equilibrium Green’s Function formalism. The numerical results show that the use of high-k gate at fixed equivalent oxide thickness (EOT), deteriorates the short channel effects due to FIBL effect. We show that the FIBL can be effectively suppressed by using underlapped source/drain region.     

Accurate prediction of the volume inversion impact on undoped Double Gate MOSFET capacitances

This paper demonstrates the capability of our previously published undoped Double‐Gate (DG) MOSFET explicit and analytical compact model to also forecast the effect of the volume inversion (VI) on the intrinsic capacitances. For that purpose, we present simulation results for these capacitances. We show now that the model presents an accurate dependence on the silicon layer thickness, consistent with two‐dimensional numerical simulations, for both thin and thick silicon films. As opposed to our previous work, here we test the capacitance model for three different film thicknesses and also show that the transition from VI regime to dual gate behaviour is well simulated. We demonstrate in this paper that even if the current drive and transconductance are enhanced in VI regime, our results show that intrinsic capacitances are higher as well, which may limit the high‐speed (delay time) behaviour of DG MOSFETs under VI regime. The good agreement between the numerical simulations and our model shows the high potential of our complete DG MOSFET model. Copyright © 2010 John Wiley & Sons, Ltd.     

Uncoupled mode space approach for analysis of nanoscale strained junctionless double-gate MOSFET

In this paper, we have analyzed the electrical characteristics of Strained Junctionless Double-Gate MOSFET (Strained JL DG MOSFET). A quantum mechanical transport approach based on non-equilibrium Green’s function (NEGF) method with the use of uncoupled mode space approach has been employed for this analysis. We have investigated the effects of high-\(\kappa \) materials as gate and spacer dielectrics on the device performance. Low OFF-state current, low DIBL, and low subthreshold slope have been obtained with increase in the gate and spacer dielectric constants. The electrical characteristics of strained JL DG MOSFET have also been compared with conventional JL DG MOSFET and Inversion Mode (IM) DG MOSFET. The results indicated that the Strained JL DG MOSFET outperforms the conventional JL and IM DG MOSFETs, yielding higher values of drain current.     

Semi‐analytical non‐charge‐sheet and non‐depletion MOS model,for inversion charge calculation

A new computationally implemented semi‐analytic mathematical model is presented to obtain a more accurate estimation of the inversion charge in a MOS structure than standard models. The values of the error of the inversion charge obtained are compared with the assumed ‘exact’ numerical calculated values. These errors are appreciably smaller than the estimation coming from the classical charge‐sheet and depletion approximations. Also the calculation time to obtain the inversion charge is shown to be significantly lower than the numerical one. Because of its accuracy and its relatively low computational speed, the proposed model is a good alternative methodology for the calculation of the inversion charge of MOSFET transistors as a function of their physical features and gate bias voltage. In this sense it should be very useful to be implemented by computer‐aided design integrated circuit simulation software. Copyright © 2013 John Wiley & Sons, Ltd.     

A physically based,accurate compact model of direct tunneling gate current considering quantum mechanical effects in nanoscale metal‐oxide‐semiconductor field‐effect transistors

We present a physically based, accurate model of the direct tunneling gate current of nanoscale metal‐oxide‐semiconductor field‐effect transistors considering quantum mechanical effects. Effect of wave function penetration into the gate dielectric is also incorporated. When electrons tunnel from the metal oxide semiconductor inversion layer to the gate, the eigenenergies of the quasi‐bound states turn out to be complex quantities. The imaginary part of these complex eigenenergies, Γ_ij, are required to estimate the finite lifetimes of these states. We present an empirical equation of Γ_ij as a function of surface potential. Inversion layer electron concentration is determined using eigenenergies, calculated by modified Airy function approximation. Hence, a compact model of direct tunneling gate current is proposed using a novel approach. Good agreement of the proposed compact model with self‐consistent numerical simulator and published experimental data for a wide range of substrate doping densities and oxide thicknesses states the accuracy and robustness of the proposed model. The proposed model can well be extended for devices with high‐κ/stack gate dielectrics introducing necessary modifications. Copyright © 2011 John Wiley & Sons, Ltd.     

选择区域外延槽栅结构GaN常关型MOSFET的研究

高性能GaN常关型功率开关器件的实现是目前研究的热点。槽栅结构GaN常关型MOSFET以其栅压摆幅冗余度大、栅极漏电流小等优势受到广泛关注。制备槽栅结构GaN常关型MOSFET需要的刻蚀方法会在栅极沟道引入缺陷,影响器件的稳定性。首先,提出选择区域外延方法制备槽栅结构GaN常关型MOSFET,期望避免刻蚀对栅极沟道的损伤;再通过改进选择区域外延工艺(包括二次生长界面和异质结构界面的分离及抑制背景施主杂质),使得二次生长的异质结构质量达到标准异质结构水平。研究结果表明,选择区域外延方法能够有效保护栅极导通界面,使器件具备优越的阈值电压稳定性;同时也证明了选择区域外延方法制备槽栅结构GaN常关型MOSFET的可行性与优越性。     

Channel noise enhancement in small geometry MOSFET and its influence on phase noise calculation of integrated voltage‐controlled oscillator

Channel noise enhancement due to MOSFET scaling and its influence on phase noise estimation of fully integrated VCO have been studied. The channel noise of MOSFET increases due to the hot electron effect of small geometry MOSFET is obvious. The channel noise coefficient, γ, of NMOS is 3.5 for 40‐nm gate length, 2.0 for 90‐nm gate length in spite of being ⅔ for long channels MOSFET. Simultaneously, calculation of phase noise of fully integrated VCO shows large difference using γ=⅔ because the part of noise performance of VCO gain‐cell depends on channel noise of MOSFET. Calculated phase noise showed good agreement with measured data when the optimum value of channel noise of MOSFET was adopted. Copyright © 2005 John Wiley & Sons, Ltd.