Germanium on sapphire by wafer bonding

This paper describes the creation of a germanium on sapphire platform, via wafer bonding technology, for system-on-a-chip applications. Similar thermal coefficients of expansion between germanium (5.8 × 10^?6 K^?1) and sapphire (5 × 10^?6 K^?1) make the bonding of germanium to sapphire a reality. Germanium directly bonded to sapphire results in microvoid generation during post bond annealing. Inclusion of an interface layer such as silicon dioxide layer by plasma enhanced chemical vapour deposition, prior to bonding, results in a microvoid free bond interface after annealing. Grinding and polishing of the subsequent germanium layer has been achieved leaving a thick germanium on sapphire (GeOS) substrate. Submicron GeOS layers have also been achieved with hydrogen/helium co-implantation and layer transfer. Circular geometry transistors exhibiting a field effect mobility of 890 cm²/V s have been fabricated onto the thick germanium on sapphire layer.     

Development of reliable low temperature wafer level hermetic bonding using composite seal joint

A reliable composite metal seal comprising both intermetallic compounds (IMC) and solder joints, which are formed by transient liquid phase bonding and soldering respectively, is proposed and demonstrated in wafer level bonding experiments. Hermetic sealing is demonstrated on 8-in. wafers using low volume Cu/Sn materials at process temperatures as low as 280 °C. It is shown that the composite seal is stable when subjected to temperatures of 250 °C, and that it provides better hermeticity and reliability than an IMC seal alone.     

Direct bonding of Si wafer pairs with SiO2 and Si3N4 films with a fast linear annealing

2000 Å-SiO₂/Si(1 0 0) and 560 Å-Si₃N₄/Si(1 0 0) wafers, that are 10 cm in diameter, were directly bonded using a rapid thermal annealing method, so-called fast linear annealing (FLA), in which two wafers scanned with a high-power halogen lamp. It was demonstrated that at lamp power of 550 W, corresponding to the surface temperature of ∼450°C, the measured bonded area was close to 100%. At the same lamp power, the bond strength of the SiO₂∥Si₃N₄ wafer pair reached 2500 mJ/m², which was attained only above 1000°C with conventional furnace annealing for 2 h. The results clearly show that the FLA method is far superior in producing high-quality directly bonded Si wafer pairs with SiO₂ and Si₃N₄ films (Si/SiO₂∥Si₃N₄/Si) compared to the conventional method.     

Template replication for full wafer imprint lithography

Typically, the Step and Flash Imprint Lithography (S-FIL^TM) process uses field-to-field drop dispensing of UV-curable liquids for step-and-repeat patterning. Several applications, including patterned magnetic media, photonic crystals, and wire grid polarizers, are better served by a process that allows high-throughput, full-wafer patterning of sub-100 nm structures with modest alignment. Full-wafer imprinting requires a full-wafer template; however, creation of a wafer-scale imprint template with sub-100 nm structures is not feasible with direct-writing approaches. This paper describes a practical methodology for creating wafer-scale templates suitable for full-wafer imprinting of sub-100 nm structures.The wafer-scale template is replicated from a smaller area master template using the S-FIL step-and-repeat process. The pattern is repeated to accommodate the wafer substrate targeted for a particular application. The tone of the master template is maintained by employing an SFIL/R^TM (reverse tone) pattern transfer process. To create the replicate template, the patterns are imprinted onto a fused silica wafer that has been coated with chromium and an organic transfer layer. A silicon-containing resist, Silspin^TM, is spun on to planarize the organic monomer material. Following an etch back of the Silspin, the monomer and transfer layer are patterned using the Silspin as a hard mask. The Silspin and monomer stack then serves as a masking layer for the chromium and fused silica etches. The remaining monomer and chromium are then removed to create a conformal replicate template.     

Fabrication of NbN/AlN/NbN junctions with Al embedding circuits on Si membrane for 1.5 THz SIS mixers

A process has been developed to fabricate NbN tunnel junctions and 1.5 THz SIS mixers with Al electrodes and Al/SiO₂/Al microstrip tuning circuits on thin Si membranes patterned on silicon on insulator wafers (SIMOX). High Josephson current density (J_c up to 2×10⁴ A/cm²) NbN/AlN/NbN and NbN/MgO/NbN SIS junctions have been fabricated with a reasonably good V_m quality factor and energy gap values close to 5 meV at 4.2 K on (100) oriented 3 inches SIMOX wafers covered by a thin (∼8 nm) MgO buffer layer. The sputtering conditions critically influence the dielectric quality of both AlN and MgO tunnel barriers as well as the surface losses of NbN electrodes. 0.6-μm Si/SiO₂ membranes are obtained after processing of a whole wafer and etching the individual chips in EDP. Such a technology is applied to the development of a waveguide/membrane SIS mixer for use around 1.5 THz.     

Influence of a lift hole-equipped pin chuck on wafer flatness

A site flatness of less than 32 nm will be required when fabricating next-generation devices. A pin chuck is used to flatten a warped wafer. This chuck has three lift holes that are utilized when loading and unloading wafers. These holes deteriorate local flatness. This paper describes the influence of wafer thickness and the diameters of lift holes and chuck pins on a theoretical local deformation of a wafer above a lift hole. It clarifies that local deformation is not caused by deformation between pins and is instead caused by the pin sinking into the back surface of the wafer and the compressive deformation caused by the pin itself. Reducing the lift hole diameter by half, or doubling the diameter of the pin, decreases the raised amount above the lift hole to about 75% or 40%, respectively. In addition, a solution that can be used to distribute the concentrated load above pins without increasing the pin diameter is shown which involves decreasing the pin pitch. It has been determined that local flatness less than 10 nm can be achieved by using a pin chuck with a pitch of 1 mm.     

Characterization of n-type Ge layers on Si (100) substrates grown by rapid thermal chemical vapor deposition

Phosphorus-doped n-type Ge layers were grown on p-type Si (100) wafers (8 in. in diameter, resistivity 5–15 Ω cm) using rapid thermal chemical vapor deposition (RTCVD). The surface morphology was very smooth, with a root mean square (RMS) surface roughness of 0.29 nm. The in-plane lattice constant calculated from high-resolution X-ray diffraction (HR-XRD) data was 0.5664 nm, corresponding to in-plane tensile strain of ～0.47%. The Raman Ge peak for each location indicates tensile strain from the Ge wafer. We estimated the in-plane strain as tensile strain of ～0.45%, in excellent agreement with the XRD analysis. Initial photocurrent spectrum experiments on the sample confirm valence band splitting of the direct gap induced by tensile strain. The temperature dependence of the direct bandgap energy E_Γ1 of Ge can be described by the empirical Varshni expression E_Γ1(T)=0.864–5.49×10^–4T ²/(T+296).     

Tailored wafer holder for a reliable deposition of sputtered aluminium nitride thin films at low temperatures

Active actuated resonant micro-electro-mechanical-systems (MEMS) are used for sensing purpose like topography analysis and viscosity sensors. Those applications require straight beams and they rely on controlled film stress of the involved thin films, e.g. the active piezoelectric aluminium nitride (AlN) layer. The AlN consists of aluminium and nitrogen and is deposited with a reactive sputter process. The deposition process heats up the substrate and therefore the wafer bow of the substrate causes a variation of the thermal connection between wafer and sample holder. This goes along with undefined film stress of the AlN layer. In order to minimize the derivation of film stress, the reduction of substrate temperature and the enhancement of thermal connection between substrate and substrate holder is targeted. Therefore a novel clamped substrate holder is designed. High thermal connection to the ambient equipment, equal heat distribution and clamping of wafer stabilize the deposited AlN layer. By examining the layer stress and applying an acid structuring method, an improvement of deposited film is observed. A long term study with AlN deposition with thicknesses of 0.5 µm, 1.0 µm and 2.0 µm on silicon wafers was made to confirm the enhancement.     

Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H₂SO₄, 96%) and hydrogen peroxide (H₂O₂, 30%), 120 °C), SC1 (1:1:5 mixture of NH₄OH, H₂O₂ and H₂O, at 80 °C) or HF solution (6 parts of 40% NH₄F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film.     

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

Low temperature CuCu thermo-compression bonding with temporary passivation of self-assembled monolayer and its bond strength enhancement

Self-assembled monolayer (SAM) of alkane-thiol is formed on copper (Cu) thin layer coated on silicon (Si) wafer with the aim to protect the surface against excessive oxidation during storage in the room ambient. After 3 days of storage, the temporary SAM layer is desorbed with in situ anneal in inert ambient to uncover the clean Cu surface. A pair of wafers is bonded at 250 °C. Clear evidences of in-plane and out-of-plane Cu grain growth are observed resulting in a wiggling bonding interface. This gives rise to enhancement in shear strength in the bonded CuCu layer.     

Determination of safe reliability region over temperature and current density for through wafer vias

Circular and slot backside vias are stressed over current and temperature and the resulting failure times are fitted to Black's equation. Contour plots of the FIT rate are generated and the reliability of circular and slot vias are compared. It is demonstrated that in most cases the FIT rate of the circular via is statistically significantly lower than that of the slot via. However, both types are easily able to meet a goal of 100 FITs in 10 years at T = 125 °C and J = 0.25 × 10⁶ A/cm². The contour map of the FIT rate defines the region where the via can operate reliably. By use of the 95% upper confidence bound, the region of safe operation is reduced in size, adding a layer of margin to the prediction of via reliability. The approach described here provides a “reliability map” for designers allowing trade-offs between temperature current to be made when designing for high reliability.     

Flexible Chip-on-Flex (COF) and embedded Chip-in-Flex (CIF) packages by applying wafer level package (WLP) technology using anisotropic conductive films (ACFs)

Due to increasing demand for higher performance, greater flexibility, smaller size, and lighter weight in electronic devices, extensive studies on flexible electronic packages have been carried out. However, there has been little research on flexible packages by wafer level package (WLP) technology using anisotropic conductive films (ACFs) and flex substrates, an innovative packaging technology that requires fewer process steps and lower process temperature, and also provides flexible packages. This study demonstrated and evaluated the reliability of flexible packages that consisted of a flexible Chip-on-Flex (COF) assembly and embedded Chip-in-Flex (CIF) packages by applying a WLP process.The WLP process was successfully performed for the cases of void-free ACF lamination on a 50 μm thin wafer, wafer dicing without ACF delamination, and a flip-chip assembly which showed stable bump contact resistances. The fabricated COF assembly was more flexible than the conventional COF whose chip thickness is about 700 μm. To evaluate the flexibility of the COF assembly, a static bending test was performed under different bending radiuses: 35 mm, 30 mm, 25 mm, and 20 mm. Adopting optimized bonding processes of COF assembly and Flex-on-Flex (FOF) assembly, CIF packages were then successfully fabricated. The reliability of the CIF packages was evaluated via a high temperature/humidity test (85 °C/85% RH) and high temperature storage test (HTST). From the reliability test results, the CIF packages showed excellent 85 °C/85% RH reliability. Furthermore, guideline of ACF material property was suggested by Finite Element Analysis (FEA) for better HTST reliability.     

Aligned wafer bonding: A key to three dimensional microstructures

Successful fabrication of critically aligned three dimensional structures has been achieved by combining precision alignment procedures and techniques for direct silicon bonding. This produces three dimensional bonded layers that might include combinations of mechanical, electronic and/or optical elements formed in separate prefabricated layers. We call this techniquealigned wafer bonding. The precise aligned bonding of the features was done with an Optical AssociatesHyperline 400 Infrared Aligner. This machine can hold two imprinted wafers face to face while projecting an infrared image of the surfaces to a viewing screen. An array of alignment marks were etched into the surface of silicon wafers with hot potassium hydroxide. These V-grooves were then precisely aligned and the wafers were brought into contact for initial bonding. Subsequent high temperature annealing was used to strengthen and complete the chemical bonding. The instrumentation used in this work required alignment features with a vertical dimension of 30 micrometers to produce a suitable infrared image. We found that the apparent size of the images produced by the optical system limited the accuracy in precision alignment. However, with reduced wafer separation, we achieved wafer alignment with an accuracy of better than 5 micrometers. This technique would generally be used for the precision alignment and bonding of complementary micromechanical, electrical, or optical structures during the formation of three dimensional devices. The details of the aligned wafer bonding and its applications are presented.     

Full wafer microlens replication by UV imprint lithography

The fabrication of microlenses is of great interest for several applications in the field of optics like wafer level cameras, homogenization of light, and coupling of light into glass fibers. Especially for low-cost optical products, microlenses have to be fabricated with a high throughput at an adequate quality. One way to fulfil these requirements is the patterning of microlenses by UV imprint lithography (UV-IL). Within this work, microlenses were replicated into the UV curing material PAK-01 by step and stamp UV-IL on silicon substrates with a diameter of 150 mm. The resulting substrates were used as masters to cast PDMS templates. These PDMS templates can be used for high throughput full wafer UV-IL. Additionally, quartz substrates with a diameter of 100 mm were patterned which could be directly used as so called “optowafers”. Master and patterned microlenses were inspected by scanning electron microscopy and with a white light profilometer. The results clearly demonstrate the excellent quality of the replication process and the capability of UV-IL to pattern microlenses on full wafer level for high throughput applications.     

Low-dimensional devices fabricated by molecular beam epitaxy regrowth over patterned δ-doped backgates

Hydrogen radical decontamination of ex situ patterned GaAs wafers was successfully used to grow a two-dimensional electron gas (2DEG) only 160 Å from the regrowth interface. Interface roughness scattering limits the mobility of this 2DEG to 330 000 cm²/Vs. An initial growth incorporating a delta-doping layer is etched to expose a {411} facet intersecting this back gate and then a 2DEG is regrown over the patterned wafer. We can modulate the potential in the 2DEG on a length-scale given by the width of the doped layer projected onto the facet (<600 Å). We have fabricated a one-dimensional (1D) constriction using this technique which exhibits quantized ballistic conductance.     

Single-walled carbon nanotube transistors fabricated by advanced alignment techniques utilizing CVD growth and dielectrophoresis

Single-walled carbon nanotube field effect transistors (SWNT-FETs) are fabricated by two different alignment techniques. The first technique is based on direct synthesis of an aligned SWNTs array on quartz wafer using chemical vapor deposition. The transistor with three SWNTs and atomic layer deposited (ALD) Al₂O₃ gate oxide shows a contact resistance of 280 KΩ, a maximum on-current of ?7 μA, and a high I_on/I_off ratio (>10³). The second technique is based on room temperature self-assembly of SWNT bundles using dielectrophoresis. By applying AC electric fields, we have aligned nanotube bundles between drain and source contact patterns of a transistor at room temperature. Transistors based on twisted bundle of SWNTs show high contact resistance (MΩ range) and low current drive in the order of tens of nA.     

A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

The wafer warpage problem, mainly originated from coefficient of thermal expansion mismatch between the materials, becomes serious in wafer level packaging as large diameter wafer is adopted currently. The warpage poses threats to wafer handling, process qualities, and can also lead to serious reliability problems. In this paper, a novel mechanical diced trench structure was proposed to reduce the final wafer warpage. Deep patterned trenches with a depth about 100 μm were fabricated in the Si substrate by mechanical dicing method. Both experiment and simulation approaches were used to investigate the effect of the trenches on the wafer warpage and the influence of the geometry of the trenches was also studied. The results indicate that, by forming deep trenches, the stress on the individual die is decoupled and the total wafer warpage could be reduced. The final wafer warpage is closely related to the trench depth and die width. Trenched sample with a depth of 100 μm can decrease the wafer warpage by 51.4%.     

A MEMS-based pneumatic micro-conveyor for planar micromanipulation

This paper present a two dimensional pneumatic actuator based on silicon MEMS technology for objects micro-manipulation using tilted air jets. The device is composed of three layers stacked together, two micro-machined silicon wafers and a Pyrex glass wafer. The system is composed of a set of micro-conveyors in about 9 mm × 9 mm area. Each micro-conveyor has four nozzles and can generate tilted air-jets which allow four conveyance directions. An experiment of the conveyance of a silicon chip of 3 mm diameter and weighing approximately 2 mg was performed with pulsed air flow.     

Biaxially aligned YBCO film tapes fabricated by all pulsed laser deposition

Biaxially aligned yttria-stabilized zirconia (YSZ) films on Ni-based alloy substrates were realized with high deposition rate of 0.5 μm min⁻¹ by the inclined substrate deposition (ISD) technique without ion beam assistance. The microstructure of YSZ was examined to study the growth mechanism of biaxial alignment by ISD. Columnar structures toward the plasma plume suggested a self-shadowing effect in the ISD process. To raise I_c values, YBCO thickness was increased up to 5 μm. Thick YBCO films with high J_c values were realized on the ISD-grown YSZ. Long YBCO tapes with biaxial alignment were successfully fabricated using continuous pulsed laser deposition and a high I_c value of 37.0 A (77.3 K, 0 T) at a 75 cm voltage tap spacing was achieved.