Damascene W/TiN gate MOSFETs with improved performance for 0.1-/spl mu/m regime

W/TiN gate CMOS technologies with improved performance were investigated using a damascene metal gate process. 0.1-/spl mu/m W/TiN stacked gate CMOS devices with high performance and good driving ability were fabricated successfully by optimizing the W/TiN stacked gate structure, improving the W/TiN gate electrode sputtering technology, and reducing W/TiN stacked gate MOSFET surface states and threshold voltages. A super steep retrograde (SSR) channel doping with heavy ion implantation, /sup 115/In/sup +/ for NMOS and /sup 121/Sb/sup +/ for PMOS, was applied here to obtain a reasonably lower threshold voltage and to suppress short-channel effects (SCEs). Non-CMP technology, used to replace CMP during the damascene metal gate process, was also explored. The propagation delay time of 57 stage W/TiN gate CMOS ring oscillators was 13 ps/stage at 3 V and 25 ps/stage at 1.5 V, respectively. Better performance would be achieved by using Co/Ti salicide source/drain (S/D) and thinner gate dielectrics.     

Electrical Properties of Ultra Thin Nitride/Oxynitride Stack Dielectrics pMOS Capacitor with Refractory Metal Gate

Electrical properties of high quality ultra thin nitride/oxynitride（N/O）stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated，and ultra thin (＜2 nm＝ N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are fabricated.Experiment results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices.     

超薄氮氧叠层栅介质的金属栅pMOS电容的电学特性

研究了高质量超薄氮化硅/氮氧化硅(N/O)叠层栅介质的金属栅pMOS电容的电学特性,制备了栅介质等效厚度小于2nm的N/O复合叠层栅介质,该栅介质具有很强的抗硼穿通能力和低的漏电流.实验表明这种N/O复合栅介质与优化溅射W/TiN金属栅相结合的技术具有良好的发展前景.     

高性能亚100nm栅长氮氧叠层栅介质难熔W/TiN金属栅电极CMOS器件

在国内首次将等效氧化层厚度为1.7nm的N/O叠层栅介质技术与W/TiN金属栅电极技术结合起来,用于栅长为亚100nm的金属栅CMOS器件的制备.为抑制短沟道效应并提高器件驱动能力,采用的关键技术主要包括:1.7nm N/O叠层栅介质,非CMP平坦化技术,T型难熔W/TiN金属叠层栅电极,新型重离子超陡倒掺杂沟道剖面技术以及双侧墙技术.成功地制备了具有良好的短沟道效应抑制能力和驱动能力的栅长为95nm的金属栅CMOS器件.在VDS=±1.5V,VGS=±1.8V下,nMOS和pMOS的饱和驱动电流分别为679和-327μA/μm.nMOS的亚阈值斜率,DIBL因子以及阈值电压分别为84.46mV/dec,34.76mV/V和0.26V.pMOS的亚阈值斜率,DIBL因子以及阈值电压分别为107.4mV/dec,54.46mV/V和0.27V.结果表明,这种结合技术可以完全消除B穿透现象和多晶硅耗尽效应,有效地降低栅隧穿漏电并提高器件可靠性.     

Single-Grain Si TFTs and Circuits Inside Location-Controlled Grains Fabricated Using a Capping Layer of SiO2

To enlarge the size of two-dimensional location-controlled Si grains fabricated in the mu-Czochralski process in excimer-laser crystallization, a capping layer (C/L) of SiO₂ was applied to the amorphous-Si (a-Si) thin film. With a 50-nm-thick SiO₂ C/L on a 100-nm-thick a-Si film, the diameter of the location-controlled grain was increased to 7.5 mum. Single-grain Si thin-film transistors (TFTs) were fabricated with the SiO₂ C/L as part of the gate insulator. Field-effect mobilities of 510 and 210 cm²/Vmiddots were obtained for electrons and holes, respectively. Both TFTs were integrated in a single-grain CMOS inverter inside a location-controlled grain. The propagation gate delay was found to be shorter than that in poly-Si circuits under the same device conditions     

Dual-polycide gate technology using regrowth amorphous-Si tosuppress lateral dopant diffusion

Process techniques for dual-polycide gate CMOS have been developed. The origin of lateral dopant diffusion is analyzed, and an enlarged-grain dual-polycide gate technology using regrowth amorphous-Si (a-Si) is proposed. Reduction of the dopant absorption into the silicide layer has been observed in the regrowth of a-Si polycide gate structure. Lateral dopant diffusion has been suppressed to less than 0.1 μm, and, as a result, 0.2 μm n-MOS/p-MOS spacing has been realized under an 850°C furnace annealing process. This technology can also achieve current drivability improvement by suppressing the gate depletion simultaneously. Suppression of boron penetration through the gate oxide to the channel region from the p⁺ gate has been realized by gate doping ion implantation into the a-Si, and no threshold voltage lowering with small standard deviation has been confirmed. It has been recognized that the above techniques are a possible solution for the dual-polycide gate CMOS structure     

The impact of TiN capping Layer on NiSi, CoSi/sub 2/, and Co/sub x/Ni/sub 1-x/Si/sub 2/ FUSI metal gate work function adjustment

The impact of TiN capping layer on dual work functions of Ni, Co, and Co-Ni fully silicided (FUSI) metal gates was investigated. It was found that the TiN capping layer significantly altered the distribution of both n- and p-dopants during the FUSI process, which in turn changed the work functions of both As-doped and B-doped in the three FUSI metal gate systems. The work function tuning was found to have a linear relationship with the change of dopant level at the silicides/dielectric interface after adding TiN capping layer. The investigation of TiN capping layer on FUSI provided some insights on work function tuning mechanism in FUSI systems. This work also suggested a new methodology for optimizing the nMOS and pMOS work functions for CMOS device applications.     

不同双栅极设计对a-Si:H TFT特性影响

本实验于原有的单底栅a-Si TFT产品结构下,通过增加不同的顶栅极设计方式(不同a-Si覆盖比例、不同沟道几何形貌、不同沟道W/L比例)来研究双栅极设计对a-Si TFT特性的影响。实验结果显示双栅极a-Si TFT比现行单底栅a-Si TFT可以提升I_on 7%、降低SS 3%、同时对I_off以及TFT稳定性影响不明显,显示双栅极a-Si TFT设计结构具有在不提高成本以及不变更工艺流程下,达到整体提升TFT特性的效果。顶栅极 TFT 特性不如底栅极,推测为a-Si/PVX界面不佳使得电子导通困难导致,未来可以借由改善a-Si/PVX界面工艺提升顶栅极TFT特性。     

Ultrathin gate oxide CMOS with nondoped selective epitaxial Sichannel layer

The nondoped selective epitaxial Si channel technique has been applied to ultrathin gate oxide CMOS transistors. It was confirmed that drain current drive and transconductance are improved in the epitaxial channel MOSFETs with ultrathin gate oxides in the direct-tunneling regime. It was also found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current. The relation between channel impurity concentration and direct-tunneling gate leakage current was investigated in detail. It was confirmed that the lower leakage current in epitaxial channel devices was not completely explained by the lower impurity concentration in the channel. The results suggest that the improved leakage current in the epitaxial channel case is attributable to the improvement of some aspect of the oxide film quality, such as roughness or defect density, and that the improvement of the oxide film quality is essential for ultrathin gate oxide CMOS. AFM and 1/f noise results support that SiO₂-Si interface quality in epitaxial Si channel MOSFETs is improved. Good performance and lower leakage current of TiN gate electrode CMOS was also demonstrated     

On the impact of TiN film thickness variations on the effective work function of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON gate stacks

The impact of TiN film thickness variations on the effective work function (WF) of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON interfaces has been investigated. The electrical signatures of these gate stacks indicate that the concentration of Hf-Ti and Ti-Si bonds at the (poly-Si/TiN)/HfSiON and (poly-Si/TiN)/SiO/sub 2/ interface plays a significant role on the control of the gate stacks' WF. The density of these interfacial bonds and the related work function changes are correlated to the degree of nucleation of the TiN film on the dielectric.     

Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS)technology for very low voltage operation of under 0.7 V

We propose dynamic threshold-voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very low voltage operation (under 0.7 V). In this technology the metal gate is formed by the damascene gate process and directly connected to the well region (Si-body). Therefore, the connection between gate electrode and silicon body can be more easily fabricated in the DT-DMG transistor than with conventional technologies. Furthermore, we found that low threshold voltage (about 0.15 V reduction for CMOS), high drive current, excellent subthreshold swing (about 60 mV/decade), and uniform electrical characteristics (great reduction of threshold voltage deviation) were obtained in the transistors with midgap work function metal gates (Al/TiN or W/TiN) and low supply voltage (0.7 V)     

体硅衬底上的CMOS Fin FET

介绍了一种制作在普通体硅上的 CMOS Fin FET.除了拥有和原来 SOI上 Fin FET类似的 Fin FET结构 ,器件本身在硅衬底中还存在一个凹槽平面 MOSFET,同时该器件结构与传统的 CMOS工艺完全相容 ,并应用了自对准硅化物工艺 .实验中制作了多种应用该结构的 CMOS单管以及 CMOS反相器、环振电路 ,并包括常规的多晶硅和 W/Ti N金属两种栅电极 .分析了实际栅长为 110 nm的硅基 CMOS Fin FET的驱动电流和亚阈值特性 .反相器能正常工作并且在 Vd=3V下 2 0 1级 CMOS环振的最小延迟为 14 6 ps/门 .研究结果表明在未来 VL SI制作中应用该结构的可行性     

Effective-Work-Function Control by Varying the TiN Thickness in Poly-Si/TiN Gate Electrodes for Scaled High- $k$ CMOSFETs

We have investigated the controllability of the effective work function $( !phi_{m,{rm eff}}!)$ of TiN as a work-function-determining metal (WFM) for various gate-electrode structures in HfSiON MOSFETs. $phi_{m,{rm eff}}$ was controllable from 4.7 to 4.44 eV by changing the TiN thickness from 30 to 2 nm in poly-Si/TiN gate electrodes, without any distinct increase in EOT. Therefore, thin-TiN and thick-TiN WFMs are preferred for the reduction in threshold voltage in nMOSFETs and pMOSFETs with poly-Si/TiN gate electrodes, respectively. A similar controllability was not observed with W/TiN gate electrodes but was evident with W/TaSiN/TiN gate electrodes. This means that controllability is a characteristic of metal gate electrodes with a structure including a Si-rich layer (such as poly-Si and TaSiN)/TiN. It is considered that Ti suboxides, which increase $ phi_{m,{rm eff}}$ as a thin insulator with negative fixed charges, or interface dipoles in the TiN/HfSiON interface, are reduced by oxidation of the Si-rich layer, producing the required result of $phi_{m,{rm eff}}$ decrease when the TiN thickness becomes as thin as 2 nm.      

体硅衬底上的CMOS FinFET

介绍了一种制作在普通体硅上的CMOS FinFET.除了拥有和原来SOI上FinFET类似的FinFET结构,器件本身在硅衬底中还存在一个凹槽平面MOSFET,同时该器件结构与传统的CMOS工艺完全相容,并应用了自对准硅化物工艺.实验中制作了多种应用该结构的CMOS单管以及CMOS反相器、环振电路,并包括常规的多晶硅和W/TiN金属两种栅电极.分析了实际栅长为110nm的硅基CMOS FinFET的驱动电流和亚阈值特性.反相器能正常工作并且在Vd=3V下201级CMOS环振的最小延迟为146ps/门.研究结果表明在未来VLSI制作中应用该结构的可行性.     

Characteristics and thermal stability of MOS devices with MoN/TiN and TiN/MoN metal gate stacks

Metal gate with high work function is the key issue for MOS device. The influences of MoN metal gate with TiN layer above or below and various post metal annealing (PMA) treatments were studied in this work. Experimental results show that metal gate stack with TiN under MoN film (i.e., MoN/TiN sample) exhibits better electrical characteristics on gate leakage current, stress-induced flat-band voltage shift, and stress-induced leakage current and thermal stability despite a little lower work function. Thus MoN/TiN metal gate is promising for p-channel MOS device applications.     

Fully-depleted SOI devices with TaSiN gate, HfO/sub 2/ gate dielectric, and elevated source/drain extensions

We report for the first time the performance of ultrathin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS transistors using HfO/sub 2/ gate dielectric and TaSiN gate material. The transistors feature 100-150 /spl Aring/ silicon film thickness and selective epitaxial silicon growth in the source/drain extension regions. TaSiN-gate shows good threshold voltage control using an undoped channel, which reduces threshold voltage variation with silicon film thickness and discrete, random dopant placement. Device processing for CMOS fabrication is drastically simplified by the use of the same gate material for both n- and p-MOSFETs. Electrical characterization results illustrate the combined impact of using high-k dielectric and metal gate on the performance of ultrathin film FD SOI devices.     

TiN栅薄膜全耗尽SOI CMOS器件

制备并研究了TiN栅薄膜全耗尽SOI CMOS器件,并对其关键工艺进行了详细阐述.相对于双多晶硅栅器件,在不改变阈值电压的前提下,可以减小nMOS和pMOS的沟道掺杂浓度,进而提高迁移率.由于TiN的功函数处于中间禁带,在几乎相同的调整阈值注入剂量下,可以得到对称的阈值电压.当顶层硅膜厚度减小时,可以改善短沟道效应.     

An advanced 0.5-μm CMOS disposable TiN LDD/salicide spacerprocess

An advanced 0.5-μm CMOS technology which features disposable TiN spacers to define both lightly doped drain (LDD) implantation and self-aligned silicided source, drain, and gate regions is discussed. Since the LDD implantation sequences are reversed using the disposable TiN spacers, this process results in CMOS devices with low salicided junction leakage, reduced source/drain lateral diffusion, and shallow phosphorus N^- and boron P^- regions for improved short-channel behavior     

W/TiN Gate Thin-Film Fully-Depleted SOI CMOS Devices

TiN gate thin-film fully-depleted SOI CMOS devices are fabricated and discussed.Key process technologies are demonstrated.Compared with the dual polysilicon gate devices,the channel doping concentration of nMOS and pMOS can be reduced without changing threshold voltage (VT)，which enhances the mobility.Symmetrical VT is achieved by nearly the same VT implant dose because of the near mid-gap workfunction of TiN gate.The SCE effect is improved when the thin-film thickness is reduced.     

Titanium nitride local interconnect technology for VLSI

This paper reports on how the self-aligned titanium disilicide process, normally used to simultaneously reduce MOS gate and junction sheet resistances to less than 1 Ω/square, has been extended to provide a layer of local interconnect for VLSI CMOS applications. The local interconnect level has been realized by utilization of the titanium nitride (TIN) layer that forms during the gate and junction silicidation process. Normally the TiN layer is discarded, but in this process the 0.1-µm-thick TiN layer is patterned and etched to provide local connections between polysilicon gates and n⁺and p⁺junctions, with a sheet resistance of less than 10 Ω/ square. This is accomplished without area consuming contacts or metal straps, and without any extra deposition steps. In addition to providing a VLSI version of the buried-contact process, the technology permits the widespread use of self-aligned contacts and minimum geometry junctions. These features significantly reduce parasitic capacitance with the result that the signal propagation delay through a 1-µm CMOS inverter is decreased by 20- 25 percent. The TiN local interconnect process has been successfully demonstrated by the fabrication of a pseudo-static CMOS VLSI memory with nearly half a million 1-µm transistors. A full CMOS 16K SRAM has also been fabricated in which the TiN layer performs the gate to n⁺and p⁺junction cross-coupling function. Application of the technology to achieve a high-density full CMOS SRAM cell, that makes a 256K SRAM chip size of less than 80K mils²feasible with 1-µm design rules, is also discussed.