Depletion layer of gate poly-Si

The depletion effects of gate poly-Si are investigated in detail taking into consideration the fact that many-body effects due to carrier-carrier and carrier-ion interactions are different at the surface than in a bulk of the gate poly-Si. All calculations are self-consistently performed including an incomplete ionization of activated impurities in an iterative manner. As a result, it is found that the surface part of these interactions affects the equivalent oxide thickness determined by the capacitance-voltage fitting, and that the bulk part affects the determination of flat band potential. It is also found that the surface of the gate poly-Si is incompletely depleted, and the depletion layer is then wider than calculated when assuming the complete depletion (N/sub S//N/sub D/). The width of the incomplete depletion layer is studied in detail for the first time.     

On the impact of TiN film thickness variations on the effective work function of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON gate stacks

The impact of TiN film thickness variations on the effective work function (WF) of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON interfaces has been investigated. The electrical signatures of these gate stacks indicate that the concentration of Hf-Ti and Ti-Si bonds at the (poly-Si/TiN)/HfSiON and (poly-Si/TiN)/SiO/sub 2/ interface plays a significant role on the control of the gate stacks' WF. The density of these interfacial bonds and the related work function changes are correlated to the degree of nucleation of the TiN film on the dielectric.     

TiN栅薄膜全耗尽SOI CMOS器件

制备并研究了TiN栅薄膜全耗尽SOI CMOS器件,并对其关键工艺进行了详细阐述.相对于双多晶硅栅器件,在不改变阈值电压的前提下,可以减小nMOS和pMOS的沟道掺杂浓度,进而提高迁移率.由于TiN的功函数处于中间禁带,在几乎相同的调整阈值注入剂量下,可以得到对称的阈值电压.当顶层硅膜厚度减小时,可以改善短沟道效应.     

W/TiN Gate Thin-Film Fully-Depleted SOI CMOS Devices

TiN gate thin-film fully-depleted SOI CMOS devices are fabricated and discussed.Key process technologies are demonstrated.Compared with the dual polysilicon gate devices,the channel doping concentration of nMOS and pMOS can be reduced without changing threshold voltage (VT)，which enhances the mobility.Symmetrical VT is achieved by nearly the same VT implant dose because of the near mid-gap workfunction of TiN gate.The SCE effect is improved when the thin-film thickness is reduced.     

Submicrometer polysilicon gate CMOS/SOS technology

A process is described for the fabrication of CMOS/SOS submicrometer devices and integrated circuits. The process utilizes the lateral diffusion of boron into polycrystalline silicon and a subsequent anisotropic etchant to define the narrow poly gates. Devices with channel lengths as small as 0.3 µm have been fabricated and characterized. Both avalanche and tunnel injection of carriers into the gate dielectric have been measured and both can have an impact on the limit of voltage operation. At present, these mechanisms appear to place an upper limit of about 8 V on the operating voltage of dynamic circuits containing 0.5- µm channel length devices. The propagation delay of 0.5-µm channel length CMOS/SOS inverters is about 200 ps at 5 V and dynamic binary counters will operate with a maximum input frequency of 550 MHz and 8 V while dissipating 130 mW.     

An integratable dual metal gate CMOS process using an ultrathin aluminum nitride buffer layer

We propose and demonstrate a novel approach for dual metal gate CMOS process integration through the use of a very thin aluminum nitride (AlN/sub x/) buffer layer between metal and gate oxide. This buffer layer prevents the gate oxide from being exposed to a metal etching process which potentially causes oxide thinning and damage. Subsequent annealing consumes the very thin AlN/sub x/ layer and converts it into a new metal alloy film by reacting with gate metals, resulting in no increase in EOT due to this buffer layer. The work function of the original gate metal is also modified as a result of its reaction with AlN/sub x/, making this approach extremely attractive for engineering the work function for dual metal gate CMOS applications.     

Performance and reliability of poly-Si TFTs on FSG buffer layer

A novel and process-compatible scheme for fabricating poly-Si thin-film transistors (TFTs) on an FSG buffer layer was proposed and demonstrated. Experimental results reveal that remarkably improved device performance and uniformity can be achieved with appropriate fluorine concentration. The poly-Si TFTs fabricated on FSG layers have a higher on-current, a lower leakage current, and a higher field-effect mobility compared with the conventional poly-Si TFTs. Furthermore, the incorporation of fluorine also increased the reliability of poly-Si TFTs against hot carrier stressing, which is attributed to the formation of Si-F bonds.     

High-performance subquarter-micrometer gate CMOS technology

A single phosphorous-doped poly(n⁺)-Si gate, a 3.5-nm-thick gate oxide, and a retrograde twin-well structure with trench isolation are used in the devices considered. Latchup holding voltages exceed 8 V. The transconductances of 0.22-μm-gate-length n and p MOSFETs are 450 and 330 mS/mm, respectively, and unloaded ring oscillator delays are 36 ps at 2 V. A static-type 1/2 divider utilizing nMOSFETs of 0.16-μm gate length and pMOSFETs of 0.22-μm gate length achieved a maximum operating frequency of 1.3 GHz and power of 5.6 mW at a supply voltage of 2 V     

在metal/high-k 栅叠层中插入Ti/TiN金属层实现远距离吸氧技术

High permittivity materials have been required to replace traditional SiO₂ as the gate dielectric to extend Moore’s law.However,growth of a thin SiO₂-like interfacial layer（IL） is almost unavoidable during the deposition or subsequent high temperature annealing.This limits the scaling benefits of incorporating high-k dielectrics into transistors.In this work,a promising approach,in which an O-scavenging metal layer and a barrier layer preventing scavenged metal diffusing into the high-k gate dielectric are used to engineer the thickness of the IL,is reported. Using a Ti scavenging layer and TiN barrier layer on a HfO₂ dielectric,the effective removal of the IL and almost no Ti diffusing into the HfO₂ have been confirmed by high resolution transmission electron microscopy and X-ray photoelectron spectroscopy.     

A new MoSi2/Thin poly-Si gate process technology without dielectric degradation of a gate oxide

The dielectric degradation phenomena in gate oxides of MoSi²/thin n⁺poly-Si (<100 nm) gate structure which appeared after high-temperature annealing have been analyzed in detail. Analyses included obtaining the correlation between gate oxide dielectric characteristics and various factors like phosphorus concentration in poly-Si, native oxide on poly-Si, sheet resistance of MoSi², and the SEM or TEM observations of textures of MoSi², poly-Si, and gate oxide. From analyses, it was concluded that the local reaction of molybdenum silicide with poly-Si under the presence of a barrier, like the thick native oxide on poly-Si formed before MoSi²deposition, results in the damage to a gate oxide through a thin poly-Si layer during annealing. Based upon analytical results, a new MoSi²/thin poly-Si gate process without dielectric degradation has been developed, in which the direct MoSi²deposition on undoped poly-Si to suppress the native oxide growth and phosphorus implantation into MoSi²were introduced. The process provided a good dielectric strength of a gate oxide even to the device with a poly-Si layer as thin as 50 nm, an easy dry etching without undercutting of poly-Si, and stable device characteristics and reliabilities compatible to a conventional poly-Si gate process.     

Elimination of poly-Si gate depletion for sub-65-nm CMOS technologies by excimer laser annealing

Pulsed excimer laser annealing (ELA) is used to reduce the poly-Si gate depletion effect (to <0.1 nm). Low resistivity (0.58 m/spl Omega//spl middot/cm) and high active boron concentration (4/spl times/10/sup 20/ cm/sup -3/) at the gate-oxide interface are achieved while preserving the gate oxide quality and avoiding boron penetration, to meet International Technology Roadmap for Semiconductors requirements for sub-65-nm CMOS technology nodes. ELA is compatible with high-/spl kappa/ dielectric (HfO/sub 2/) and results in significantly lower gate leakage current density as compared with rapid thermal annealing (RTA).     

Calculation of microwave performance of buffer layer gate GaAs MESFET's

The microwave performance of a GaAs MESFET, where a buffer layer of a low carrier concentration is inserted between the gate metal and the channel layer, is calculated and compared with that of a conventional MESFET. It is found that the use of such a high-resistivity buffer layer contributes to a great improvement of the microwave performance of the GaAs MESFET, especially in fTandf_{max}.     

Damascene W/TiN gate MOSFETs with improved performance for 0.1-/spl mu/m regime

W/TiN gate CMOS technologies with improved performance were investigated using a damascene metal gate process. 0.1-/spl mu/m W/TiN stacked gate CMOS devices with high performance and good driving ability were fabricated successfully by optimizing the W/TiN stacked gate structure, improving the W/TiN gate electrode sputtering technology, and reducing W/TiN stacked gate MOSFET surface states and threshold voltages. A super steep retrograde (SSR) channel doping with heavy ion implantation, /sup 115/In/sup +/ for NMOS and /sup 121/Sb/sup +/ for PMOS, was applied here to obtain a reasonably lower threshold voltage and to suppress short-channel effects (SCEs). Non-CMP technology, used to replace CMP during the damascene metal gate process, was also explored. The propagation delay time of 57 stage W/TiN gate CMOS ring oscillators was 13 ps/stage at 3 V and 25 ps/stage at 1.5 V, respectively. Better performance would be achieved by using Co/Ti salicide source/drain (S/D) and thinner gate dielectrics.     

Ultrathin gate oxide CMOS with nondoped selective epitaxial Sichannel layer

The nondoped selective epitaxial Si channel technique has been applied to ultrathin gate oxide CMOS transistors. It was confirmed that drain current drive and transconductance are improved in the epitaxial channel MOSFETs with ultrathin gate oxides in the direct-tunneling regime. It was also found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current. The relation between channel impurity concentration and direct-tunneling gate leakage current was investigated in detail. It was confirmed that the lower leakage current in epitaxial channel devices was not completely explained by the lower impurity concentration in the channel. The results suggest that the improved leakage current in the epitaxial channel case is attributable to the improvement of some aspect of the oxide film quality, such as roughness or defect density, and that the improvement of the oxide film quality is essential for ultrathin gate oxide CMOS. AFM and 1/f noise results support that SiO₂-Si interface quality in epitaxial Si channel MOSFETs is improved. Good performance and lower leakage current of TiN gate electrode CMOS was also demonstrated     

Characteristics of sub-1/4-μm gate surface channel PMOSFET'susing a multilayer gate structure of boron-doped poly-Si on thinnitrogen-doped poly-Si

This paper reports the effects of a new p⁺ gate structure (MBN gate) on the properties of surface channel PMOSFET's with an extremely thin gate oxide. The MBN gate is a multilayer gate structure of boron-doped poly Si on thin nitrogen-doped poly-Si. The thin nitrogen-doped Si layer effectively suppresses boron diffusion, so that the gate poly Si can be doped with boron in high concentration without the fear of boron penetration. Gate depletion effects are well suppressed. Effective hole mobility is improved due to the reduction of the initial interface state density. The hot-hole induced interface state generation is shown to be the dominant clause of degradation in the 1/4-μm level PMOSFET's, and less Gm degradation is found in the MBN-gate PMOSFET's than in conventional p⁺-gate PMOSFET's. Finally, with respect to the reliability of the gate oxide, a conventional p⁺ gate with boron penetration exhibits an increase in short-time defect related breakdown during constant-current FN stressing. Short-time defect-related breakdown is not observed in the MBN gate but a slight decrease in charge to breakdown     

Thickness optimization of the TiN metal gate with polysilicon-capping layer on Hf-based high-k dielectric

An optimal thickness of the metal nitride (TiN) film capped by polysilicon for the MOSFET gate electrode application is investigated. Interface trap density, which depends on the TiN film thickness and transistor channel length is suggested to be controlled by mechanical stress of the metal layer after full transistor processing including high temperature annealing. Thinner TiN gate electrode was found to have lower interface trap density. Thicker TiN, however, showed better barrier properties for impurity diffusion from the polysilicon-capping layer. We found that 10 nm is the optimum thickness of the ALD TiN layer for minimizing charge trapping and adequate blocking of boron penetration.     

Improving gate-oxide reliability by TiN capping layer on NiSi FUSI metal gate

The impact of TiN capping layer on gate oxide reliability of NiSi fully silicided metal gate was investigated. It was found that the TiN capping layer significantly improved V/sub th/ stability and oxide reliability during negative bias temperature stress. Better life-time performance was also extrapolated for the samples with TiN capping layer.     

Composite TiSi2/n + poly-Si low-resistivity gate electrode and interconnect for VLSI device technology

A composite polycide structure consisting of refractory metal silicide film on top of polysilicon has been considered as a replacement for polysilicon as a gate electrode and interconnect line in MOSFET integrated circuits. This paper presents fine-line patterning techniques and device characteristics of MOSFET's with a TiSi2polycide gate. A coevaporated TiSi2polycide gate was chosen for this study because it had 2 to 5 times lower resistivity as compared to other silicides. Polycide formation by electron-beam coevaporation is chosen in preference to sputtered TiSi2because of lower oxygen contamination. The coevaporation technique to form TiSi2polycide with a sheet resistivity of 1 Ω/square (bulk resistivity of 21 µΩ.cm) is described. Anisotropic etching of nominally 1-µm lines with a 15:1 etch selectivity against oxide is reported. Measurements of metal-semiconductor work function, fixed oxide charge density, dielectric strength, oxide defect density, mobile-ion contamination, threshold voltage, and mobility have been made on polycide structures with 25-nm gate oxides. These MOS parameters correspond very closely to those obtained for n+ poly-Si gates. In addition, the specific contact resistivity between Al and TiSi2polycide is lower than the contact resistivity between Al and polysilicon by one order of magnitude.     

SrHfO3 as gate dielectric for future CMOS technology

Thin epitaxial films of the high-κ perovskite SrHfO₃ were grown by molecular beam epitaxy on Si(100) and investigated by ellipsometry and X-ray photoelectron spectroscopy to determine its band gap and valence band offset. Conducting AFM shows a good correlation between topography and current mapping, pointing to direct tunneling conduction. Long channels MOSFETs with low equivalent oxide thickness (EOT) were fabricated and their channel mobility measured. Mobility enhancement can be achieved by post processing annealing in various gases but at the cost of interfacial regrowth. An alternative approach is to increase mobility without changing EOT is by electrically stressing the gate dielectric at ∼150 °C.     

Dual-metal gate CMOS technology with ultrathin silicon nitride gatedielectric

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si₃N₄) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO₂) are observed