DDFSGEN

This paper presents a functional compiler for the automatic design of Direct Digital Frequency Synthesizer (DDFS) integrated circuits (ICs) using a ROM based table look-up architecture. The compiler allows the user to specify high-level specifications such as the acceptable spurious response and it generates the IC architecture, floorplan, and layout. To construct the layout for different specifications, a library of parameterized macrocells has been developed in 1.2 μm CMOS technology. A test chip with a quadrature DDFS module has been generated, using the compiler, and fabricated. The chip has two input signals: one is for frequency control while the other is for phase initialization. Input and output word lengths are 16 bits and 6 bits respectively. The chip complexity is approximately 12,000 transistors (DDFS core) and the die size is 4.8×2.9mm ². A maximum sample rate of 80 MHz has been attained implying a maximum sine (cosine) output frequency of 40 MHz and a frequency resolution of 1.22 kHz. The maximum spurious level measured is ?46 dB.     

A 12-Bit Nonlinear DAC for Direct Digital Frequency Synthesis

A 12-bit nonlinear digital-to-analog converter (DAC) was fabricated in a 0.35-$mu$m SOI CMOS process. The nonlinear DAC can implement a piecewise-linear approximation to a sine function and results in significant reduction of complexity and power dissipation when used in direct digital frequency synthesizers (DDFSs). The DDFS look-up table only needs to store offset and gain values for each segment. The look-up table size can be reduced from 11K bits to 544 bits for a 12-bit DDFS with 72 dB spurious-free dynamic range (SFDR). The nonlinear DAC consists of a 12-bit binary-weighted offset DAC and a multiplying DAC. The DACs use a current steering architecture for high-speed operation and the 5 most significant bits of the offset DAC are unary encoded to reduce glitches. The multiplying DAC consists of binary-weighted current sources switched by the partial products of the inputs. Test results show that the DAC has 12-bit accuracy after digital trimming, operates up to 600 MS/s and provides differential outputs of 0.5 V into 50 $Omega$ loads. The SFDR is over 60 dBc below 20 MHz with a maximum of 72 dBc. Radiation tests show the nonlinear DAC can tolerate a total ionizing dose of 200 Krad Si.      

A low-power direct digital frequency synthesiser

This work presents a low power direct digital frequency synthesiser (DDFS) by using a new two-level lookup table algorithm. The algorithm uses trigonometric double angle formula to divide lookup table ROM into two parts. The ROM size of the proposed architecture is 25% less than that of conventional lookup table DDFS. The hardware of new DDFS architecture compared to the traditional two-level table DDFS also requires less one multiplication. A synthesised 0.35 µm DDFS with an spurious free dynamic range of ?80 dB, runs up to 100 MHz and consumes 81 mW at 3.3 v. The power efficiency is 0.81 mW MHz^?1, which represents an enhancement of more than 38% compared to the conventional DDFS.     

An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter

An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase-to-sine converters, and a D/A converter. The high-speed operation of the DDFS is enabled by applying parallelism to the phase-to-sine converter and by including a D/A converter in a single chip. The on-chip D/A converter saves delay and power consumption due to interchip interconnections. The DDFS considerably reduces power consumption by using several low-power techniques. The pipelined parallel accumulator consumes only 22% power of a conventional pipelined accumulator with the same throughput. The quad line approximation (QLA) and the quantization and error ROM (QE-ROM) minimize the ROM to generate a sine wave. The QLA saves 4 bits of the sine amplitude by approximating the sine function with four lines. The QE-ROM quantizes the ROM data by magnitude and address and then it stores the quantized values and the quantization errors separately. The ROM size for a 9-bit sine output is only 368 bits. A DDFS chip is fabricated in a 0.35-/spl mu/m CMOS process. It consumes only 174 mW at 800 MHz with 3.3 V. The chip core area is 1.47 mm/sup 2/. The spurious-free dynamic range (SFDR) is 55 dBc.     

多通道高速直接数字频率合成器

本文提出了一款具有32位相位精度,输出12位精度的高性能直接数字频率合成器。该直接数字频率合成器通过多通道采样技术和12位精度的数模转换器,使其同时具有高速和高精度的特性。该芯片采用130nm标准CMOS工艺制造,核心区域面积为0.89mm×0.98mm,在1.2V单电源供电情况下,总功耗约为300mW,室温条件下,最大时钟工作频率为2.0GHz。     

基于FPGA的低杂散小容量DDFS设计

研究传统的DDFS频谱杂散分量,分析了杂散分量的来源和传统相位抖动除噪技术的缺点,提出了对相位舍入分解进行Taylor展开的DDFS改进结构。同时该结构采用循环相位累加器等结构,降低了杂散分量,提高了频率精度,压缩了ROM的容量。FPGA上的实现表明该结构能有效降低杂散,能使SDFR比采用相位抖动除噪的方法扩大30 dB,同时ROM的容量比传统结构压缩了4倍以上。     

A low-power segmented nonlinear DAC-based direct digital frequency synthesizer

A 2.5-V CMOS direct digital frequency synthesizer (DDFS) with 12 bits of phase resolution and 11 bits of amplitude resolution is presented. Low power consumption is achieved using a nonlinear digital-to-analog converter (DAC). To further reduce power and area, a new technique is proposed to segment the non-linear DAC into a coarse nonlinear DAC and a number of fine nonlinear sub-DACs. The DDFS fabricated in a 0.25-/spl mu/m CMOS process occupies an active area of 1.4 mm/sup 2/. For a clock frequency of 300 MHz, it consumes 240 mW and the spurious-free dynamic range is less than 51 dB for output frequencies up to 3/8 of the clock frequency.     

A low-glitch binary-weighted DAC with delay compensation scheme

This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers to drive a lot of current switches and re-timing latches, the proposed design uses variable-delay buffers with a compact layout to compensate for the delay difference among different bits, and to reduce glitch energy from 132 to 1.36 pV s during major code transitions. The measured spurious free dynamic range (SFDR) has been improved over 10 dB, as compared to DACs without variable-delay buffers. At 250 MS/s update rate, the proposed DAC achieves 56 dB SFDR for 0.67 MHz output frequency and 49 dB SFDR for 94 MHz output frequency with 50 Ω termination. For static performance, the measured integral nonlinearity (INL) and differential nonlinearity (DNL) is less than 1.6 and 1.8 LSB, respectively. The proposed DAC can be used in various applications in industry, including digital video, digital TV, wireless communication system, etc. This chip was implemented in TSMC 1P6M 0.18 μm CMOS technology and dissipates 19 mW from a single 1.8 V power supply.     

Efficient, ROM-less DDFS using non-linear interpolation and non-linear DAC

A non-linear interpolation based ROM-less Direct Digital Frequency Synthesisiser (DDFS) is more efficient than previous systems as each current cell in a non-linear DAC is used more effectively. This was achieved by forming an analogue voltage from a small linear DAC addressed by phase bits that are usually discarded. The analogue voltage was connected to a selected current source in a thermometer decoded non-linear DAC to allow non-linear interpolation between the conventional, phase limited output levels. By increasing the number of phase bits the spurious free dynamic range (SFDR) was improved without increasing the size of the non-linear DAC. Modelling and simulation of the non-linear response of the differential switch based current cell revealed suitable parameters. The architecture of 64 current cells used a modified thermometer decoder and three-state switch in each current cell. Simulation and testing of 10 sample circuits demonstrated a robust DDFS with SFDR better than −60 dBc and suitable for use in a wide range of instrumentation systems.     

Design of New DSP Instructions and Their Hardware Architecture for High-Speed FFT

This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture for high-speed FFT. The instructions perform new operation flows, which are different from the MAC (Multiply and Accumulate) operation on which existing DSP chips heavily depend. This paper proposes the DPU (Data Processing Unit) supporting the instructions and shows it to be two times faster than existing DSP chips for FFT. The architecture has been modeled by the Verilog HDL and logic synthesis has been performed using the 0.35 m standard cell library. The maximum operating clock frequency is about 144.5 MHz and the architecture will be employed on an application-specific DSP chip.     

A direct digital synthesizer with an on-chip D/A-converter

A direct digital synthesizer (DDS) with an on-chip D/A converter is designed and processed in a 0.8 μm BiCMOS. The on-chip D/A converter avoids delays and line loading caused by interchip connections. At the 150 MHz clock frequency, the spurious free dynamic range (SFDR) is better than 60 dBc at low synthesized frequencies, decreasing to 52 dBc worst case at high synthesized frequencies in the output frequency band (0-75 MHz). The DDS covers a bandwidth from DC to 75 MHz in steps of 0.0349 Hz with the frequency switching speed of 140 ns. The chip has a complexity of 19100 transistors with a die/core area of 12.2/3.9 mm². The power dissipation is 0.6 W at 150 MHz at 5 V. The maximum operating clock frequency of the chip is 170 MHz     

一种用于铷频标的紧凑型直接数字频率合成器

研发了高精度铷频标芯片SoC实现中应用的一种紧凑型直接数字频率合成器(DDFS).为了减小芯片面积和降低功耗,采用正弦对称技术、modified Sunderland技术、正弦相位差技术、四线逼近技术以及量化和误差ROM技术对相位转正弦的映射数据进行了压缩.利用这些技术,ROM尺寸压缩了98%.采用标准0.35μm CMOS工艺,一个具有32位相位存储深度和10位DAC的紧凑型DDFS流片成功,其核心面积为1.6mm2.在3.3V电源下,该芯片的功耗为167mW,无杂散动态范围(SFDR)为61dB.     

A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-$mu$m CMOS

A wideband frequency synthesizer architecture is presented. The proposed topology employs a direct digital frequency synthesizer (DDFS) to control the output frequency of an offset-PLL. In this way, the synthesizer features a very fine frequency resolution, 24 Hz, as in delta-sigma fractional-N PLLs, but without being affected by the quantization-induced phase noise. This, in turn, allows enlarging the loop bandwidth. The frequency synthesizer is designed to be employed as a direct modulator for Bluetooth transmitter in a low-cost 0.35-mum CMOS technology. At 2.5GHz it achieves 1.8-MHz bandwidth, while the settling time within 30ppm for an 80-MHz step is 3 mus. The integrated phase noise gives less than 1 degree of rms phase error and the worst-case spur is 48dBc at 1 MHz, well below the specifications. Power dissipation is 120 mW for the PLL core, 50 mW for the DDFS plus DACs, and 19 mW for the GFSK modulator.     

一种基于0.35m工艺的高速混合旋转结构DDFS

设计实现了一种基于CORDIC算法和乘法器的直接数字频率合成器。采用混合旋转算法实现相位幅度转换,最高工作频率达到400MHz。在算法级,将DDFS中需要执行的π/4旋转操作分成两次旋转完成,第一次旋转采用CORDIC算法,第二次旋转采用乘法器来完成,同时采用流水线结构来实现累加器,提高整体性能。在晶体管级,采用DPL(Double-pass-transistor logic)逻辑实现基本电路单元,减少延迟提高速度。经0.35μmCMOS工艺流片,在400MHz的工作频率下,输出信号在80MHz处,SFDR为76.47dB,整个芯片面积为3.4mm×3.8mm。     

CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications

Using a 3.5-/spl mu/m gate length complementary metal-oxide-semiconductor/silicon-on-sapphire technology, a single-chip, radiation-hardened, direct digital frequency synthesizer has been developed. The circuit is a critical component of a fast-tuning wideband frequency synthesizer for spread spectrum satellite communications. During each clock period the chip generates a new digitized sample of a sine wave, whose frequency is variable in 2/SUP 20/ steps from DC to one-half the clock frequency. Operation at up to 7.5 MHz is possible in a worst-case environment, including ionizing radiation levels up to 3/spl times/10/SUP 5/ rads(Si). A computationally efficient algorithm was chosen, resulting in 12-bit output precision with only 1084 logic gates and 3840 bits of on-chip read-only memory. The accuracy of the algorithm is sufficient to maintain in-band spurious frequency components below -65 dBc. At 300 mW, the chip replaces an MSI implementation which uses 25 integrated circuits and consumes 3.5 W.     

Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture

This paper presents an efficient real-time variable block size motion estimation architecture. The proposed architecture provides motion vectors for each 16 $times$ 16 block and its 40 sub-blocks. The proposed architecture is a single-instruction multiple-data architecture integrated with embedded SRAMs on one chip. The architecture has been prototyped using Xilinx Virtex-4 XC4VSX35-10 field-programmable gate array. It processes 30-CIF fps using 71-MHz clock frequency. Its maximum clock frequency is 187.7 MHz and the maximum throughput is 20 4CIF fps. The prototyped architecture has 175 k gates and 18 kbits embedded SRAM.      

Low-power direct digital frequency synthesis for wirelesscommunications

A low-power direct digital frequency synthesizer (DDFS) architecture is presented. It uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity 29-Hz frequency resolution, and 9-bit output data for sine function generation is being implemented in 0.8-μm CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V)     

A 1.2-MHz 10-bit Continuous-Time Sigma–Delta ADC Using a Time Encoding Quantizer

This paper shows the operating principle and experimental results of a new continuous-time sigma–delta modulator architecture. The proposed modulator does not require a multibit quantizer nor a mismatch-shaping digital-to-analog converter to produce a multibit noise-shaped output. Instead, its quantizer encodes the loop filter output in a binary signal using a time encoding technique similar to pulsewidth modulation. This binary signal is used to generate both the analog feedback loop signal and the digital output. A proof-of-concept chip in 0.35-${rm mu}{hbox{m}}$ CMOS achieves 10 bits of resolution within a signal bandwidth of 1.2 MHz using a first-order modulator.      

Novel Analog Calibration Technique for Current-Steering DACs’ Dynamic Performance

This paper reports the post-layout dynamic performance of a novel calibration technique for current-steering digital-to-analog converter that was proposed previously. This technique not only improves the linearity, but it does so with low power as well as a very low area. It uses an analog feedback loop consisting of four transistors to calibrate each bit of the DAC, and the same feedback circuit is used for all the bits, thus significantly saving the chip area. Layout of the 10-bit calibrated CS DAC circuit was done in a 180-nm technology; the total area of the DAC and the calibration circuit together was 0.16 \(\hbox {mm}^{2}\). Simulation results show that the spurious free dynamic range is 62 dB for signals of 1 MHz at a sampling frequency of 100 MS/s.