面向裕量优化的高效时钟偏差规划和延迟提取

为了减少时钟偏差规划所需的时间,提出一种准线性时间复杂度的时钟偏差规划方法.该方法以整数来描述延迟大小的时钟偏差规划算法,限制每次对时钟延迟调整的步进至少为1,降低了算法的时间复杂度;改变了传统的预先生成完整的时序图作为算法输入的流程,采用一种新的增量式延迟提取策略为时钟偏差规划算法提取关键边的权重,减少了生成时序图所需要的时间.实验结果表明,采用文中方法进行时钟偏差规划的效率很高,对包含数千触发器的基准测试电路,其运行时间仅为数十秒.     

工艺参数变化下的基于统计时序分析的时钟偏差安排

针对工艺参数变化的情况,提出一种成品率驱动的时钟偏差安排算法.提出统计时序约束图的概念,利用统计时序分析的结果将时序电路转换为统计时序约束图;将寻找关键环问题转换为最小费用/时间比值环问题,并按比例分配关键环中的时钟偏差的安全余量.实验结果表明,该算法有助于提高集成电路的成品率.     

考虑预采样的时序错误检测与自恢复方法

集成电路老化效应会导致组合电路关键路径时延增加,不满足电路时序约束条件,从而引起时序错误,使得电路功能失效.为此,提出一种基于预采样的时序错误检测与自恢复方法,并设计了一个检测与纠错结构.首先利用系统本身时钟在时钟有效沿前后构建一个预采样区间和一个检测区间;然后在预采样区间内提前捕获输入信号;最后在检测区间内进行时序错误检测,如果检测电路发出报警信号,电路将会进行自纠错.仿真结果表明,相比于其他的检测结构,该结构在检测速度上平均提高了3.6倍;同时不需要调整时序,电路就可以实现自纠错与自恢复,且不会降低电路的工作性能.     

RTL电路的时序优化设计

时序设计是数字系统性能的关键,在高层设计方法中对时序的控制进一步抽象,我们在介绍电路时钟和时序的基础上分析了RTL电路的时序模型,该模型讨论了RTL电路的时延路径、建立保持时间以及瞠工作的条件,并据此提出了相应的设计策略,通过实践证明这种设计方法是行之有效的。     

基于H .264/AVC解码芯片的静态时序分析约束设计

作为分析和验证电路时序行为的重要手段,静态时序分析（ STA）技术在深亚微米级ASIC设计中得到了广泛的应用,而正确的时序约束输入是时序分析工具给出正确结果的必要条件之一。文中在介绍 STA 原理的基础上,以一款H.264/AVC解码芯片为例,分析了解码芯片的时钟结构等时序信息,详细介绍了时钟定义、端口信号等关键时序约束,并重点介绍了PLL时钟偏差的约束设计。时序分析工具PT分析及与动态仿真的交叉验证的结果表明,解码芯片时序约束设计完整、正确。     

一种CDC信号滑动窗口时序分析方法

异步时钟域设计中CDC信号的时序分析及收敛是超大规模高频数字电路设计功能正确的重要保证。为了减少设计面积,提出了一种CDC信号滑动窗口时序分析方法,该方法在每种corner的每条CDC通路上单独设置适当的时序约束窗口进行时序计算与分析,有效避免了常用的固定约束分析方法由于约束条件过严导致的虚假时序违反及不必要的时序修复,而使设计面积增大的问题,减轻了CDC电路的后端设计工作量。在16 nm工艺下的实验结果表明,该方法在时钟树偏差较大时与固定约束分析方法相比显著节省了设计面积。     

一种基于寄存器翻转时刻随机化的抗DPA攻击技术

在密码算法电路中寄存器翻转时刻随机化对芯片抗DPA(differential power analysis)攻击能力有很大影响,因此提出了一种基于寄存器翻转时刻随机化的抗DPA攻击技术,其核心是利用不同频率时钟相位差的变化实现电路中关键寄存器翻转时刻的随机变化.针对跨时钟域的数据和控制信号,提出了需要满足的时序约束条件的计算方法,同时还分析了不同时钟频率对寄存器翻转时刻随机化程度的影响.以AES密码算法协处理器为例,实现了所提出的寄存器翻转时刻随机化技术,通过实验模拟的方法验证了理论分析的正确性.实验结果显示,在合理选择电路工作时钟频率的情况下,所提出的技术能够有效提高密码算法电路的抗DPA攻击性能.     

改进的基于属性不变量生成和数学归纳法的时序逻辑优化算法

为了在时序逻辑综合中使电路面积和关键路径延迟同时得到快速优化,提出一种改进的基于假设后验证的时序优化算法.在位并行随机模拟提取候选属性不变量之前,利用寄存器共享来降低初始候选不变量数目,以减少SAT程序的频繁调用;然后利用推测化简模型和改进的数学归纳法将基本条件和归纳步骤合并处理,有效地降低了电路规模和关键路径延迟,同时提高了算法运行速度.实验数据表明,文中算法使寄存器和节点规模平均下降41％和48％,关键路径延迟减小30％;与同类方法相比,该算法运行时间平均下降17％.     

基于IFM PLC内置计时器的时序控制研究

IFM PLC在工程机械行业的电气系统中广为应用,但其时序控制偏差一直困扰着控制系统设计人员。针对IFM PLC时序控制的偏差问题,根据Codesys编程环境中使用内置计时器的不同情况,对问题进行深入研究,指出了产生问题的根本原因。并基于内置计时器的特性及使用场景,提出了几种控制偏差的方法,实现了时序偏差的精确控制,在提高了时序控制精确度的同时,降低了由于时序问题产生BUG的可能性,保证设备电气性能的及时性和准确性。最后利用实例验证了该时序控制方法的可行性及有效性。     

DDR源同步接口的设计与时序约束方法

在高速I/O接口的设计中,DDR源同步接口的应用越来越广泛,因其在相同时钟频率下的数据带宽是SDR接口的两倍.由于DDR接口电路时序的复杂性,对其进行正确的时序约束也成为静态时序分析中的一个难点.结合曙光5000ASIC中的chipsct芯片,详细介绍了DDR源同步接口的设计,并且利用Synopsys公司的静态时序分析软件PrimeTime,对DDR接口接收端和发送端的时序约束方法进行了具体的分析说明.     

Hierarchical timing verification system

A hierarchical timing verification system, based on critical path analysis technique, is described. These techniques permit the system to identify the critical paths of the logic designs. The system performs timing analysis on VLSI designs with sequential circuits and feedback loops. The system traces the design both in the forward and backward directions and computes the arrival times and required arrival times at the primary inputs and primary outputs of the design. The results are applicable to hierarchical VLSI design methodologies. This system has been tested using the logic of Sperry's 1100 series mainframe computer system.     

Revisiting timing in process algebra

We shortly review the framework of process algebras with timing presented by Baeten and Middelburg [Handbook of Process Algebra, Elsevier, 2001, Chapter 10]. In order to cover processes that are capable of performing certain actions at all points in some time interval, we add integration to the process algebra with continuous relative timing from this framework. This extension happens to reveal some points that are peculiar to relative timing. We go into these points. The most flagrant point is that, unlike in case of absolute timing, discretization cannot be added to the extension without first adding a mechanism for parametric timing like initial abstraction.     

Compaction with general synchronous timing

In current microcode generation systems, one simplification that is frequently made is to assume an absence of timing restrictions. It is critical that timing is considered when the target architecture involves branch delays, volatile registers, or microoperations requiring multiple microinstructions to complete. A general form for representing synchronous timing in clocked microarchitectures and methods of compacting data-dependency graphs with general timing are described     

时间约束工作流的可调度性分析

提出一种时间约束工作流的可调度性分析方法。针对时间约束Petri网（Timing Constraint Petri Nets,TCPN）为普通Petri网无法建模多参与资源的不足,给出了扩展的时间约束Petri网（w-TCPN）的定义;结合w-TCPN的拓扑结构,从模型和实例两个层次,给出了w-TCPN变迁可调度的判定定理;提出了时间约束的调整策略。w-TCPN的研究使得时间约束工作流的建模和可调度性分析更加合理。     

Acquiring and incorporating state-dependent timing requirements

Some real-time systems are designed to deliver services to objects that are controlled by external sources. Their services must be delivered on a timely basis, and the system fails when some services are delivered too late. In general, the timing requirements of the system may change when the states of the objects monitored by the system change. Such a system may fail if the timing requirements which it is designed to meet are erroneous. It may underutilize resources and consequently be costly or unreliable if the requirements are too stringent. Hence, one must identify how changes in object states call for changes in system requirements and how these changes should be incorporated into the design and implementation of the system. This paper first describes a methodology to determine timing requirements and to take into account requirement changes at runtime. The method is based on several timing requirement determination schemes. Simulation data show that these schemes are effective for applications such as mobile IP hand-offs. The paper then discusses how to incorporate this methodology in the system architecture and in the development process.

Handling timing errors in distributed programs

The authors describe a tool called TAP, which is defined to aid the programmer in discovering the causes of timing errors in running programs. TAP is similar to a postmortem debugger, using the history of interprocess communication to construct a timing graph, a directed graph where an edge joins node x to node y if event x directly precedes event y in time. The programmer can then use TAP to look at the graph to find the events that occurred in an unacceptable order. Because of the nondeterministic nature of distributed programs, the authors feel a history-keeping mechanism but always be active so that bugs can be dealt with as they occur. The goal is to collect enough information at run time to construct the timing graph if needed. Since it is always active, this mechanism must be efficient. The authors also describe experiments run using TAP and report the impact that TAP's history-keeping mechanism has on the running time of various distributed programs     

EMCCD时序发生器的VHDL设计

具有电子倍增功能的CCD图像传感器在微光探测与成像领域获得了极大的成功。分析了该TC285SPD EMCCD用于微光成像时的控制要求,并结合模拟前端信号处理器AD9845B的时序控制要求,采用VHDL语言进行编程,实现了对该EMCCD的驱动控制。详细介绍了EMCCD时序发生器的VHDL设计方法和实现过程,在Quartus II环境下给出了系统的仿真结果,并对结果进行了分析讨论。     

Verifying timing consistency in formal specifications

The authors' algorithm formally verifies the rule set that expresses timing discipline in digital system specifications. Their algorithm is based on a higher level behavioral specification model and concerns formal consistency verification at the design level of the system specification development procedure