A novel polysilicon thin-film transistor with a p-n-p structuredgate electrode

We propose and fabricate a novel polycrystalline silicon thin-film transistor (poly-Si TFT) which exhibits the properties of an offset gated structure in the OFF state, while acting as a nonoffset structure in the ON state. The fabrication process is compatible with the conventional nonoffset poly-Si TFT's process and does not require any additional mask. Experimental results show that the leakage current of the new device is two orders of magnitude lower than that of the nonoffset gated device, while the ON current of the new device is almost identical to the nonoffset gated device. It is observed that the ON/OFF current ratio of the proposed poly-Si TFT is improved remarkably     

Novel offset gated poly-Si TFTs with subgate

We have fabricated a new offset gated poly-Si TFT by employing photoresist reflow, have measured various experimental data of the new device, such as hydrogenation results and high-frequency characteristics, and have analyzed device characteristics as a function of driving frequency. Our devices have a unique gate pattern and the hydrogenation effect is somewhat different from the previous results. Our experimental results suggest that with the same offset length, the device with a wider space between the maingate and the subgate is more advantageous for hydrogenation. Experimental results show that the leakage current of the new device is two orders of magnitude lower than that of the nonoffset gated device, while the ON current of the new device is almost identical to the nonoffset gated device in the typically used frequency range (10-100 kHz)     

A novel gate-overlapped LDD poly-Si thin-film transistor

We fabricate a new polycrystalline silicon thin-film transistor (poly-Si TFT), called a gate-overlapped lightly doped drain (GO-LDD) TFT, which reduces the leakage current without sacrificing the ON current. A new GO-LDD TFT, of which the electrical characteristics are tolerable to the change of LDD doping concentration, can be easily fabricated by employing the buffer oxide without any additional LDD implantation. The change of ON current due to the misalignment of the LDD region may be eliminated. Experimental results show that the leakage current of the proposed TFT's is reduced by two orders of magnitude, compared with that of conventional nonoffset TFT, while the ON current is not decreased. It is observed that the ON/OFF current ratio is not changed significantly with LDD doping concentration and LDD length     

Active-gate thin-film transistor

A thin-film transistor (TFT) with a lightly-doped offset built in the polysilicon gate is proposed. The offset region of the gate acts as a dielectric in the OFF state and as a conductor in the ON state. The unwelcome peak of the electric field near the drain in the OFF state is significantly reduced, as has been confirmed by two-dimensional device simulation. The key advantage of this device over conventional passive offset structures is that the ON current is not reduced, while the OFF current is suppressed by several orders of magnitude     

Gate-overlapped lightly doped drain poly-Si thin-film transistorsfor large area-AMLCD

We have fabricated a gate-overlapped lightly doped drain (GO-LDD) polycrystalline silicon thin-film transistor (poly-Si TFT) applicable for large area AMLCD by employing the uniform and low-temperature doping techniques, such as ion shower doping and in situ doping. Experimental results show that the leakage current of the proposed TFT's is reduced by more than the magnitude of two orders, compared with that of conventional nonoffset TFT, while the ON current is scarcely decreased. It is verified by the device simulator that the electron concentration in the LDD region is increased under the ON state and decreased under the OFF state due to the field plate with gate potential over the LDD region. Furthermore, the vertical peak electric field in the LDD region is decreased significantly by the extended field plate potential during the OFF state. It is observed that the gate bias stress degrades significantly the subthreshold slope of the ion shower doped GO-LDD TFT's at the low drain bias but does not degrade the device characteristics of those with in situ doping due to the high-quality TEOS SiO₂ interlayer     

Characteristics of offset-structure polycrystalline-siliconthin-film transistors

In order to reduce anomalous leakage current from n-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs), an offset structure that has an n^- region between channel and n⁺ source-drain electrodes has been proposed. Drain-current measurements of the poly-Si TFT prove that the offset structure is effective in reducing the anomalous leakage current, and that the optimization of the offset length and the doping concentration in the offset region enlarge the ON/OFF current ratio. Implantation of 5×10¹³ cm^-2 phosphorus ions in the offset region makes the ON/OFF current ratio more than one order of magnitude larger than that of conventional structure TFTs     

A novel offset gated polysilicon thin film transistor without anadditional offset mask

We have proposed a novel offset gated polysilicon TFT fabricated without an offset mask in order to reduce leakage current and suppress the kink effect. The photolithographic process steps of the new TFT device are identical to those of conventional non-offset structure TFT's and an additional mask to fabricate an offset structure is not required in our device. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The novel TFT also exhibits a considerable reduction in the kink effect because a very thin film TFT may be easily fabricated due to the elimination of the contact over-etch problem     

Novel Offset-Gated Bottom Gate Poly-Si TFTs With a Combination Structure of Ultrathin Channel and Raised Source/Drain

We propose an offset-gated bottom gate polycrystalline silicon thin-film transistor (TFT), with a combination structure of ultrathin channel and raised source/drain, employing a simple process of the back surface exposure. It is experimentally and simulatively demonstrated that the new device has lower leakage current and better saturation characteristics, as compared with the conventional non offset TFT, due to the lateral electric field near the drain, which is reduced by the proposed structure. Moreover, the proposed TFT exhibits much better ON/OFF current ratio because the high current drive due to the raised source/drain structure is enough to compensate for the ON-state current reduction due to the offset-gate structure.     

A novel self-aligned poly-Si TFT with field-induced drain formed by the damascene Process

We have proposed and fabricated a self-aligned polysilicon thin-film transistor (poly-Si TFT) with a thick dielectric layer at the gate edges near the source and drain. A T-shaped polysilicon gate was successfully formed by the damascene process used in VLSI interconnection technology. During the on state, an inversion layer is induced by the subgate as a drain so that the on current is still high and the poly-Si region under the subgate behaves as an offset, reducing the off-state leakage current during the off-state. As the subgate dielectric becomes 3.5 times thicker than the main gate oxide, the minimum off-state leakage current of the new TFT is decreased from 1.4/spl times/10/sup -10/ to 1.3/spl times/10/sup -11/ without sacrifice of the on current. In addition, the on-off current ratio is significantly improved.     

A new poly-Si TG-TFT with diminished pseudosubthreshold region: theoretical investigation and analysis

In this paper, we have proposed a new poly-Si triple-gate thin-film transistor (TG-TFT) where the front gate consists of two materials and three sections in order to reduce the OFF state leakage current without affecting the ON state voltage. We have used one and three grain-boundaries in the channel for analyzing the electrical characteristics of the poly-Si TG-TFT. The key idea in this paper is to make the dominant conduction mechanism in the channel to be controlled by the accumulation charge density modulation by the gate and not by the gate-induced grain barrier lowering. As a result, we demonstrate that the TG-TFT exhibits a highly diminished pseudosubthreshold region resulting in a substantial OFF state leakage current without any significant change in the ON voltage when compared to a conventional poly-Si TFT (C-TFT). Using two-dimensional and two-carrier device simulation, we have examined various design issues of the TG-TFT and provided the reasons for the improved performance.     

A p-channel poly-Si/Si1-xGex/Si sandwichedconductivity modulated thin-film transistor

A p-channel poly-Si/Si_1-xGe_x/Si sandwiched conductivity modulated thin-film transistor (CMTFT) is proposed and demonstrated in this paper for the first time. This structure uses a poly-Si/Si_1-xGe_x/Si sandwiched structure as the active layer to avoid the poor interface between the gate oxide and the poly-Si_1-xGe_x material. Also an offset region placed between the channel and the drain is used to reduce the leakage current. Furthermore, the concept of conductivity modulation in the offset region is used to provide high on-state current. Results show that this structure provides high on-state current as well as low leakage current as compared to that of conventional offset drain TFTs. The on-state current of the structure is 1.3-3 orders of magnitude higher than that of a conventional offset drain TFT at a gate voltage of -24 V and drain voltage ranging from -15 to -5 V while maintaining comparable leakage current     

Electrical characteristics of new LDD poly-Si TFT structuretolerant to process misalignment

A new lightly doped drain (LDD) poly-Si TFT structure having symmetrical electrical characteristics independent of the process induced misalignment is described in this paper. Based on the experimental results, we have established that there is no difference between the bi-directional I_D-V_G characteristics, and a low leakage current, comparable to a conventional LDD poly-Si TFT, has been maintained for this new poly-Si TFT. The maximum ON/OFF current ratio of about 1×10⁸ is obtained for the LDD length of 1.0 μm. In addition, the kink effect in the output characteristics has been remarkably improved in the new TFTs in comparison to the conventional non-LDD single- or dual-gate TFTs     

A Center-Offset Polycrystalline-Silicon Thin-Film Transistor With ${rm n}^{+}$ Amorphous-Silicon Contacts

We have studied a bottom-gate polycrystalline-silicon thin-film transistor (poly-Si TFT) with amorphous-silicon (a-Si) ${rm n}^{+}$ contacts and center-offset gated structure, where intrinsic poly-Si is used in the center-offset region. The fabrication process is compatible with the conventional a-Si TFT with addition of thermal annealing for crystallization of a-Si. The bottom-gate poly-Si TFT with a 5-$muhbox{m}$ offset length exhibited a field-effect mobility of 18.3 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$ and minimum OFF-state current of $hbox{2.79} times hbox{10}^{-12} hbox{A}/muhbox{m}$ at $V_{rm ds} = hbox{5} hbox{V}$. The leakage currents are two orders of magnitude lower than those of a nonoffset TFT with mobility drop from 23.8 to 18.3 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$.      

Characteristics of p-channel polysilicon conductivity modulatedthin-film transistors

A p-channel polysilicon conductivity modulated thin-film transistor (CMTFT) is demonstrated and experimentally characterized. The transistor uses the concept of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. The conductivity modulation is achieved by injecting minority carriers (electrons) into the offset region through a diode added to the drain. Experimental results show that the conductivity modulation in the p-channel device is as effective as that in the n-channel device. This structure can provide 1.5 to 2 orders of magnitude higher on-state current than that of the conventional offset drain thin-film transistor (TFT) at drain voltage ranging from -15 V to -5 V while still maintaining low leakage current and simplicity in device operation. The p-channel CMTFT can be combined with the n-channel CMTFT to form CMOS high-voltage drivers, which is very suitable for use in fully integrated large-area electronic applications     

Floating-island TFT leakage caused by process step reduction

The leakage mechanism for a top-gate thin-film transistor (TFT) produced using the fewest process steps in the industry is analyzed in order to achieve a high-contrast liquid crystal display (LCD). Using a T-shaped TFT structure, the OFF and ON channel lengths are defined independently, so that the leakage can be reduced with no ON current decrease     

A low-leakage-current CdSe thin film transistor

This paper reports the design, fabrication, and performance of a very low-leakage-current thin film transistor (TFT). The TFT had a double-gate structure and used a 80–100 Å thick CdSe thin film as the semiconductor. The free charge carrier concentration in the semiconductor film was calculated to be 5×10¹⁴/cm³. These factors contributed to achieving a zero-gate-bias current less than 10^?10 A in the TFT. The ON/OFF current ratio of the TFT was measured to be greater than 10⁶. The TFT had acceptable stability in the ON condition and excellent stability in the OFF condition. A life test was performed on a TFT under a zero-gate-bias condition. After 1100 hr of testing, the zero-gate-bias current of the TFT increased from 5.8×10^?10 A to 9×10^?10 A. With extrapolation, the TFT had more than 10,000 hr lifetime.     

Performance and reliability of SLS ELA polysilicon TFTs fabricated with novel crystallization techniques

SLS ELA polysilicon TFTs fabricated in films crystallized with several novel techniques, yielding different film microstructure and texture, were investigated. The parameter statistics indicate that the TFT performance depends on film quality and asperities, in conjunction with the grain boundary trap density. The drain current transients, upon TFT switch from OFF to ON state, showed gate oxide polarization, related to film asperities and also confirmed the presence of extended defects in the TFTs of small mobilities. DC hot carrier stress was applied, indicating a reliability dependence on polysilicon structure and differences in degradation mechanisms for the various TFT technologies.     

Effect of Gate Leakage in the Subthreshold Characteristics of AlGaN/GaN HEMTs

This letter studies the effect of gate leakage on the subthreshold slope and ON/OFF current ratio of AlGaN/GaN high-electron mobility transistors (HEMTs). We found a strong correlation between the gate leakage current and the transistor subthreshold characteristics: the lower the gate leakage, the higher the ON/OFF ratio and the steeper the subthreshold slope. To improve the subthreshold characteristics in GaN HEMTs, the gate leakage current was reduced with an $hbox{O}_{2}$ plasma treatment prior to the gate metallization. The $hbox{O}_{2}$ plasma treatment effectively reduces the gate leakage current by more than four orders of magnitude, it increases the ON/OFF ratio to more than seven orders of magnitude and the improved AlGaN/GaN HEMT shows a nearly ideal subthreshold slope of 64 mV/dec.      

a—Si：H TFT自对准工艺的研究

实验研究了自对准结构的ａ－Ｓｉ：Ｈ ＴＦＴ的制备工艺，对其中关键的底部曝光和顶胶工艺进行了详细的研究和分析，对制备工艺和结构参数进行了合理的优化，成功地制备出自对准结构的ａ－Ｓｉ：Ｈ ＴＦＴ。对影响自对准结构ａ－Ｓｉ：Ｈ ＴＦＴ特性的主要因素进行了详细的分析，提出了一种新颖的双有源层结构的ａ－Ｓｉ：Ｈ ＴＦＴ，可以有效地改善ａ－Ｓｉ：Ｈ ＴＦＴ的开态特性，其通断电流比ＩＯＮ／ＩＯＦＦ〉１０＾５。     

Ovonic Memory Switching in Multimaterial Fibers

We demonstrate the first rewritable memory in thermally drawn fibers. A high tellurium‐content chalcogenide glass, contacted by metallic electrodes internal to the fiber structure, is drawn from a macroscopic preform. An externally applied voltage is utilized to switch between a high resistance (OFF) and a low resistance (ON) state; this in turn allows the fibers to function as a memory device reminiscent of the ovonic switch. The difference between the ON and OFF states is found to be four orders of magnitude. The glass–crystal phase transition is localized to micrometer‐wide filaments, whose position can be optically controlled along the fiber axis. An architecture that enabled the encoding of multiple bits per fiber is described.