ULSI多层互连中的化学机械抛光工艺

介绍了化学机械抛光(CMP)技术在大规模集成电路多层互连工艺[1]中的重要作用,对CMP过程和CMP的影响因素进行简单分析。总结出CMP技术在多层互联平坦化中的优势,介绍目前常用互连材料中SiO2介质及其金属材料钨和铜的化学机械抛光常用分析机理,并简单介绍了各种互联材料常用的抛光液及抛光液的组分,对抛光液作了简单的对比。针对传统CMP过程存在的问题,分析了皮带式和固定磨料的CMP技术。     

蓝宝石衬底nm级CMP技术研究

介绍了蓝宝石衬底的化学机械抛光工艺,讨论分析了影响蓝宝石衬底化学机械抛光的因素,定量确定了最佳CMP工艺。提出先以重抛过程提高蓝宝石抛光速率,然后以轻抛过程降低最终表面粗糙度的工艺路线。在配制抛光液时加入FA/OⅠ型活性剂保护SiO2胶粒的双电子层结构。在轻抛过程之前抛光垫用原液浸泡20～30min,抛光磨料直径为20～40nm。实验最佳工艺条件下的抛光速率达231.6nm/min,粗糙度降至0.34nm。     

CMP在集成电路非金属材料平坦化中的应用（Ⅰ）

化学机械抛光（CMP）工艺由IBM于1984年引入集成电路制造工业，并首先用在后道工艺的金属间绝缘介质（IMD）的平坦化，然后通过设备和工艺的改进用于钨（W）的平坦化，随后用于浅沟槽隔离（STI）和铜（Cu）的平坦化。化学机械抛光（CMP）为近年来IC制程中成长最快、最受重视的一项技术。其主要原因是由于超大规模集成电路随着线宽不断细小化而产生对平坦化的强烈需求。本文重点介绍CMP在集成电路中的非金属材料的平坦化应用。     

抛光液各组分在SiO_2介质CMP中的作用机理分析

介绍了超大规模集成电路中SiO2介质的化学机械抛光机理及抛光液在化学机械抛光中扮演的重要角色。通过单因素实验法,在低压力的实验环境下,着重分析了抛光液中表面活性剂、pH值调节剂、纳米磨料等成分在SiO2介质化学机械抛光中的具体作用及影响机理。最终得出,最优化的实验配比,即当表面活性剂的浓度为30mol/L,pH值为11.30,硅溶胶与去离子水的体积比为2:1时,在保证较低表面粗糙度的同时得到了较高的抛光速率476nm/min。     

CMP在集成电路非金属材料平坦化中的应用(Ⅰ)

化学机械抛光(CMP)工艺由IBM于1984年引入集成电路制造工业,并首先用在后道工艺的金属间绝缘介质(IMD)的平坦化,然后通过设备和工艺的改进用于钨(W)的     

300mm铜膜低压CMP速率及一致性

随着铜互连结构中低k介质的应用,要求CMP抛光过程中必须将压力减小到6.89 kPa以下,传统的化学机械抛光已不符合当前的工艺要求,如何兼顾超低压力下抛光速率和速率一致性成为关键问题.对300 mm Blanket铜膜进行了低压化学机械抛光实验,分析研究了碱性抛光液组分及抛光工艺参数对铜膜去除速率及其一致性的影响.通过...     

低压力Cu布线CMP速率的研究

采用低介电常数材料(低k介质)作为Cu布线中的介质层,已经成为集成电路技术发展的必然趋势.由于低k介质的低耐压性,加工的机械强度必须降低,这对传统化学机械抛光(CMP)工艺提出了挑战.通过对CMP过程的机理分析,提出了影响低机械强度下Cu布线CMP速率的主要因素,详细分析了CMP过程中磨料体积分数、氧化剂体积分数、FA/O螯合剂体积分数等参数对去除速率的影响.在4.33 kPa的低压下通过实验得出,在磨料体积分数为20%,氧化剂体积分数为3%,FA/O螯合剂体积分数为1.5%时可以获得最佳的去除速率及良好的速率一致性.     

ULSI铜互连线CMP抛光液的研制

介绍了一种碱性抛光液,选用有机碱做介质,SiO2水溶胶做磨料,依据强络合的反应机理,克服了SiO2水溶胶做磨料对铜去除速率低及在溶液中凝胶的难点.实验结果表明:该抛光液适用于Cu化学机械抛光过程第一阶段的抛光,并达到了高抛光速率及铜/钽/介质层间的高选择性的效果.     

ULSI铜互连线CMP抛光液的研制

介绍了一种碱性抛光液,选用有机碱做介质,SiO2水溶胶做磨料,依据强络合的反应机理,克服了SiO2水溶胶做磨料对铜去除速率低及在溶液中凝胶的难点.实验结果表明:该抛光液适用于Cu化学机械抛光过程第一阶段的抛光,并达到了高抛光速率及铜/钽/介质层间的高选择性的效果.     

以BCB为介质层的圆片级三维多芯片封装结构研究

研究了一种新型的圆片级三维多芯片封装结构,该结构以BCB为介质层,体硅工艺加工的硅片为基板,适合于毫米波射频元器件的封装与应用。结构中包含多层BCB介质层和金属布线,同时可以集成射频芯片,薄膜电阻,可变电容等有源和无源元件。封装过程中,射频芯片埋置在接地金属化的硅腔体中,利用热压焊凸点技术和化学机械抛光（CMP）实现多成金属布线间的层间互连。BCB介质层的涂覆、固化和抛磨对封装结构的性能影响较大,为了在进行CMP工艺和多层布线工艺之前得到高质量的BCB介质层,对BCB的固化曲线进行了优化,改进后的BCB介质层在经过CMP工艺后,能够得到光滑可靠的抛磨表面,不易产生质量缺陷,表粗糙度能够控制在10nm以内,利于BCB表面的金属布线工艺。同时,对加工完成的封装结构的力学、热学和射频传输性能进行了测试,结果显示：互连金凸点的剪切力达到70 N/mm2,优化后封装结构的热阻可以控制在2℃/W以内,在工作频段内,测试用低噪放大器的S参数变化很小,插入损耗的变化小于1db,回波损耗在10~15GHz的范围内,低于-8db,满足设计要求。     

GLSI多层布线钨插塞CMP表面质量的影响因素分析

随着超大规模集成电路向高集成、高可靠性及低成本的方向发展,对IC工艺中的全局平坦化提出了更高的要求。在特大规模集成电路(GLSI)多层布线化学机械抛光(CMP)过程中,抛光质量对器件的性能有明显影响。研究了多层互连钨插塞材料CMP过程中表面质量的影响因素及控制技术,分析了抛光过程中影响抛光质量的主要因素,确定了获得较高去除速率和较低表面粗糙度的抛光液配比及抛光工艺参数。     

低k介质与铜互连集成工艺

阐明了低k介质与铜互连集成工艺取代传统铝工艺在集成电路制造中所发挥的关键作用。依照工艺流程,介绍了如何具体实现IC制造多层互连工艺:嵌入式工艺、低k介质与平坦化、铜电镀工艺与平坦化;阐述了工艺应用现况与存在的难题,给出了国际上较先进的解决方法。     

Optimization of tribological properties of silicon dioxide during the chemical mechanical planarization process

Chemical mechanical planarization (CMP) has been proved to achieve excellent global and local planarity, and, as feature sizes shrink, the use of CMP will be critical for planarizing multilevel structures. Understanding the tribological properties of a dielectric layer in the CMP process is critical for successful evaluation and implementation of the materials. In this paper, we present the tribological properties of silicon dioxide during the CMP process. A CMP tester was used to study the fundamental aspects of the CMP process. the accessories of the CMP tester were first optimized for the reproducibility of the results. The coefficient of friction (COF) was measured during the process and was found to decrease with both down pressure and platen rotation. An acoustic sensor attached to this tester is used to detect endpoint, delamination, and uniformity. The effects of machine parameters on the polishing performance and the correlation of physical phenomena with the process have been discussed.     

超大规模集成电路制造中硅片化学机械抛光技术分析

目前半导体制造技术已经跨入0.13μm 和300mm时代,化学机械抛光(CMP)技术在ULSI制造中得到了快速发展,已经成为特征尺寸0.35μm以下IC制造不可缺少的技术。CMP是唯一能够实现硅片局部和全局平坦化的方法,但CMP的材料去除机理至今还没有完全理解、CMP系统过程变量和技术等方面的许多问题还没有完全弄清楚。本文着重介绍了化学机械抛光材料去除机理以及影响硅片表面材料去除率和抛光质量的因素。     

Embedded benzocyclobutene in silicon: An integrated fabrication process for electrical and thermal isolation in MEMS

This paper reports a novel fabrication process to develop planarized isolated islands of benzocyclobutene (BCB) polymer embedded in a silicon substrate. Embedded BCB in silicon (EBiS) can be used as an alternative to silicon dioxide in fabrication of electrostatic micromotors, microgenerators, and other microelectromechanical devices. EBiS takes advantage of the low dielectric constant and thermal conductivity of BCB polymers to develop electrical and thermal isolation integrated in silicon. The process involves conventional microfabrication techniques such as photolithography, deep reactive ion etching, and chemical mechanical planarization (CMP). We have characterized CMP of BCB polymers in detail since CMP is a key step in EBiS process. Atomic force microscopy (AFM) and elipsometry of blanket BCB films before and after CMP show that higher polishing down force pressure and speed lead to higher removal rate at the expense of higher surface roughness, non-uniformity, and scratch density. This is expected since BCB is a softer material compared to inorganic films such as silicon dioxide. We have observed that as the cure temperature of BCB increases beyond 200 °C, the CMP removal rate decreases drastically. The results from optical microscopy, scanning electron microscopy, and optical profilometry show excellent planarized surfaces on the EBiS islands. An average step height reduction of more than 95% was achieved after two BCB deposition and three CMP steps.     

化学机械抛光中的硅片夹持技术

目前半导体制造技术已经进入0.1 3μm时代,化学机械抛光(CMP)已经成为IC制造中不可缺少的技术.本文描述了下一代IC对大尺寸硅片(≥300mm)局部和全局平坦化精度的要求,介绍了目前工业发达国家在化学机械抛光加工中硅片夹持技术方面的研究现状,分析了当前硅片夹持技术中存在的问题,并指出了未来大尺寸硅片超精密平坦化加工中夹持与定位技术的发展趋势.     

Pad Deflection-Based Model of Chemical–Mechanical Polishing for Use in CAD IC Layout

The use of chemical–mechanical polishing (CMP) during the integrated circuit (IC) fabrication process has allowed for the aggressive interconnect patterning that is necessary for modern microprocessor technology. However, as IC technology has moved into the deep submicron realm, nonidealities during polishing have begun to play a significant role in device yield and circuit performance. In order to accurately predict circuit performance, designers must consider the effects of CMP prior to fabrication. A physics-based model to predict feature-scale wear of devices during polishing is presented and integrated into a CAD framework to test the model on various IC layouts. The model is benchmarked against experimental data and shown to be qualitatively accurate in predicting surface topography evolution.      

ULSI多层互连中W-CMP速率研究

随着IC制造技术进入到亚深微米时代,化学机械抛光(CMP)工艺成为ULSI多层布线的关键技术之一。分析了W-CMP的机理,抛光液对W材料表面具有化学腐蚀和机械研磨的双重作用,对抛光速率有着重要的影响。在分析了抛光液中各组分的作用基础上,重点研究了专用的氧化剂、磨料、pH值调节剂和抛光液流量对CMP速率的影响,优化配制了高速率、高平整的碱性W抛光液。实验证明,抛光液流量为150mL/min,V(硅溶胶):V(水)=1:1,有机碱为5mL/L,活性剂为5mL/L,H2O2质量浓度为20mL/L时,能够获得较高的抛光速率,并实现了全局平坦化。最后对W-CMP中存在的问题和发展趋势进行了分析和展望。     

Chemical mechanical polishing of polymer films

Strategies to reduce capacitance effects associated with shrinking integrated circuit (IC) design rules include incorporating low resistivity metals and insulators with low dielectric values, or “low-κ” materials. Using such materials in current IC fabrication schemes necessitates the development of reliable chemical mechanical polishing (CMP) processes and process consumables tailored for them. Here we present results of CMP experiments performed on FLARE™ 2.0 using a specialized zirconium oxide (ZrO₂) polishing slurry. FLARE™ 2.0 is a poly(arylene) ether from AlliedSignal, Inc. with a nominal dielectric constant of 2.8. In addition, we provide insight into possible removal mechanisms during the CMP of organic polymers by examining the performance of numerous abrasive slurries. Although specific to a limited number of polymers, the authors suggest that the information presented in this paper is relevant to the CMP performance of many polymer dielectric materials.