基于门控时钟技术的低功耗三值D型触发器设计

本文在三值D型触发器的基础上提出了一种低功耗三值门控时钟D型触发器的设计.该设计通过抑制触发器的冗余触发来降低功耗,PSPICE模拟验证了该触发器具有正确的逻辑功能.与三值D触发器相比,该触发器在输入信号开关活动性较低的情况下具有更低的功耗.同时该电路结构可以推广到基值更高的低功耗多值触发器的设计中.     

A flip-flop sensor array with on-spot A/D conversion

A two-dimensional optical flip-flop sensor array, consisting of an 8×8 matrix of flip-flop sensors integrated in one chip together with sense amplifiers and access selection circuitry, is discussed. A flip-flop sensor contains two phototransistors, one of which is covered over the aluminum while the other is exposed to light. Each flip-flop senses the light intensity and converts it to a series of ones and zeros. It is operated by turning the supply current on and off with a high frequency. During the absence of light the flip-flop is totally symmetrical and the number of ones and zeros is equal. Light causes an asymmetry in the flip-flop that changes the ratio of ones and zeros. A fully digital output is obtained by counting the number of ones. A triangle-wave voltage is applied to the flip-flop to vary its threshold. The device showed that a large array of sensors with on-spot A/D (analog-to-digital) conversion can be realized using the flip-flop sensor technique     

三值低功耗多米诺JKL触发器设计及应用

通过对三值触发器和绝热多米诺电路的研究,提出一种新颖低功耗多米诺JKL触发器开关级设计方案。该方案首先利用开关—信号理论,根据三值JKL触发器真值表,推导出三值绝热多米诺JKL触发器开关级结构式;然后利用三值JKL触发器实现三值正循环门电路和三值反循环门电路的设计;最后,经Spice软件模拟证明所设计的三值绝热多米诺JKL触发器逻辑功能正确,与常规三值多米诺JKL触发器相比,能耗节省约69%。     

Optical Flip-Flop Using Bistable Vertical-Cavity Semiconductor Optical Amplifiers With Anti-Resonant Reflecting Optical Waveguide

Flip-flop operations of anti-resonant reflecting-optical-waveguide (ARROW) vertical-cavity semiconductor optical amplifiers (VCSOAs) under the influence of undesired high-order injection modes are investigated theoretically. Three types of flip-flop operations, namely: (1) flip-flop triggered by optical injection, (2) inverse flip-flop triggered by optical injection, and (3) flip-flop triggered by injection current, are to be considered in the studies. It is found that with the presence of ARROW, all three types of optical flip-flop are insensitive to high-order injection modes, and stable single-mode flip-flop can be maintained in the operation.     

GHz programmable counter with low power consumption

A high-speed programmable counter with a new reloadable D flip-flop which integrates the programmable function to a true-single-phase-clock (TSPC) D flip-flop is presented. The proposed reloadable D flip-flop is able to operate at higher frequencies with lower power consumption compared to the performance of the existing bitcell. The programmable divide-by-N counter implemented with this reloadable D flip-flop using the Chartered 0.18 /spl mu/m CMOS process is capable of operating up to 2 GHz for a 1.8 V supply voltage with 4.7 mW power consumption.     

同步JK触发器门级建模仿真讨论

同步JK触发器是“数字电路与逻辑设计”课程中重要的一种触发器单元。但目前教材给出的同步JK触发器的翻转状态是值得商榷的。关于同步JK触发器的仿真方面,网上的一些资料较为混乱,很多资料上对于JK触发器直接采用教科书上的结论进行行为级建模,虽然避免了初始状态的影响,但并不能真正反应JK触发器的真正功能。也有人采用与非门例化的方法对其进行门级建模,但仿真输出一直为一个不确定的状态。本文通过加入复位信号,使得触发器的当前状态为一个确定状态,从而能正确仿真。仿真和分析表明,翻转状态是值得商榷的,教科书也应据此进行更改。     

基于MOBILE的JK触发器设计

介绍了一种新型量子逻辑单元电路——单稳双稳转换逻辑单元及其工作原理,在此基础上探讨并设计了以MOBILE为基本单元电路的具有同步置位复位功能的边沿型JK触发器电路,从而丰富了量子电路中触发器的类型     

A reduced clock-swing flip-flop (RCSFF) for 63% power reduction

A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop which embodies the leakage current cutoff mechanism. The RCSFF can reduce the clock system power of a VLSI down to one-third compared to the conventional flip-flop. This power improvement is achieved through the reduced clock swing down to 1 V. The area and the delay of the RCSFF can also be reduced by a factor of about 20% compared to the conventional flip-flop. The RCSFF can also reduce the RC delay of a long RC interconnect to one-half     

基于半导体光放大器的光单稳态触发器

为实现全光缓存中的光读写控制和光逻辑判断,提出并实验验证了一种基于半导体光放大器(SOA)双环结构的全光单稳态触发器。此触发器的稳态与非稳态激射不同的光波长,状态间静态消光比超过40 dB,切换时间仅仅为1-2个环腔周期,控制信号光波长范围大。通过减小环腔长度可进一步减小两状态之间切换时间,并可作为光缓存的控制单元。     

基于CPLD/FPGA的多触发器逻辑功能模拟研究

利用FPGA／CPLD芯片高集成度、多I／O口特点，提供两种方法，通过设计输入、编译、仿真与硬件下载验证等过程，实现将基本RS、同步RS、D、JK触发器同时集成在一块FPGA／CPLD芯片中并模拟其逻辑功能。     

Flip-flop device with state actuation

The operation of a two-stage JK flip-flop with the alternate use of two main flip-flops by the master-master scheme is considered. This flip-flop features improved operation speed and reliability due to an insignificant hardware redundancy. Operation of this flip-flop at the functional level is considered, modeling results are presented, and time parameters are estimated.     

SEU/SET加固D触发器的设计与分析

针对D触发器的抗单粒子辐射效应加固,提出了一种新型的保护门触发器(GGFF)设计,使用两个保护门锁存器串接成主从触发器.通过Spice仿真验证了GGFF抗SEU/SET的能力,通过比较和分析,证明GGFF对于具有同样抗SEU/SET能力的时间采样触发器(TSFF),在电路面积和速度上占据明显优势.     

Reduced setup time static D flip-flop

The design of a reduced setup time static D type flip-flop is described. The setup time of the proposed static D flip-flop is equivalent to that of dynamic D flip-flops     

Fast all-optical flip-flop memory exploiting the electric field nonlinearity of coherent laser amplifiers

The coherent nonlinear feedback in an integrated optical flip-flop is studied in order to demonstrate device applications of laser amplifiers operated above the laser threshold. The nonlinear feedback is provided by the stabilizing fields of the laser amplifiers, interfering with coherent optical reference fields. In both stable states of the flip-flop, the nonlinear feedback allows the laser amplifiers to maintain an ever present photon population in the laser modes and to have an approximately constant carrier population. This enables faster response (switching times below 25 ps are reached in this work)than in conventional active optical flip-flop structures. The operation of the flip-flop is studied using a rate equation model accounting for the carrier densities and the complex electric fields in the different cavity modes of the laser amplifiers.     

Loosely coupled multi-bit flip-flop allocation for power reduction

Merging 1-bit flip-flops into multi-bit flip-flops in the post-placement stage is one of the most effective techniques for minimizing clock power. In this work, we introduce a new style of multi-bit flip-flop, called loosely coupled multi-bit flip-flop (LC-MBFF). The merit of LC-MBFF is that the logically constituent 1-bit flip-flops in LC-MBFF can be physically apart (i.e., no relocation), providing no need to set aside white space. Utilizing LC-MBFFs, we propose a multi-bit flip-flop allocation algorithm which fully explores the diverse allocation of LC-MBFF structures to maximally reduce clock power consumption. Experimental results with ISCAS89 and IWLS2005 benchmark circuits show that our proposed allocation algorithm using the newly designed multi-bit flip-flops is able to reduce on average the clock power by 8.51% while the best known multi-bit flip-flop allocation algorithm [7] reduces by 5.37%. Additionally, we extend our algorithm to support the multi-bit flip-flop allocation for circuits with clock polarity assignment.     

Multisim在触发器工作波形分析中的应用

介绍用Multisim仿真软件进行触发器工作波形仿真分析的方法,目的是探索触发器工作波形的仿真实验技术,即用Multisim仿真软件中的字组产生器产生触发器的时钟脉冲、数据输入、异步控制等多路信号,用Multisim中逻辑分析仪多踪同步显示触发器的各种输入及状态输出波形。并介绍了几种典型触发方式,不同逻辑功能触发器工作波形仿真分析时Multisim中字组产生器的设置方法。该软件可直观形象地描述触发器的逻辑功能和状态变化特点。所述方法的创新点是解决了触发器工作波形无法用电子实验仪器进行分析验证的问题。     

All-optical flip-flop based on coupled laser diodes

An all-optical set-reset flip-flop is presented that is based on two coupled lasers with separate cavities and lasing at different wavelengths. The lasers are coupled so that lasing in one of the lasers quenches lasing in the other laser. The flip-flop state is determined by the laser that is currently lasing. A rate-equation based model for the flip-flop is developed and used to obtain steady-state characteristics. Important properties of the system, such as the minimum coupling between lasers and the optical power required for switching, are derived from the model. These properties are primarily dependent on the laser mirror reflectivity, the inter-laser coupling, and the power emitted from one of the component lasers, affording the designer great control over the flip-flop properties. The flip-flop is experimentally demonstrated with two lasers constructed from identical semiconductor optical amplifiers (SOAs) and fiber Bragg gratings of different wavelengths. Good agreement between the theory and experiment is obtained. Furthermore, switching over a wide range of input wavelengths is shown; however, increased switching power is required for wavelengths far from the SOA gain peak     

基于QCA的双边沿JK触发器的实现

量子元胞自动机(Quantum-dot Cellular Automata,QCA)是一种有望替代传统半导体晶体管的新型纳米器件.本文提出了一种改进的双边沿触发结构及其相应的JK触发器电路,用概率转移矩阵(Probabilistic Transfer Matrix,PTM)分析该触发结构,结果表明该结构较以往的可靠性更高.同时利用模块垂直堆叠方法来优化了JK触发器电路,新结构电路较之前的电路元胞数和整体面积均有所减少.     

全光触发器的研究进展

全光触发器是数字光信号处理的基础技术,也是全光分组交换网的关键技术之一.文章就光触发器的功能模型与性能指标提出了自己的见解,概括总结了各种光触发器的原理与性能,并进行了比较.     

基本RS触发器工作状态的Multisim仿真

给出了具有置0、置1功能及不确定输出状态的基本RS触发器的Multisim仿真方法,即用字组产生器产生所需的各类输入信号,用四踪示波器同步显示输入信号及状态输出信号的波形,可直观描述触发器的置O、置1过程及不确定状态的产生过程。分析了基本RS触发器不确定状态的输出逻辑表达式及Muhisim仿真方案。所述方法的创新点是解...