L波段高效率射频功率放大器的设计与仿真

射频功率放大器是无线通信系统中的重要组成部分,其工作效率直接影响着整个系统的耗能、稳定度和对电源散热装置的要求,提高射频功率放大器的效率,能够节约能源,降低功耗,因此实现射频功率放大器的高效率工作是目前射频功率放大器领域的热点问题之一。本文选用Freescale晶体管MW6S004N,借助ADS2013软件,采用负载牵引技术和源牵引技术得到最佳负载阻抗和最佳源阻抗,并用Smith圆图进行电路的匹配设计,对射频功率放大器进行了仿真和优化。仿真结果表明,在频率为1960MHz的L波段,输入功率为21d Bm时,射频功率放大器的输出功率大于36d Bm,功率附加效率大于50%。这种高效率射频功率放大器适用于WCDMA基站,对基站中高效率功率放大器的设计有着重要的参考价值。     

A MEMS reconfigurable matching network for a class AB amplifier

This letter presents the design of a reconfigurable amplifier with an adaptive matching network implemented by shunt MEMS switches. In particular, the MEMS switches are used as capacitive stubs in double-stub matching circuit designs. The effective capacitance of the switches can be varied by switch activation which results in a change of the matching configuration. The RF response of the adaptive matching network is studied and the power performance of the amplifier is presented.     

Attenuation compensation in distributed amplifier design

A high-gain common-gate FET that presents at its drain a broadband impedance characterized by a (frequency-dependent) negative resistance and a capacitance is examined theoretically and experimentally. Loading the input and/or the output lines of a distributed amplifier with this circuit reduces the signal losses, leading to an increase in the allowed number of active devices with a consequent increase in the gain-bandwidth and gain-maximum-frequency products. The cascode circuit, a related loss reduction network, is also evaluated because of its use in distributed amplifiers. Several designs employing the common-gate FET loss-compensating circuit and/or the cascode amplifying circuit are compared to a conventional distributed amplifier optimized for gain-bandwidth product. Simulated gain-maximum-operating frequency product increases of 27% to 245% over that of the optimized conventional distributed amplifier are shown. The increase in single-stage amplifier gain provided by this technique often results in (proportionally) higher maximum output power     

Nonlinear design procedures for single-frequency and broad-bandGaAs MESFET power amplifiers

The design and optimization of MESFET power amplifiers are investigated using an intermediate-level (functional) device modeling approach. The approximations involved are discussed, together with considerations of required circuit terminations at harmonic frequencies. Three variations of the approach, based on large-signal admittance, scattering, and hybrid parameters, are compared in the design of a single-frequency amplifier, and the method is extended to broadband power amplifier design. In all cases, results are validated by comparison with a full time-domain large-signal amplifier analysis, involving realistic, distributed external circuits     

基于ADS的功率放大器设计与仿真

为了使射频功率放大器输出一定的功率给负载,采用一种负载牵引和源牵引相结合的方法进行功率放大器的设计。通过ADS软件对其稳定性、输入/输出匹配、输出功率进行仿真,并给出清晰的设计步骤。最后结合设计方法给出一个中心频率为2.6GHz、输出功率为6.5W的功率放大器的设计及优化实例和仿真结果。仿真结果表明,这种方法是可行的,满足设计的要求,并且对功放的设计有着重要的参考价值。     

基于列车监测网络设备的射频功放模块设计

列车关键设备及行车状态的无线实时监测是列车安全运行的有效技术保障,而如何延长无线监测节点通信距离、增强通信可靠性成为研究重点。本文提出适用于列车监测特殊环境的射频功放模块设计方法,采用集成化芯片RF5110G避免内部干扰,通过滤波电路和阻抗匹配优化电路板设计,所设计的功放模块很好地解决了列车特殊环境导致的信号衰减问题,增强了监测网络节点数据传输可靠性,为列车监测、维护提供了可行的方法。     

On the performance analysis and design of an integrated front-end PIN/HBT photoreceiver

A detailed study on the performance analysis and optimum design of an integrated front-end PIN/HBT photoreceiver for fiber-optic communication is presented. Receiver circuits with two different transimpedance amplifiers-a single-stage common emitter (CE) amplifier and a three-stage amplifier comprising a CE amplifier and two emitter followers (EFs), are analyzed assuming a standard load of 50 /spl Omega/. A technique to include the transit-time effect of a PIN photodetector on the overall receiver circuit analysis is introduced and discussed. Gain-bandwidth product (GB) and gain-bandwidth-sensitivity measure product (GBS) are obtained as functions of feedback resistance (R/sub F/) and various device parameters. Hence, some optimum designs are suggested using a photodetector of area 100 /spl mu/m/sup 2/ and with a feedback resistance of 500 /spl Omega/. The bandwidth plays a major role in determining the optimum designs for maximum GB and maximum GBS. A bandwidth >8 GHz has been obtained for the photoreceiver even with a single-stage CE amplifier. The optimum design for a receiver with a three-stage amplifier shows a bandwidth of 35 GHz which is suitable for receivers operating well beyond 40 Gb/s; however, in this case, the gain is reduced. The performance of different fixed square-emitter structures are investigated to choose the optimum designs corresponding to different gains. Very low power dissipation has been estimated for the optimized devices. The noise performance of the devices with optimum designs was calculated in terms of the minimum detectable optical power for a fixed bit-error rate of 10/sup -9/. The present design indicates that GB and noise performance can be improved by using an optimum device design.     

Parasitic-aware design and optimization of a CMOS RF power amplifier

Implementation of fully integrated CMOS RF power amplifiers is a challenge owing to the low breakdown voltage of aggressively scaled CMOS transistors and parasitic effects associated with on-chip passive components. To address this problem, a parasitic-aware design and optimization paradigm and novel power amplifier circuit design techniques are proposed. The parasitic-aware synthesis described herein employs a simulated annealing algorithm that includes an adaptive tunneling mechanism and post-optimization sensitivity analysis (i.e., design centering) with respect to process, voltage, and temperature variations. Several design techniques are introduced including a self-biased power-amplifier configuration and a digitally controlled conduction angle topology. The techniques are validated via the design of a fully differential nonlinear three-stage 900-MHz GSM power amplifier integrated in 2 mm/sup 2/ in 250-nm CMOS that outputs 2 W (1.5 W) with 30% (43%) drain efficiency from a single 3.0-V (2.5-V) power supply.     

无线传输系统中低噪声放大电路的设计

介绍射频功率放大器的基础理论和技术参数,并根据设计要求选取合适的低噪声放大器。给出了射频功率放大电路的设计方案,并根据系统接收端无线信号特点,设计低噪声功率放大电路,从而提高无线传输系统的接收灵敏度,并满足冲击渡测试对无线传输距离的要求。     

新型缺陷地结构改善射频功率放大器的性能

提出了一种新型的缺陷地结构,并将这种新型的缺陷地结构应用于实际所设计的射频功率放大器中.这种新型的缺陷地结构,蚀刻在射频功率放大器的偏置线下面的地平面和输出匹配电路后方的地平面,经过最后和不加这种结构的射频功率放大器进行比较和测试验证,证明成功的抑制了射频功率放大器的二次、三次谐波.     

Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology

Highly integrated transmitter and receiver MMICs have been designed in a commercial 0.15 /spl mu/m, 88 GHz f/sub T//183 GHz f/sub MAX/ GaAs pHEMT MMIC process and characterized on both chip and system level. These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.5 GHz. Although the chips are inherently multipurpose designs, they are especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics. The single-chip transmitter MMIC consists of a balanced resistive mixer with an integrated ultra-wideband IF balun, a three-stage power amplifier, and the X8 LO chain. The X8 is a multifunction design by itself consisting of a quadrupler, a feedback amplifier, a doubler, and a buffer amplifier. The transmitter chip delivers 3.7/spl plusmn/1.5 dBm over the RF frequency range of 54-61 GHz with a peak output power of 5.2 dBm at 57 GHz. The single-chip receiver MMIC contains a three-stage low-noise amplifier, an image reject mixer with an integrated ultra-wideband IF hybrid and the same X8 as used in the transmitter chip. The receiver chip has 7.1/spl plusmn/1.5 dB gain between 55 and 63 GHz, more than 20 dB of image rejection ratio between 59.5 and 64.5 GHz, 10.5 dB of noise figure, and -11 dBm of input-referred third-order intercept point (IIP3).     

Integrated Multilayered On-Chip Inductors for Compact CMOS RFICs and Their Use in a Miniature Distributed Low-Noise-Amplifier Design for Ultra-Wideband Applications

A novel multilayered vertically integrated inductor structure is developed for miniature CMOS RF integrated circuits, and its properties are investigated. The effect of mutual inductance both within and between adjacent multilayer inductors is also studied. A distributed low noise amplifier is designed by incorporating this novel inductor structure in a standard JAZZ 0.18-$mu$m RF/mixed signal CMOS process, demonstrating the significance of the proposed multilayered inductors in CMOS circuit miniaturization. The three-stage distributed amplifier occupies just 288$,times,$291 $mu$m or 0.08 mm $^{2}$ of die area, making it the smallest distributed amplifier reported to date. The circuit exhibits a relatively flat gain of 6 dB from 3.1 to 10.6 GHz with less than 0.5-dB ripple, with excellent input and output match of less than ${-}$ 12 and ${-}$25 dB, respectively. The noise figure is less than 5 dB to 14 GHz with only 2.7 dB across 8–10 GHz, while the power consumption is approximately 22 mW.      

可重构多波段射频功率放大器设计

在未来通信系统发展中,多波段多模式的射频功率放大器具有很大的应用前景。在众多解决方案中,利用可重构器件实现的可重构多波段射频功率放大器最具优势。利用PIN二极管的单向导电性,提出了基于PIN二极管开关的可重构多波段功放的设计思路。介绍了可重构器件的仿真设计,并进行了实际测试。在1 750 MHz、2 100 MHz和2 600 MHz频点设计了可重构多波段功放电路,并做了仿真测试。为验证仿真设计的准确性,完成了实际电路板制作和功放的调试工作。实验测试结果表明,提出的设计方法可行并达到了设计指标,对今后的研究工作具有重要的指导意义。     

Modeling and characterization of an 80 V silicon LDMOSFET foremerging RFIC applications

This paper describes the design and optimization of an 80 V silicon RF LDMOSFET used in a power amplifier for base station applications. The transistor was prototyped using the doping profiles extracted from an experimental device and extensive two-dimensional (2-D) simulations were performed to characterize the DC and RF performance of the device. A good match between the measured and simulated data is reported. A simple circuit model was developed which accurately predicts the DC and RF characteristics in circuit simulators. It is shown through 2-D simulations that the LDD region in the LDMOSFET can be modeled as a JFET. A methodology for the accurate extraction of model parameters for the circuit model is discussed. It is shown that the DC and RF performances of the circuit model closely match the measured data. Advanced mixed device and circuit simulations were used to obtain S-parameters of the device which provide new insights into device physics and also the basis for statistical process control studies     

The class BD high-efficiency RF power amplifier

Class B and class D operation of the same RF power amplifier circuit is not normally possible because of constraints imposed by the tuned output circuit and DC power input circuit. The use of square-wave drive in a current switching class D RF amplifier circuit allows the amplifier to move gradually from current source to current switch operation. This amplifier, called class BD, has a linear transfer characteristic (drive envelope to output envelope) and an efficiency 1.23 times that of a class B RF amplifier with the same peak output. The addition of a resistive AC current path to ground in the DC power input circuit of the class BD RF amplifier allows operation with sinewave driving waveforms. While this lowers the efficiency at the peak output, it can raise it at lower outputs, making possible a factor of 1.57 improvement in efficiency in the amplification of signals with large peak-to-average ratios. The class BD RF amplifier may therefore be used as a broad-band replacement for a Doherty-type amplifier.     

Bufferless broadcasting: a low power distributed circuit techniquefor broadcasting 10-Gb/s chip input signals

Bufferless distributed circuit (BDC) broadcasting is proposed as a technique for broadcasting high-speed chip input signals to a series of on-chip destination cells as needed in crosspoint switch, parallel multiplier, distributed amplifier, etc., chip designs. In contrast with conventional techniques that use an on-chip buffer to assist broadcasting, BDC broadcasting offers the advantage of lower signal delay and power dissipation. In an experimental GaAs heterojunction bipolar transistor (HBT) 8×4 crosspoint switch assembly, BDC broadcasting was found to achieve a 40% power savings with little or no penalty in jitter or bit error rate performance at a 10-Gb/s data rate     

一种基于ADS仿真的射频放大器设计方法

针对当前无线通信系统研发周期缩短、研发费用节省的需要,EDA设计工具越来越被电子技术研究的各领域所采用。以EDA中的ADS软件为设计工具,通过具体设计步骤的展示,描述了一种基于ADS仿真的射频放大器设计方法,具有积极的指导意义。在设计过程中,着重注意增益、三阶交调、稳定性等参数。最后列举了实例,说明了该设计方法的可行性。     

低噪声放大器的两种设计方法

低噪声放大器是射频收发机的一个重要组成部分,也是射频电路设计中的难点。在此先对晶体管ATF-54143做了定性分析,根据定性分析以及实际需求,阐述了射频低噪声放大器设计与仿真的两种方法。一种是以最佳噪声系数为目标的设计方法;另一种是以噪声系数为主兼顾增益目标的设计方法。该方法详尽且数据准确真实,其仿真结果均符合预定的设计要求。     

一种优异温度稳定性Ka波段上变频放大模块

研究了Ka波段变频放大电路的设计及其温度补偿技术,分析了上变频放大模块的基本原理,分别对射频增益及检波电压进行了温度补偿,提出了一种优异温度稳定性、高线性度、高增益稳定性的总体设计方案。该变频放大模块由放大电路、温补电路、混频电路、滤波电路及功率放大器等单元电路组成。运用Agilent ADS软件完成了模块的整体电路设计。同时,介绍了一种基于场仿真软件和实测相结合的方法,建立毫米波多芯片组件中互连的键合线模型,将键合线的寄生电感融入了上变频放大模块电路设计中,显著提高键合线互连电路的频率响应。采用多芯片组装工艺制作了高性能的变频放大模块,实现了在Ka波段输出功率＞于30.6 dBm,全温范围功率波动＜0.8 dB,全温检波电压指示波动＜0.2 V,测试结果与仿真结果一致。     

Design of Ultra-Low-Voltage RF Frontends With Complementary Current-Reused Architectures

In this paper, ultra-low-voltage circuit techniques are presented for CMOS RF frontends. By employing a complementary current-reused architecture, the RF building blocks including a low-noise amplifier (LNA) and a single-balanced down-conversion mixer can operate at a reduced supply voltage with microwatt power consumption while maintaining reasonable circuit performance at multigigahertz frequencies. Based on the MOSFET model in moderate and weak inversion, theoretical analysis and design considerations of the proposed circuit techniques are described in detail. Using a standard 0.18-mum CMOS process, prototype frontend circuits are implemented at the 5-GHz frequency band for demonstration. From the measurement results, the fully integrated LNA exhibits a gain of 9.2 dB and a noise figure of 4.5 dB at 5 GHz, while the mixer has a conversion gain of 3.2 dB and an IIP₃ of -8 dBm. Operated at a supply voltage of 0.6 V, the power consumptions of the LNA and the mixer are 900 and 792 muW, respectively.