A CMOS switched transconductor mixer

A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled outputs, which are alternatingly activated by the switches. For ideal switching, the operation is equivalent to a conventional active mixer. This paper analyzes the performance of the switched transconductor mixer, in comparison with the conventional mixer, demonstrating competitive performance at a lower supply voltage. Moreover, the new mixer has a fundamental noise benefit, as noise produced by the switch-transistors and LO-port is common mode noise, which is rejected at the differential output. An experimental prototype with 12-dB conversion gain was designed and realized in standard 0.18-/spl mu/m CMOS to operate at only a 1-V supply. Experimental results show satisfactory mixer performance up to 4 GHz and confirm the fundamental noise benefit.     

Doubly balanced dual-gate CMOS mixer

The operation, biasing, and measured results of a CMOS doubly balanced dual-gate downconversion mixer are presented. Measurements show, with a radio-frequency input of 1.9 GHz and an intermediate-frequency output of 250 MHz, that the mixer has a conversion gain of 0 dB, an input-referred third-order intercept point of +2 dBm, and a single-sideband noise figure of 13.6 dB while requiring +5 dBm of local-oscillator power and consuming 10.2 mA from a 3 V power supply     

High-performance current bleeding CMOS mixer

A high-performance mixer, known as the amplifier-driven double-balanced Gilbert-cell mixer, is proposed and implemented in 0.18 mum RFCMOS technology. A class-A amplifier-based current bleeding source is used to amplify the local oscillator signal and improve transconductance of the transconductor stage. The conversion gain is measured to be 17.5 dB when the LO power is 14 dBm only. The measured noise figure is better than 12.5 dB. The chip area is 1.2 1.3 mm and the power consumption is 12 mA at 1.5 V supply voltage.     

A low-power 65-nm CMOS mixer linearized with IM2 injection for V2X applications

Analog Integrated Circuits and Signal Processing - In this paper, high linearity, low power down-conversion mixer is presented with a 65-nm CMOS process for vehicle-to-everything (V2X)...     

65 nm CMOS SSB mixer for UWB synthesiser

The present work addresses the design of a 65 nm CMOS wide-band single-sideband mixer for UWB synthesiser. The circuit has been designed inductorless and with few capacitors, in order to save silicon area and, at the same time, to get a mixer independent of the adopted frequency plan and synthesiser architecture. Particular attention has been paid to reducing the spurs as much as possible. In order to address a realistic investigation, the design has accounted also for the corner cases and the possible impairments in the input signals. A comparison with the state-of-the-art of the SSB mixers shows the low power consumption of the present work.     

A 1-GHz CMOS up-conversion mixer

A high-frequency linear MOS mixer topology is presented for the implementation of a 1-GHz up-conversion mixer in a standard 0.7-μm CMOS technology. The high output bandwidth has been achieved by the development of an nMOS-only current amplifier that converts the modulated current of the nMOS mixing transistor biased in the linear region to the RF output voltage     

26-34 GHz CMOS mixer

A 26-34 GHz fully integrated CMOS down mixer is presented. At 30 GHz RF frequency and 2.5 GHz IF frequency, 50 /spl Omega/ terminations, 5 dBm LO and 1.2 V/spl times/17 mA supply power, the circuit yields a conversion loss of 2.6 dB, an SSB NF of 13.5 dB and an IIP3 of 0.5 dBm.     

An ultra-low-voltage ultra-low-power CMOS active mixer

The scaling of CMOS technology has greatly influenced the design of analog and radio-frequency circuits. In particular, as technology advances, due to the use of lower supply voltage the available voltage headroom is decreased. In this paper, after a brief overview of conventional low-power CMOS active mixer structures, we introduce an active mixer structure with sub-mW-level power consumption that is capable of operating from a supply voltage comparable or lower than the threshold voltage of the transistor. In addition, the proposed architecture provides a performance and conversion gain (CG) that compares favorably or exceeds those of the state-of-the-art designs. As a proof-of-concept, a wide-band DC to 8.5 GHz down-conversion mixer is designed and fabricated in a 90-nm CMOS process. Measurement results show that the mixer achieves a CG as high as 18 dB while consuming 98 μW from a 0.3-V supply.     

A broadband folded Gilbert cell CMOS mixer

A folded Gilbert cell mixer was implemented in 0.13 μm complementary metal oxide semiconductor (CMOS) technology. The downconversion mixer is designed for 5–6 GHz radio frequency (RF) band and an intermediate frequency (IF) of 500 MHz. A voltage conversion gain (CG) of 9 dB, a noise figure (NF) of 11 dB and an IIP3 of 2 dBm were demonstrated experimentally under very low power consumption conditions, only 4.2 mW for the mixer core. Considering the overall performance of the circuit, this paper shows that the folded mixer architecture is one of the most interesting frequency converter solutions for low-power mobile applications.     

A merged CMOS LNA and mixer for a WCDMA receiver

A low-noise amplifier (LNA) and mixer circuit in 0.35-/spl mu/m CMOS operates at 2.1 GHz. Merging the LNA and mixer lowers the number of transistors in the signal path and thereby also the nonlinearity and power consumption. The circuit meets the specifications for a direct conversion wide-band code-division multiple access (WCDMA) receiver. Its noise figure is 3.4 dB (5kHz to 5MHz), the total conversion gain is 23 dB, the third-order input-referred intercept point is -1.5 dBm, and the local oscillator leakage to the antenna is less than -71 dBm. The fully differential circuit takes 8 mA from a 2.7-V supply.     

W-Band CMOS down-conversion mixer using micromixer-based gain-enhanced technique

We demonstrate a W-band down-conversion micromixer for imaging and gesture recognition transceiver. Micromixer-based gain-boosted technique, i.e. inductive-peaking gain-boosted single-to- differential transconductance (g_m) stage, is adopted to increase the output impedance and restrain the feedback capacitance C_gd of the g_m stage. This leads to the conversion gain (CG), noise figure (NF) and LO-to-RF leakage of the micromixer being significantly improved. The micromixer dissipates 7.2 mW and attains marvellous RF-port return loss of ?12.7~ ?14.7 dB for 85 ~ 110 GHz. That is, the ?10 dB matching bandwidth is wider than 25 GHz. Moreover, for 90 ~ 96 GHz, the micromixer attains CG of 10.5 ~ 12 dB and LO-to-RF isolation of 40.2 ~ 46.2 dB, one of the highest values ever demonstrated for a W-band mixer/micromixer. The 3 dB CG bandwidth is 22 GHz (83 ~ 105 GHz), and the input third-order intercept point (IIP3) is 1 dBm. These results indicate the micromixer is appropriate for W-band imaging and gesture recognition transceivers.     

一种用于数字电视接收机的58dB IRR CMOS镜像抑制混频器

The design,implementation,and characterization of an image-rejection double quadrature conversion mixer based on RC asymmetric polyphase filters（PPF） are presented.The mixer consists of three sets of PPFs and a mixer core for quadrature down conversion.Two sets of PPFs are used for the quadrature generation and the other one is used for the IF signal selection to reject the unwanted image band.Realized in 0.18-μm CMOS technology as a part of the DVB-T receiver chip,the mixer exhibits a high image rejection ratio（IRR） of 58 dB,a power consumption of 11 mW,and a 1-dB gain compression point of-15 dBm.     

A CMOS image-rejection mixer with 58-dB IRR for DTV receivers

The design, implementation, and characterization of an image-rejection double quadrature conversion mixer based on RC asymmetric polyphase filters (PPF) are presented. The mixer consists of three sets of PPFs and a mixer core for quadrature down conversion. Two sets of PPFs are used for the quadrature generation and the other one is used for the IF signal selection to reject the unwanted image band. Realized in 0.18-μm CMOS technology as a part of the DVB-T receiver chip, the mixer exhibits a high image rejection ratio (IRR) of 58 dB, a power consumption of 11 mW, and a 1-dB gain compression point of -15 dBm.     

A new approach to amplifier linearization by the generalized baseband signal injection method

The authors present a new technique for the reduction of third-order intermodulation distortion (IMD) in microwave amplifiers. A baseband predistortion signal is injected into a diode circuitry and the main amplifier to mix with the fundamental to generate a canceling signal for the suppression of the inherent IMD component. The proposed method can achieve higher linearity performance, in comparison to the conventional difference-frequency approach, and unlike many other techniques, no RF circuitry, such as variable gain amplifiers and phase-shifters, is needed other than baseband amplifiers. Both two-tone and vector signal measurement results are included.     

一种高线性低噪声CMOS混频器设计

混频器应用在多标准领域中,对混频器的线性度和噪声性能提出了严格的要求。文中提出了一种新型的高线性、低噪声CMOS混频器。该混频器同时采用了三阶失真抵消技术和噪声抵消技术。采用TSMC 0.13μm CMOS工艺进行设计并流片实现,测试结果表明,较之传统的吉尔伯特混频器而言,文中混频器的输入三阶交调点IIP3增加了6.18d Bm,噪声系数下降了3.5d B,而用于三阶失真抵消技术和噪声抵消技术的电路部分仅使混频器多消耗了0.85m A的电流。     

Linearity enhancement technology for mixer in monolithic CMOS UHF RFID interrogator

Linearity requirements characterised by second-order intercept point (IP2) and third-order intercept point (IP3) are recapitulated for the proposed zero-IF receiver in accordance with ETSI and EPC global UHF radio frequency identification (RFID) protocols. To improve linearity of the downconversion mixer without noise penalty, the common mode intermodulation signal feedback through the bleeding current path and the inductively degenerated common source transconductance are adopted. The circuitry is demonstrated in 0.18 m standard CMOS process. The average IP3 for 23 samples is of 15 dBm and the IP2 is boosted from 37 to 52 dBm while drawing 8.7 mA from a 3.3 V power supply. These results show that the mixer is also very promising for other high linearity RF receiver applications.     

Analysis and design of a low-voltage RF CMOS mixer

A CMOS low-voltage downconversion mixer is presented. With 1.69-GHz local oscillator signal input and 1.63-GHz RF signal input, measurement results show that the conversion gain is 6.631 dB, input-referred third-order intercept point is 1.51 dBm, single-sideband noise figure is 21.43 dB with a 1.8-V supply voltage. The mixer's noise and linearity analysis, layout technique to maximize RF performance and minimize noise performance are also presented in this paper.     

A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver

A CMOS passive mixer is designed to mitigate the critical flicker noise problem that is frequently encountered in constituting direct-conversion receivers. With a unique single-balanced passive mixer design, the resulted direct-conversion receiver achieves an ultralow flicker-noise corner of 45 kHz, with 6 dB more gain and much lower power and area consumption than the double-balanced counterpart. CMOS switches with a unique bias-shifting network to track the LO DC offset are devised to reduce the second-order intermodulation. Consequently, the mixer's IIP2 has been greatly enhanced by almost 21 dB from a traditional single-balanced passive mixer. An insertion compensation method is also implemented for effective dc offset cancellation. Fabricated in 0.18 /spl mu/m CMOS and measured at 5 GHz, this passive mixer obtains 3 dB conversion gain, 39 dBm IIP2, and 5 dBm IIP3 with LO driving at 0 dBm. When the proposed mixer is integrated in a direct-conversion receiver, the receiver achieves 29 dB overall gain and 5.3 dB noise figure.     

900 MHz CDMA/1.8 GHz PCS/450 MHz CDMA RF receiver ICs with a new mixer linearization method and optimization of integrated inductor for single balance mixer LO buffer

900 MHz CDMA, 1.8 GHz PCS, and 450 MHz CDMA RF receivers are implemented and measured. In order to reduce NRE cost and meet the demand of fast time-to-market, a metal-mask configurable method is applied for those receivers using only upper metals, contact and via layers. Also to reduce power consumption, a new mixer linearization method is proposed, along with an optimization methodology of an integrated inductor for a single balance mixer LO buffer, with respect to power consumption and silicon area. In order to apply the proposed inductor optimization methodology into metal-mask configurable circuits, inductor design considerations for metal-mask variant circuits are presented. With the proposed linearization technique and inductor optimization method, low power 900 MHz CDMA/1.8 GHz PCS/450 MHz CDMA mixers are obtained. The proposed receivers are fabricated in a 0.35 μm SiGe BiCMOS process. In the 900 MHz CDMA case, measurement results of the proposed mixer show 12 dBm IIP3 and 10.2 dB conversion gain, and 7.5 dB SSB NF with 10.5 mA current consumption at 2.7 V supply voltage.     

Design and analysis of an ultrawide-band distributed CMOS mixer

This paper presents the design and analysis of a novel distributed CMOS mixer for ultrawide-band (UWB) receivers. To achieve the UWB RF frequency range required for the UWB communications, the proposed mixer incorporates artificial inductance-capacitance (LC) delay lines in radio frequency (RF), local oscillator (LO), and intermediate frequency signal paths, and single-balanced mixer cells that are distributed along these LC circuits. Closed-form analytical model for the conversion gain of the mixer is presented. Furthermore, a comprehensive noise analysis of the proposed distributed mixer is carried out, which includes calculation of the mixer noise figure (NF) and derivation of the optimum number of stages, n, minimizing the NF. The designed mixer is capable of covering the RF and LO frequencies over a wide range of frequencies from 3.1-8.72 GHz. A two-stage distributed mixer has been fabricated in a 0.18-/spl mu/m CMOS process. Experiments show a conversion gain of more than 2.5 dB for the entire range of the frequencies. The dc power consumption is 10.4 mW.