Electrical and interfacial characteristics of nanolaminate (Al2O3/ZrO2/Al2O3) gate stack on fully depleted SiGe-on-insulator

The structural and electrical characteristics of a novel nanolaminate Al₂O₃/ZrO₂/Al₂O₃ high-k gate stack together with the interfacial layer (IL) formed on SiGe-on-insulator (SGOI) substrate have been investigated. A clear layered Al₂O₃ (2.5 nm)/ZrO₂ (4.5 nm)/Al₂O₃ (2.5 nm) structure and an IL (2.5 nm) are observed by high-resolution transmission electron microscopy. X-ray photoelectron spectroscopy measurements indicate that the IL contains Al-silicate without Ge atom incorporation. A well-behaved C–V behavior with no hysteresis shows the absence of Ge pileup or Ge segregation at the gate stack/SiGe interface.     

Growth behavior and improved water–vapor-permeation-barrier properties of 10-nm-thick single Al2O3 layer grown via cyclic chemical vapor deposition on organic light-emitting diodes

We have investigated the growth behavior and water vapor permeation barrier properties of cyclic chemical vapor deposition (C-CVD)-grown 10-nm-thick single layer of Al₂O₃. Al₂O₃ layers grown by C-CVD showed a high density of 3.298 g/cm³ and were amorphous without grain boundaries. A deposition rate of 0.46 nm/cycle was obtained. The C-CVD system was self-limiting, as in the case of atomic layer deposition, which enables precise control of the thickness of the Al₂O₃ layer. A water vapor transmission rate of 1.51 × 10⁻⁵ (g/m²)/day was obtained from a Ca degradation test performed at 85 °C and 85% relative humidity. Moreover, the performance of organic light-emitting diodes, passivated by a C-CVD-grown 10-nm-thick Al₂O₃ single layer, was not affected after 24,000 h of turn-on time; this is strong evidence that C-CVD-grown Al₂O₃ layers effectively prevent water vapor from diffusing into the active organic layer.     

Improved electrical properties using SrTiO3/Y2O3 bilayer dielectrics for MIM capacitor applications

In this paper, we show that the capacitance–voltage linearity of MIM structures can be enhanced using SrTiO₃ (STO)/Y₂O₃ dielectric bilayers. The C(V) linearity is significantly improved by combining two dielectric materials with opposite permittivity-voltage responses. Three STO/Y₂O₃ stacks with different thicknesses were realized and compared to a 20 nm STO single layer structure. We observed that an increase in the Y₂O₃ thickness leads to an improvement in the voltage linearity, while maintaining an overall capacitance density greater than 10 fF/μm².     

Memory characteristics of Al2O3/La2O3/Al2O3 multi-layer films with various blocking and tunnel oxide thicknesses

In order to investigate charge trap characteristics with various thicknesses of blocking and tunnel oxide for application to non-volatile memory devices, we fabricated 5 and 15 nm Al₂O₃/5 nm La₂O₃/5 nm Al₂O₃ and 15 nm Al₂O₃/5 nm La₂O₃/5, 7.5, and 10 nm Al₂O₃ multi-stack films, respectively. The optimized structure was 15 nm Al₂O₃ blocking oxide/5 nm La₂O₃ trap layer/5 nm Al₂O₃ tunnel oxide film. The maximum memory window of this film of about 1.12 V was observed at 11 V for 10 ms in program mode and at ?13 V for 100 ms in erase mode. At these program/erase conditions, the threshold voltage of the 15 nm Al₂O₃/5 nm La₂O₃/5 nm Al₂O₃ film did not change for up to about 10⁴ cycles. Although the value of the memory window in this structure was not large, it is thought that a memory window of 1.12 V is acceptable in the flash memory devices due to a recently improved sense amplifier.     

Ultra-low-energy ion-beam-synthesis of Ge nanocrystals in thin ALD Al2O3 layers for memory applications

Structural and electrical properties of ALD-grown 5 and 7 nm-thick Al₂O₃ layers before and after implantation of Ge ions (1 keV, 0.5–1 × 10¹⁶ cm^?2) and thermal annealing at temperatures in the 700–1050 °C range are reported. Transmission Electron Microscopy reveals the development of a 1 nm-thick SiO₂-rich layer at the Al₂O₃/Si substrate interface as well as the formation of Ge nanocrystals with a mean diameter of ～5 nm inside the implanted Al₂O₃ layers after annealing at 800 °C for 20 min. Electrical measurements performed on metal–insulator–semiconductor capacitors using Ge-implanted and annealed Al₂O₃ layers reveal charge storage at low-electric fields mainly due to location of the Ge nanocrystals at a tunnelling distance from the substrate and their spatial dispersion inside the Al₂O₃ layers.     

Electrical characterisation and reliability of HfO2 and Al2O3–HfO2 MIM capacitors

Current leakage and breakdown of MIM capacitors using HfO₂ and Al₂O₃–HfO₂ stacked layers were studied. Conduction in devices based upon HfO₂ layers thinner than 8 nm is probably dominated by tunnelling. Al₂O₃–HfO₂ stacked layers provide a limited benefit only in term of breakdown field. Constant-voltage wear-out of samples using insulating layer thicker than 6 nm is dominated by a very fast increase of the leakage current. A two step mechanism involving the generation of a conduction path followed by a destructive thermal effect is proposed to explain breakdown mechanism.     

The structural and electrical properties of the SrTa2O6/In0.53Ga0.47As/InP system

The structural and electrical properties of SrTa₂O₆(SrTaO)/n-In_0.53GaAs_0.47(InGaAs)/InP structures where the SrTaO was grown by atomic vapor deposition, were investigated. Transmission electron microscopy revealed a uniform, amorphous SrTaO film having an atomically flat interface with the InGaAs substrate with a SrTaO film thickness of 11.2 nm. The amorphous SrTaO films (11.2 nm) exhibit a dielectric constant of ∼20, and a breakdown field of >8 MV/cm. A capacitance equivalent thickness of ∼1 nm is obtained for a SrTaO thickness of 3.4 nm, demonstrating the scaling potential of the SrTaO/InGaAs MOS system. Thinner SrTaO films (3.4 nm) exhibited increased non-uniformity in thickness. From the capacitance-voltage response of the SrTaO (3.4 nm)/n-InGaAs/InP structure, prior to any post deposition annealing, a peak interface state density of ∼2.3 × 10¹³ cm⁻² eV⁻¹ is obtained located at ∼0.28 eV (±0.05 eV) above the valence band energy (E_v) and the integrated interface state density in range E_v + 0.2 to E_v + 0.7 eV is 6.8 × 10¹² cm⁻². The peak energy position (0.28 ± 0.05 eV) and the energy distribution of the interface states are similar to other high-k layers on InGaAs, such as Al₂O₃ and LaAlO₃, providing further evidence that the interface defects in the high-k/InGaAs system are intrinsic defects related to the InGaAs surface.     

Improved property in organic light-emitting diode utilizing two Al/Alq3 layers

We reported on the fabrication of organic light-emitting devices (OLEDs) utilizing the two Al/Alq₃ layers and two electrodes. This novel green device with structure of Al(110 nm)/tris(8-hydroxyquinoline) aluminum (Alq₃)(65 nm)/Al(110 nm)/Alq₃(50 nm)/N,N′-dipheny1-N, N′-bis-(3-methy1phyeny1)-1, 1′-bipheny1-4, 4′-diamine (TPD)(60 nm)/ITO(60 nm)/Glass. TPD were used as holes transporting layer (HTL), and Alq₃ was used as electron transporting layer (ETL), at the same time, Alq₃ was also used as emitting layer (EL), Al and ITO were used as cathode and anode, respectively. The results showed that the device containing the two Al/Alq₃ layers and two electrodes had a higher brightness and electroluminescent efficiency than the device without this layer. At current density of 14 mA/cm², the brightness of the device with the two Al/Alq₃ layers reach 3693 cd/m², which is higher than the 2537 cd/m² of the Al/Alq₃/TPD:Alq₃/ITO/Glass device and the 1504.0 cd/m² of the Al/Alq₃/TPD/ITO/Glass. Turn-on voltage of the device with two Al/Alq₃ layers was 7 V, which is lower than the others.     

The electrical and physical analysis of Pt gate/Al<Subscript>2</Subscript>O<Subscript>3</Subscript>/p-Si (100) with dual high-k gate oxide thickness for deep submicron complementary metal-oxide-semiconductor device with low power and high reliability

In order to examine the electrical and physical properties of Al₂O₃ layers with dual thickness on a chip, Pt gate/Al₂O₃ with dual thickness/p-type Si (100) samples were fabricated using atomic-layer deposition, separation photolithography, and 100:1 HF wet etching to remove the first Al₂O₃ layer. Dual metal-oxide-semiconductor (MOS) capacitors with thin (physical thickness, ∼4.5 nm, equivalent oxide thicknesses (EOT): 2.8 nm) and thick (physical thickness, ∼8.2 nm, EOT: 4.3 nm) Al₂O₃ layers showed a good leakage current density of −5.4×10⁻⁶ A/cm² and −2.5×10⁻⁹ A/cm² at −1 V, respectively; good reliability characteristics as a result of the good surface roughness; low capacitance versus voltage measurements (C-V) hysteresis; and a good interface state density (∼7×10¹⁰ cm⁻²eV⁻¹ near the midgap) as a result of pre-rapid thermal annealing (pre-RTA) after depositing the Al₂O₃ layer compared with the single MOS capacitors without the pre-RTA. These results suggest that dual Al₂O₃ layers using the dual gate oxide (DGOX) process can be used for the simultaneous integration of the low power transistors with a thin Al₂O₃ layer and high reliability regions with a thick Al₂O₃ layer.     

Effect of AlN buffer layer thickness on the properties of GaN films grown by pulsed laser deposition

The GaN films are grown by pulsed laser deposition (PLD) on sapphire, AlN(30 nm)/Al₂O₃ and AlN(150 nm)/Al₂O₃, respectively. The effect of AlN buffer layer thickness on the properties of GaN films grown by PLD is investigated systematically. The characterizations reveal that as AlN buffer layer thickness increases, the surface root-mean-square (RMS) roughness of GaN film decreases from 11.5 nm to 2.3 nm, while the FWHM value of GaN film rises up from 20.28 arcmin to 84.6 arcmin and then drops to 31.8 arcmin. These results are different from the GaN films deposited by metal organic chemical vapor deposition (MOCVD) with AlN buffer layers, which shows the improvement of crystalline qualities and surface morphologies with the thickening of AlN buffer layer. The mechanism of the effect of AlN buffer layer on the growth of GaN films by PLD is hence proposed.     

New TIT capacitor with ZrO2/Al2O3/ZrO2 dielectrics for 60 nm and below DRAMs

New ZrO₂/Al₂O₃/ZrO₂ (ZAZ) dielectric film was successfully developed for DRAM capacitor dielectrics of 60 nm and below technologies. ZAZ dielectric film grown by ALD has a mixture structure of crystalline phase ZrO₂ and amorphous phase Al₂O₃ in order to optimize dielectric properties. ZAZ TIT capacitor showed small Tox.eq of 8.5 Å and a low leakage current density of 0.35 fA/cell, which meet leakage current criteria of 0.5 fA/cell for mass production. ZAZ TIT capacitor showed a smaller cap leak fail bit than HAH capacitor and stable leakage current up to 550 °C anneal. TDDB (time dependent dielectric breakdown) behavior reliably satisfied the 10-year lifetime criteria within operation voltage range.     

Growth of epitaxial Pr2O3 layers on Si(1 1 1)

The growth of Pr₂O₃ layers on Si(1 1 1) has been studied by X-ray diffraction, Low-energy electron diffraction (LEED) and atomic force microscopy (AFM). Pr₂O₃ starts to grow as a 0.6-nm thick layer corresponding to one unit cell of the hexagonal phase (1 ML). The X-ray results indicate that layers thicker than 0.6 nm do not grow with the hexagonal phase. Growth takes place at a sample temperature of 500–550 °C. Annealing of the monolayer in UHV at a temperature above 700 °C leads to the formation of Pr₂O₃ and PrSi₂ islands. Silicide islands are found only at annealing in UHV and do not occur at annealing in oxygen atmosphere of 10⁻⁸ mbar. The LEED pattern after heating to 730 °C shows a (2×2) and (√3×√3) superstructure and after heating to 1000 °C a (1×5) superstructure occurs. The superstructures seen in the LEED pattern arise from silicide structures in the area between the islands. The silicide remains on the surface and cannot be removed with flashing to 1100 °C. Further deposition of Pr₂O₃ on the surface covered with silicide phases does not lead to growth of ordered layers.     

Fabrication and characterization of Zr-rich Zr-aluminate films for high-κ gate dielectric applications

Two kinds of Zr-rich Zr-aluminate films for high-κ gate dielectric applications with the nominal composition of (ZrO₂)_0.8(Al₂O₃)_0.2 and (ZrO₂)_0.9(Al₂O₃)_0.1, were deposited on n-type silicon wafer by pulsed laser deposition (PLD) technique at different deposition conditions. X-ray diffraction (XRD) reveals that the (ZrO₂)_0.8(Al₂O₃)_0.2 film could remain amorphous after being rapid thermal annealed (RTA) at the temperature above 800 °C, while the other one displays some crystalline peaks at 700 °C. The energy gap calculated from optical transmittance spectrum of (ZrO₂)_0.8(Al₂O₃)_0.2 film on quartz is about 6.0 eV. Sputtering depth profile of X-ray photoelectron spectroscopy and Auger electron spectroscopy indicate that a Zr-Si-O interfacial layer was formed at the near surface of the silicon substrate. The dielectric constant of the (ZrO₂)_0.8(Al₂ O₃)_0.2 film has been determined to be 22.1 by measuring a Pt/(ZrO₂)_0.8(Al₂ O₃)_0.2/Pt MIM structure. An EOT of 1.76 nm with a leakage current density of 51.5 mA/cm² at 1 V gate voltage for the film deposited in N₂ were obtained. Two different pre-treatments of Si substrates prior to depositions were also carried out and compared. The results indicate that a surface-nitrided Si substrate can lead to a lower leakage current density. The amorphous Zr-rich Zr-aluminate films fabricated by PLD have promising structure and dielectric properties required for a candidate material for high-κ gate dielectric applications.     

Composition and electrical characteristics of Al2O3-HfO2-HfTiO nanolaminates on Si

A dielectric constant of 27 was demonstrated in the as deposited state of a 5 nm thick, seven layer nanolaminate stack comprising Al₂O₃, HfO₂ and HfTiO. It reduces to an effective dielectric constant (k_eff) of ∼14 due to a ∼0.8 nm interfacial layer. This results in a quantum mechanical effective oxide thickness (EOT) of ∼1.15 nm. After annealing at 950 °C in an oxygen atmosphere k_eff reduces to ∼10 and EOT increases to 1.91 nm. A small leakage current density of about 8 × 10⁻⁷ and 1 × 10⁻⁴ A/cm², respectively at electric field 2 and 5 MV/cm and a breakdown electric field of about 11.5 MV/cm was achieved after annealing at 950 °C.     

Two Layer Surface Exfoliation on Si3N4/Si by Sequential Implantation of He and H Ions

n-Type Si(100) wafers with a thermally grown Si₃N₄ layer (∼170 nm) were sequentially implanted with 160 keV He ions at a dose of 5 × 10¹⁶ cm⁻² and 110 keV H ions at a dose of 1 × 10¹⁶ cm⁻². Depending on the annealing temperature, surface exfoliations of two layers were observed by optical microscopy and atomic force microscopy. The first layer exfoliation was found to correspond to the top Si₃N₄ layer, which was produced at lower annealing temperatures. The other was ascribed to the implanted Si layer, which was formed at higher temperatures. The possible exfoliation processes are tentatively discussed, and potential applications of such phenomena are also suggested.     

Charge trapping and interface characteristics in normally-off Al2O3/GaN-MOSFETs

Normally-off GaN-MOSFETs with Al₂O₃ gate dielectric have been fabricated and characterized. The Al₂O₃ layer is deposited by ALD and annealed under various temperatures. The saturation drain current of 330 mA/mm and the maximum transconductance of 32 mS/mm in the saturation region are not significantly modified after annealing. The subthreshold slope and the low-field mobility value are improved from 642 to 347 mV/dec and from 50 to 55 cm² V⁻¹ s⁻¹, respectively. The I_D-V_G curve shows hysteresis due to oxide trapped charge in the Al₂O₃ before annealing. The amount of hysteresis reduces with the increase of annealing temperature up to 750 °C. The Al₂O₃ layer starts to crystallize at a temperature of 850 °C and its insulating property deteriorates.     

A flexible moisture barrier comprised of a SiO2-embedded organic–inorganic hybrid nanocomposite and Al2O3 for thin-film encapsulation of OLEDs

We demonstrated a high performance flexible multi-barrier containing a silica nanoparticle-embedded organic–inorganic hybrid (S–H) nanocomposite and Al₂O₃. The multi-barrier was prepared by low-temperature Al₂O₃ atomic layer deposition and with a spin-coated S–H nanocomposite. The moisture barrier properties were investigated with a water vapor transmission rate (WVTR), estimated by a Ca test at 30 °C, 90% R.H.. Moisture diffusion was effectively suppressed by the sub-700 nm thick multi-barrier incorporating well-dispersed silica nanoparticles in the organic layer. A low WVTR of 1.14 × 10^?5 g/m² day and average transmittance of 85.8% in the visible region were obtained for the multi-barrier. After bending under tensile stress mode, the moisture barrier property of the multi-barriers was retained. The multi-barrier was successfully applied to thin-film encapsulation of OLEDs. The thin-film encapsulated OLEDs showed practicable current–voltage–luminance (I–V–L) characteristics and stable real operation over 700 h under ambient conditions.     

Degradation kinetics of ultrathin HfO2 layers on Si(1 0 0) during vacuum annealing monitored with in situ XPS/LEIS and ex situ AFM

The evolution of HfO₂(3–5 nm)/SiO₂(0.5 nm)/Si(1 0 0) stacks during vacuum annealing was monitored in situ with the combination of X-ray photoelectron spectroscopy and low energy ion scattering techniques and supplemented with atomic force microscopy analysis to investigate the mechanism that triggers HfO₂ degradation with Hf silicide formation. The reduction of SiO₂ interfacial layer and the formation of local paths for SiO escape into vacuum are believed to be critical at vacuum annealing above T > 850 °C for the reaction between HfO₂ and Si to start and eventually lead to the degradation of the former.     

Surface modification of polymeric substrates to enhance the barrier properties of an Al2O3 layer formed by PEALD process

Aluminum oxide (Al₂O₃) layers were deposited on various polymeric substrates by a low frequency plasma-enhanced atomic layer deposition (PEALD) process. Polyethylene naphthalate (PEN), polyethylene terephthalate (PET), and polyethersulfone (PES) were tested as substrates for barrier films. Each substrate has its own characteristics to have influences on the Al₂O₃ layer formation and penetration into the substrate, which greatly affected the barrier properties. Prior to the deposition process, polymeric substrates were pretreated in argon and oxygen plasmas, and surface energy was leveled up due to the formation of polar group. Characterizations of the Al₂O₃ layer by Time of Flight - Secondary Ion Mass Spectrometry (ToF-SIMS) revealed that plasma treatment lowered the level of OH⁻ in Al₂O₃ layer. X-ray photoelectron microscopy (XPS) confirmed that A12p peak of Al₂O₃ layer was shifted to a higher core level by plasma treatment. Density of the layer on the plasma treated surface was greater than that of untreated surface. It was found that plasma treatment of the surface had significant effects on the formation of the Al₂O₃ layer, which much improved the barrier performance. Optical transmittance was little affected by plasma treatment and PEALD process. After oxygen plasma pretreatment, the WVTR of the Al₂O₃ layer deposited on the plasma-treated PEN substrate was around 7.2 × 10⁻⁴ g/m²day, which is significantly lower than that of the untreated substrate.     

用闪光灯泵浦Cr3+:GSAG和Cr3+:GSGG的斜率效率、腔结构、色心及其可调谐性

Cr3+:Gd3Sc2Al3O12(GSAG)和Cr3+:Gd3Sc2Ga3O12(GSGG)属弱场石榴石晶体,室温下,能输出脉冲可调谐激光。我们用2英寸长的Cr3+:GSAG 激光棒得到了200mJ的多模输出,其可调谐范围为700～800nm。