Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy

Forward body biasing is a promising approach for realizing optimum threshold-voltage (V _TH) scaling in the era when gate dielectric thickness can no longer be scaled down. This is confirmed experimentally and by simulation of a 10-nm gate length MOSFET. Because forward body bias (VF) decreases the depletion width (X _DEP) in the channel region, it reduces V _TH rolloff significantly. MOSFET performance is maximized under forward body bias with steep retrograde channel doping, and such channel doping profiles are required to accomplish good short-channel behavior (small X _DEP ) at low V _TH notwithstanding body bias; therefore, the combination of forward body biasing with steep retrograde channel doping profile can extend the scaling limit of conventional bulk-Si CMOS technology to 10-nm gate length MOSFET. Considering forward biased p-n junction current, parasitic bipolar transistor, and CMOS latch-up phenomena, the upper limit for |VF| should be set at 0.6-0.7 V, which is sufficient to realize significant advantages of forward body biasing.     

Power Optimization for SRAM and Its Scaling

With technology scaling, there is a strong demand for smaller cell size, higher speed, and lower power in SRAMs. In addition, there are severe constraints for reliable read-and-write operations in the presence of increasing random variations that significantly degrade the noise margin. To understand these tradeoffs clearly and find a power-delay optimal solution for scaled SRAM, sequential quadratic programming is applied for optimizing 6-T SRAM for the first time. The use of analytical device models for transistor currents and formulate all the cell-operation requirements as constraints in an optimization problem. Our results suggest that, for optimal SRAM cell design, neither the supply voltage (V_dd) nor the gate length (L_g) scales, due to the need for an adequate noise margin amid leakage and threshold variability and relatively low dynamic activity of SRAM. This is true even with technology scaling. The cell area continues to scale despite the nonscaling gate length (L_g) with only a 7% area overhead at the 22-nm technology node as compared to simple scaling, at which point a 3-D structure is needed to continue the area-scaling trend. The suppression of gate leakage helps to reduce the power in ultralow-power SRAM, where subthreshold leakage is minimized at the cost of increase in cell area     

At-Bias Extraction of Access Parasitic Resistances in AlGaN/GaN HEMTs: Impact on Device Linearity and Channel Electron Velocity

AlGaN/GaN high-electron mobility transistor "hot" parasitic source and drain resistances R_S,D are determined under operating biases through wideband S-parameter measurements, without the use of "ColdFET" biasing conditions. Both R_S and R_D are found to increase dramatically over ColdFET values, both for biases approaching threshold and for open-channel conditions. Parasitic resistance values have a significant effect on the extracted small-signal equivalent circuit model elements, as well as on the apparent device linearity. The bias dependence of access resistances modifies the understanding of the transistor physical operation: A revised delay time analysis accounting for the bias dependence of parasitic resistances shows that the effective average electron velocity in the AlGaN/GaN two-dimensional electron-gas channel is approximately equal to 1.9 times 10⁷ cm/s. This new value of channel velocity is also consistent with the C_GS/g_MO ratio obtained when the bias dependence of R_S and R_D is accounted for during the extraction of the transistor small-signal equivalent circuit model     

The effects of source/drain resistance on deep submicrometer deviceperformance

As MOSFET channel lengths approach the deep-submicrometer regime, performance degradation due to parasitic source/drain resistance (R _sd) becomes an important factor to consider in device scaling. The effects of R_sd on the device performance of deep-submicrometer non-LDD (lightly doped drain) n-channel MOSFETs are examined. Reduction in the measured saturation drain current (R_sd=600 Ω-μm) relative to the ideal saturation current (R_sd=0.0 Ω-μm) is about 4% for L_eff=0.7 μm and T_ox =15.6 nm and 10% for L_eff=0.3 μm and T _ox=8.6 nm. Reduction of current in the linear regime and reduction of the simulated ring oscillator speed are both about three times higher. The effect of salicide technologies on device performance is discussed. Projections are made of the ultimate achievable performance     

Effects of Parasitic Capacitance, External Resistance, and Local Stress on the RF Performance of the Transistors Fabricated by Standard 65-nm CMOS Technologies

Effects of parasitic capacitance, external resistance, and local stress on the radio-frequency (RF) performance of the transistors fabricated by 65-nm CMOS technology have been investigated. The effect of parasitic capacitance, particularly C_gb, becomes significant due to the reduced spacing between the gate and the substrate contact (SC) in proportion to scaling down. Current drivability (I_dsat) per unit width has been improved through introduction of mobility enhancement techniques. The influence of external resistance becomes more pronounced for large-dimensional RF transistors due to severe IR drop. Such improved current drivability and large external resistance is responsible for dc performance (g_m) degradation and, eventually, cutoff frequency (f_T) degradation. Local stress effects associated with silicon nitride capping layer and STI stress have been investigated. f_T is largely affected by local stress change, i.e., g_m degradation at minimal gate poly (GP) pitch and gate-to-active spacing, f_T is dominated by increased parasitic capacitance (C_gb) with increasing GP pitch and gate-to-active spacing. Above 10% improvement in f_T has been observed through layout optimization for C_gb reduction by increasing the transistor active-to-SC spacing.     

New channel engineering for sub-100 nm MOS devices considering bothcarrier velocity overshoot and statistical performance fluctuations

We introduce a new channel engineering design for nano-region SOI and bulk MOSFETs taking into account both carrier velocity overshoot and statistical performance fluctuations. For types of both device, in the high gate drive region, the high field carrier velocity υ_e is not degraded at channel dopant density N_a lower than 1×10¹⁷ cm^-3, according to an experimental universal relationship between υ_e and the low field mobility. On the other hand, there is a most suitable N_a condition for suppression of statistical threshold voltage fluctuations. This most suitable N_a is slightly higher for SOI devices than that for bulk MOSFETs, but it is lower than 1×10 ¹⁷ cm^-3 in both cases. Therefore, this most suitable N_a condition is consistent with the above N_a condition for carrier velocity. Consequently, new N_a conditions for nano region devices are introduced in this study. N_a should be designed to be of the order of 1×10¹⁶ cm^-3 rather than rising by the usual scaling rule, but it is necessary to suppress the short channel effects of SOI and bulk MOSFETs by scaling down the SOI thickness, and to use source/drain junction depth scaling or surface low impurity structures in bulk MOSFETs, respectively     

Counter doping into uniformly and heavily doped channel region ofsub-0.1 μm SOI MOSFETs

We proposed counter doping into a heavily and uniformly doped channel region of SOI MOSFETs. This enabled us to suppress the short channel effects with proper threshold voltage V_th and to eliminate parasitic edge or back gate transistors. We derived a model for V_th as a function of the projected range, Rp and dose, Φ_D, of the counter doping, and showed that V_th is invariable even when the as-implanted counter doping profile redistributes. Using this technology, we demonstrated a V_th roll-off free 0.075 μm-L_Geff nMOSFET with low off-state current     

A physical model of floating body thin film silicon-on-insulatornMOSFET with parasitic bipolar transistor

An analytical model for SOI nMOSFET with a floating body is developed to describe the I_ds-V_ds characteristics. Considering all current components in MOSFET as well as parasitic BJT, this study evaluates body potential, investigates the correlations among many device parameters, and characterizes the various phenomena in floating body: threshold voltage reduction, kink effect, output conductance increment, and breakdown voltage reduction. This study also provides a good physical insight on the role of the parasitic current components in the overall device operation. Our model explains the dependence of the channel length on the I_ds-V_ds characteristics with parasitic BJT current gain. Results obtained from this model are in good agreement with the experimental I_ds-V _ds curves for various bias and geometry conditions     

Bias-dependent linear scalable millimeter-wave FET model

This paper describes a measurement-based bias-dependent linear equivalent circuit field-effect-transistor/high-electron-mobility-transistor model that is accurate to at least 100 GHz and scalable up to 12 parallel gate fingers and from 100 to 1000 μm total gate width. A new and accurate technique for extracting the Z-shell parameters has been developed, and the scaling rules for all the parasitic elements have been determined. The intrinsic equivalent circuit element values are determined at each bias point in V_ge-V_ds space and interpolated by splines between points     

A new extraction algorithm for the metallurgical channel length ofconventional and LDD MOSFETs

A new extraction algorithm for the metallurgical channel length of conventional and LDD MOSFETs is presented, which is based on the well-known resistance method with a special technique to eliminate the uncertainty of the channel length and to reduce the influence of the parasitic source/drain resistance on threshold-voltage determination. In particular, the metallurgical channel length is determined from a wide range of gate-voltage-dependent effective channel lengths at an adequate gate overdrive. The 2-D numerical analysis clearly show that adequate gate overdrive is strongly dependent on the dopant concentration in the source/drain region. Therefore, an analytic equation is derived to determine the adequate gate overdrive for various source/drain and channel doping. It shows that higher and lower gate overdrives are needed to accurately determine the metallurgical channel length of conventional and LDD MOSFET devices, respectively. It is the first time that we can give a correct gate overdrive to extract L_met not only for conventional devices but also for LDD MOS devices. Besides, the parasitic source/drain resistance can also be extracted using our new extraction algorithm     

Impact of High-k Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs

The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance C_of in addition to an increase in the internal fringe capacitance C_if with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering     

Speed and power scaling of SRAM's

Simple models for the delay, power, and area of a static random access memory (SRAM) are used to determine the optimal organizations for an SRAM and study the scaling of their speed and power with size and technology. The delay is found to increase by about one gate delay for every doubling of the RAM size up to 1 Mb, beyond which the interconnect delay becomes an increasingly significant fraction of the total delay. With technology scaling, the nonscaling of threshold mismatches in the sense amplifiers is found to significantly impact the total delay in generations of 0.1 μm and below     

A physical model of floating body effects in polysilicon thin film transistors

Based on a closed form of the base–emitter voltage of the parasitic bipolar transistor, a physical model of floating body effects is proposed for polysilicon thin film transistors, which takes into account the polysilicon graded pn junction and the generation rate including the Poole-Frenkel effect. Simulated results by this model are in good agreement with experimental data. It is shown that the action of a parasitic bipolar transistor should be taken into account only when the channel length is short enough due to the much smaller carrier mobility in polysilicon compared with single crystalline silicon. Whereas, the parasitic bipolar transistor gain (β) increases sharply with decreasing the channel length when the channel length is less than 5 μm, which is due to the rapid increase of the base transport factor (_T).     

Flicker Noise and Its Degradation Characteristics Under Electrical Stress in MOSFETs With Thin Strained-Si/SiGe Dual-Quantum Well

This letter reports on the low-frequency flicker-noise characteristics in fresh and electrically stressed pMOSFETs with thin strained-Si (~4 nm)/Si_0.6Ge_0.4 (~4 nm) dual-quantum-well (DQW) channel architectures. Normalized power spectral density (NPSD) of I_d fluctuations (S_ID/I_d ²) in fresh DQW devices exhibits significant improvement (by >10²times) due to buried channel operation at low V_g. At high V_g, the NPSD enhancement reduces as carriers populate in the parasitic surface channel. Upon electrical stress, noise behavior in DQW devices was found to evolve from being carrier number-fluctuation dominated to mobility- fluctuation dominated. This was accompanied by the observation of a "less-distinct" buried-channel operation, indicating a potential stability issue of the Si/SiGe structure.     

Striped-channel InAlAs/InGaAs HEMTs with shallow-grating structures

Striped-channel (SC) InAlAs/InGaAs HEMTs have been demonstrated with shallow gratings. The shallow grating structure keeps the gate from touching the channel layer and thus solves the gate leakage problem observed in the deep grating devices on InP substrates. Various channel widths have been realized to study the impact of the channel width on the dc and microwave performance. Due to the enhanced charge control in the SC HEMTs, enhanced transconductance/source-drain current (G_m /I_ds) and transconductance/output conductance (G_m /G_ds) were observed. Compared with conventional HEMTs, the SC HEMTs showed degraded f_T due to additional parasitic capacitances and improved f_max due to better carrier confinement     

The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

Submicrometre gate length scaling of inversion channelheterojunction field effect transistor

The scaling to 0.5 μm of the inversion channel HFET with a single strained InGaAs quantum well is described. A unity current gain frequency of 40 GHz, g_m=205 mS/mm and V_TH=-0.34 V have been obtained for 0.5×100 μm² devices. For shorter gate lengths, threshold shifts are sizeable so that in order to scale further, modifications to the growth and processing are required     

A gate-quality dielectric system for SiGe metal-oxide-semiconductordevices

The authors present a high-quality dielectric system for use with Si_1-xGe_x alloys. The system employs plasma-enhanced chemical vapor deposited (PECVD) SiO₂ on a thin (6-8-nm) layer of pure silicon grown epitaxially on the Si_1-x Ge_x layer. The buffer layer and the deposited oxide prevent the accumulation of Ge at the oxide-semiconductor interface and thus keep the interface state density within acceptable limits. The Si cap layer leads to a sequential turn-on of the Si_1-xGe_x channel and the Si cap channel as is clearly observed in the low-temperature C-V curves. The authors show that this dual-channel structure can be designed to suppress the parasitic Si cap channel. The MOS capacitors are also used to extract valence-band offsets     

High-breakdown AlGaAs/InGaAs/GaAs PHEMT with tellurium doping

The authors report the fabrication and characterisation of an Al _0.43Ga_0.57As/In_0.2Ga_0.8 As/GaAs pseudomorphic HEMT (PHEMT) with high channel conductivity grown by solid source MBE. The high conductivity of the channel is a direct consequence of the high sheet charge and high mobility that has recently been obtained by using tellurium as the n-type dopant in 43% AlGaAs. The device characteristics reflect the resulting reduction in the parasitic resistances of the high channel conductivity. Microwave measurements yield a short-circuit current gain cutoff frequency f_T of 11 GHz and maximum oscillation frequency f_max of 25 GHz. A high gate-drain breakdown voltage of 26 V along with a maximum drain current density of 400 mA/mm obtained in the device illustrate the applicability of this technology in microwave power field effect transistors     

Device scaling effects on hot-carrier induced interface andoxide-trapped charge distributions in MOSFETs

The influence of channel length and oxide thickness on the hot-carrier induced interface (N_it) and oxide (N_ot) trap profiles is studied in n-channel LDD MOSFET's using a novel charge pumping (CP) technique. The technique directly provides separate N_it and N_ot profiles without using simulation, iteration or neutralization, and has better immunity from measurement noise by avoiding numerical differentiation of data. The N_it and N_ot profiles obtained under a variety of stress conditions show well-defined trends with the variation in device dimensions. The N_it generation has been found to be the dominant damage mode for devices having thinner oxides and shorter channel lengths. Both the peak and spread of the N_it profiles have been found to affect the transconductance degradation, observed over different channel lengths and oxide thicknesses. Results are presented which provide useful insight into the effect of device scaling on the hot-carrier degradation process