共查询到20条相似文献,搜索用时 31 毫秒
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导航星表构建是星敏感器设计阶段的重要工作.对于小视场,受限于恒星分布规律,易出现导航星表空洞问题.为解决小视场条件下均匀完备导航星表构建问题,对基于球面螺旋基准点的导航星表构建方法进行了改进:摒弃了原方法通过改变球面螺旋基准点数量和位置重新构建导航星表的思路,转而通过增选部分恒星来达到减少星表空洞的目的.设立了描述恒星消除星表空洞能力的权值,并以该权值递减顺序开展恒星增选;同时,设计了增选恒星距离阈值条件以保持增选后导航星表的均匀性.仿真表明,在4圆形视场条件下,相对于原方法,文中方法得到的导航星表,总星数减少708颗,均匀性指标提高约44%,而星表空洞变化较小,显示了较好的性能. 相似文献
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为提高星敏感器的星图预处理速度,减少嵌入式资源消耗,提出了一种并行流水线算法.剔除了星像点本身对背景噪声标准差(噪声水平)和均值两个特征值估计的影响,建立了是否开展滤噪的准则,确定了星图噪声的提取阈值,保证了质心定位精度.将星图缓存量降低至两行数据,用100个移位寄存器记录连通域标号,解决了嵌入式资源浪费和连通域溢出问题.仿真结果表明,50 M速率输入的496×496星图流水处理完成后延迟10 μs便可实时输出需要的亮星数据,使用的存储器和寄存器资源不到80 kB.加入背景电平和高斯噪声后,在信噪比大于1的条件下质心精度优于1/23像素量级,验证了并行流水线的实时星图预处理算法的有效性,有助于提高星敏感器数据输出率及抗动态性能. 相似文献
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天文导航具有自主性强、精度高和误差不随时间积累等优点,惯性导航系统常采用天文观测的方法来提高定位和定姿精度,全天时星跟踪器技术成为近年来国内研究的热点。近红外系统多基于 2MASS 星表产生导航星表,系统工作中需要对可观测恒星进行排序,实现对恒星的最优选择。本文阐述了2MASS近红外恒星的测星能力计算方法,利用给出的信噪比(Signal noise ratio: SNR)计算公式,对一组亮背景条件下的恒星 SNR 进行了计算,并据此进行了理论排序。 利用外场观星试验拍摄的星图,计算了恒星星点的 SNR,并按照实测星点 SNR 对恒星进行了排序。计算结果表明:导航恒星的理论 SNR 与实测 SNR 的排序结果完全一致。 相似文献
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A Boltzmann entropy-based guide star selection algorithm is presented. The guide stars generated by this algorithm satisfy uniform distribution, while there are at least two guide stars measured in any possible boresight direction of the star tracker. A guide star catalogue with a 14/spl deg//spl times/14/spl deg/ square field of view is reported. 相似文献
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星点测量精度是表征星敏感器精度的一个重要指标,影响该精度的主要因素有:光学系统误差、图像传感器的噪声、电路噪声及软件算法等。图像传感器的噪声对星点定位精度的影响是不容忽视的,但很少对此进行研究。针对某给定参数的星敏感器,对TH7890M CCD图像传感器的各项噪声进行了定量计算;基于亚像素细分质心算法,针对各噪声的分布特点及规律,分别推导出各自的均方根误差,综合各项误差得到CCD噪声的星点定位精度模型。计算结果表明TH7890M CCD的主要噪声有读出噪声、光子散粒噪声和光响应不均匀性引起的随机噪声;影响星敏感器星点定位精度的主要噪声是读出噪声和光子散粒噪声;对6等星进行星点位置的估计,CCD噪声达到了1/40像素的精度水平。 相似文献
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为提高微型星敏感器的质心定位精度,提出了一种利用外差式激光干涉装置标定图像传感器像素位置偏差的方法,并就像素位置偏差对星点像质心定位精度的影响进行了仿真研究。在噪声忽略不计的情况下,当像素位置偏差服从(-0.02,0.02)上的均匀分布时,补偿系统误差能够使星点定位精度从0.008 pixel提高到0.002 pixel。而如果加入服从N(0,5.52)的高斯白噪声,当像素位置偏差服从(-0.02,0.02)上的均匀分布时,补偿像素位置偏差能使定位精度从0.020 pixel提高到0.018 pixel;当像素位置偏差服从(-0.04,0.04)上的均匀分布时,补偿像素位置偏差能使定位精度从0.026 pixel提高到0.018 pixel,提高了31%。这说明标定像素位置偏差对提升质心定位精度有显著作用,为发展高精度微型星敏感器提供了一种新的技术手段。 相似文献
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《Electron Devices, IEEE Transactions on》2003,50(1):57-62
Most CMOS image sensors today use the rolling shutter approach to control the integration time. This pixel architecture is advantageous where minimal pixel size is required to increase resolution or reduce over all chip size. For imaging of a fast moving object or when used with pulsed illumination, the rolling shutter approach is not suitable since it leads to severe distortion. Therefore, these applications require image sensors with a global shutter pixel architecture, which incorporates a sample-and-hold element in each pixel. Due to the optical exposure of the in-pixel storage element, shutter leakage is critical. First approaches which use separate wells in the pixel to isolate the storage node from the photodiode showed good shutter efficiency, but are bulky and led to large pixels with poor fill factor and bad responsivity. This paper presents an NMOS-only pixel with a global shutter and subthreshold operation of the NMOS sample-and-hold transistor to increase optical responsivity by a factor of five to 9 /spl upsi/V/photon, including fill factor. 相似文献
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This paper presents a 256×256 pixel smart CMOS image sensor for line based vision applications. By combining the edge-based analog processing technique with an active pixel array, a dense and fast on-chip analog image processing has been achieved. The on-chip processing unit includes (1) an analog histogram equalizer, (2) a programmable recursive Gaussian filter, (3) a spatio-temporal differentiator, and (4) a local extrema extractor. An electronic shutter is applied to the active pixel sensor array in order to adapt the exposure time as a function of global illumination. The on-chip histogram equalizer extends the image into a constant and optimal range for all the following processing operators and gives a stable and predictable precision of the analog processing. A prototype chip has been designed and fabricated in a standard 0.8-μm CMOS process with double poly and double metal, giving a pixel pitch of 20 μm and die size of 7×7 mm2. A line processing time is compatible with TV line scan period. The worst case power consumption measures 40 mA at 5 V 相似文献
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A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters 总被引:4,自引:0,他引:4
Furuta M. Nishikawa Y. Inoue T. Kawahito S. 《Solid-State Circuits, IEEE Journal of》2007,42(4):766-774
This paper presents a high-speed, high-sensitivity 512times512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge amplifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-mum CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lxmiddots. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8mVrms, and the resulting signal dynamic range is 60 dB 相似文献
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针对帧转移结构电子倍增电荷耦合器件(EMCCD)对高速运动目标成像模糊、高亮度目标成像饱和且细节缺失的问题,提出了利用抗光晕通道倾泻多余电荷和外部时序控制的电子快门方法,通过帧转移时序将感光区电荷转移到与存储区相邻的抗光晕沟道进行倾泻,实现标准视频连续输出中1/25~1/1 000 s连续可调的电子快门,并推导了抗光晕漏极最大倾泻电流与光照强度之间的数学关系式;使用FPGA硬件图像处理消除了曝光时间缩短引起的漏光-拖尾(smear)效应;采用带有抗光晕结构的帧转移EMCCD开发了原理相机进行实验验证。结果表明,通过该方法控制电子快门可以有效降低旋转运动目标的成像模糊,并实现夜间的高动态范围夜视成像,显著提升图像细节。 相似文献
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星敏感器是当前广泛应用于航天器姿态测量的高精度光学姿态敏感器。介绍了一种新型分体式星敏感器的总体设计、应用及验证情况,其已成功应用于科学试验、通讯及地球观测等多种卫星平台,共有21套产品在轨验证。根据在轨遥测数据分析,全面验证了其主要技术指标:探测灵敏度5.7Mv、数据更新率8Hz、测量精度2.6、阳光抑制角28、动态性能1()/s等。新型分体式星敏感器是国际上首个在轨飞行验证并引入控制系统闭环控制的APS星敏感器,根据地面测试验证结果和20余套产品长达两年在轨数据的全面分析,其在轨性能与地面测试性能一致,在轨测试结果证明产品的测量精度、鲁棒性、可用性和可靠性等主要性能满足卫星使用要求。 相似文献
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Dominique Ginhac Jérôme Dubois Barthélémy Heyrman Michel Paindavoine 《Analog Integrated Circuits and Signal Processing》2010,65(3):389-398
A high speed analog VLSI image acquisition and low-level image processing system is presented. The architecture of the chip
is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling
the computation of programmable mask-based image processing in each pixel. Each pixel include a photodiode, an amplifier,
two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A 64 × 64 pixel proof-of-concept
chip was fabricated in a 0.35 μm standard CMOS process, with a pixel size of 35 μm × 35 μm. The chip can capture raw images
up to 10,000 fps and runs low-level image processing at a framerate of 2,000–5,000 fps. 相似文献
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An improved global shutter pixel structure with extended output range and linearity of compensation is proposed for CMOS image sensor. The potential switching of the sample and hold capacitor bottom plate outside the array is used to solve the problem of the serious swing limitation, which will attenuate the dynamic range of the image sensor. The non-linear problem caused by the substrate bias effect in the output process of the pixel source follower is solved by using the mirror FD point negative feedback self-establishment technology outside the array. The approach proposed in this paper has been verified in a global shutter CMOS image sensor with a scale of 1024×1024 pixels. The test results show that the output range is expanded from 0.95V to 2V, and the error introduced by the nonlinearity is sharply reduced from 280mV to 0.3mV. Most importantly, the output range expansion circuit does not increase the additional pixel area and the power consumption. The power consumption of linearity correction circuit is only 23.1μW, accounting for less than 0.01% of the whole chip power consumption. 相似文献
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基于背景抑制的星空图像目标运动轨迹提取 总被引:5,自引:1,他引:4
研究了空间观测CCD图像弱小目标检测与运动轨迹提取技术,介绍了一种基于背景抑制的多目标检测与运动轨迹提取方法。首先,对图像进行阈值处理,滤除图像的背景灰度和噪声;然后生成基于序列图像叠加与形态学变换相结合的背景掩模图像,对序列图像进行屏蔽处理,得到运动目标图像;对目标图像进行交叉投影算法确定目标区域,并进一步精确确定目标质心,进而提取目标的运动轨迹。实验证明所提出的算法不仅能够有效检测星空序列图像中的多个弱信号小目标,而且具有较强的实时性。 相似文献
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《Electron Devices, IEEE Transactions on》2006,53(8):1797-1804
This paper describes very large scale integration implementation using a new vision chip architecture specialized for target tracking and recognition. A 64$times$ 64 pixel prototype vision chip and its evaluation results are shown. The extraction algorithms of both higher order local autocorrelation (HLAC) features and moment features are implemented on the prototype chip in order to achieve high-speed image processing and enhanced pixel integration. The chip is integrated on a 5.00 mm$times$ 5.00 mm chip using a 0.35-$muhboxm$ CMOS DLP/TLM process; the pixel size is$hbox44.2 muhboxm times hbox48.3 muhboxm$ . The maximum current consumption is approximately 400 mA, and the chip can calculate all HLAC features more than 26 times in 1 ms. The experimental results also demonstrate that the chip can successfully recognize and count high-speed objects at real time. 相似文献