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为了提高脉冲功率装置的使用寿命,研究了SrTiO3 基高压陶瓷电容器在有10Ω 负载和无负载两种条件下持续充
放电过程中的使用寿命。详细分析了电容器使用寿命随着充电电压的增加而减小的原因,充电电压的增加会导致电容器
充放电过程中陶瓷介质所受的电致应力和温度增加,从而加快了放电通道的发展和漏电流的增加,导致了电容器寿命的
缩短。详细分析了放电回路负载的存在使电容器寿命增加的原因。放电回路负载的存在使得电容器温度增加变慢,从而
减慢了电容器充放电过程中击穿的发展速度。在无负载持续充放电的条件下,要使电容器的充放电寿命增加到105 次,
充电电压需要减小到~70%额定电压;在有10Ω 负载持续充放电的条件下,要使电容器的充放电寿命增加到105 次,充电
电压需要减小到~80%额定电压。 相似文献
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《中国无线电电子学文摘》2005,(1)
0463 2005010061流状电极结构对大气压表面放电的影响/张锐,汪磊,徐蕾,程诚,詹如娟(中国科技大学)11真空科学与技术学报一2004,24(3)一216一218研究了梳状电极结构对大气压表面放电的影响,发现频率固定时放电电流随着外加电压的增加而增加,而电压固定时在某个颇率范围内放电电流有最大值;在相同的电压和频率下较宽的电极条宽可以产生较大的放电电流,而电极条间距又们玫电电流几乎没有影响;用整块金属板做接地电极相比于梳状接地电极可以产生较大的放电电流;另外,较厚的电压电极可以在介质板表面产生更明亮、厚度更大的放电等离子体.图5参5(… 相似文献
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为了研究脉冲CO2激光诱导空气放电的特性,建立了高压电容充放电实验平台,采用间距为8mm、半径为10mm的一对球形石墨电极,取得了放电电压和电流的实时数据,采用2阶振荡电路模型对放电电压和放电电流进行拟合得到了电极间激光诱导放电等离子体的阻抗,并对放电时间、放电延时及抖动做了统计。结果表明,激光诱导放电等离子体的阻抗很小,约1Ω~2Ω,拟合得到的放电等离子体阻抗随放电电压、放电电容、以及激光能量的增加而减小;放电延时随着实验条件的变化在2μs~10μs之间变化,放电延时以及延时抖动随着放电电压和激光能量的增加而降低,而受放电电容大小的影响不明显。由此高稳定性的激光脉冲和高压有助于激光诱导放电过程的稳定。 相似文献
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脉冲氙灯电源的主放电回路中,放电电流脉冲波形与充电电压、回路中 LC 参量的关系已有文章论述。当充电电压超过某个临界值后,放电电流脉冲底宽可用 T≈(LC)~(1/2)近似估计,半宽度可用 T≈2.6(LC)~(1/2)来描述。低重复率脉冲电源中限流电阻阻值大小影响充电速度,也可参见文献。本文研究低重复率脉冲氙灯电源充电回路中限流电阻 R 对放电电流波形的影响。 相似文献
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对基于AC-Link 技术串联谐振高压充电电源的串并联特性进行了研究,对电源模块参数差异和模块间同步对
多个模块串并联特性进行了分析,研究结果表明:电源模块参数差异和模块间同步对电源并联特性没有影响,电源模
块参数差异,导致输出平均电流大小不一致,随着充电时间的延长,串联模块间输出电压差异越大,模块间不同步时
间决定串联模块间输出电压的差异,不随充电时间变化。研制了两台充电速率30kJ/s,输出电压30kV 的高压充电电源
进行实验验证,实验结果表明:充电充电源可工作于串并联两种工作模式,串联工作时输出电压为60kV,电源模块输
出电压差异小于负载电压的2.5%。 相似文献
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《电子科技文摘》2000,(3)
Y99-61987-707 0003653铅酸蓄电池的放电与充电模拟=Discharge and chargemodeling of lead acid batteries[会,英]/Rynkiewicz,R.//1999 IEEE 14th Applied Power Electronics Confer-ence,Volume 2.—707~710(PC)有效的安培/小时(Ah)放电容量是放电率(电流)的指数函数。放电与充电可逆地氧化/还原电极的活性材料。放电还产生水电极。终端电压表明充电与放电之问的滞后现象。曾报道过的电压均衡系统测试展现了蓄电池对电路阻抗的灵敏度。参9 相似文献
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为了改善现有CO2激光器工频LC谐振充电时充电电压随激光器工作频率升高而降低、影响激光输出的稳定性和光束质量,不利于装置的小型化和轻量化的问题。采用全桥逆变结构和串联谐振软开关电路,研究了36kV/10kW高频高压充电电源。该电源系统采用三相380V交流电作为供电系统,大功率智能功率模块作为全桥逆变电路。逆变交流信号经串联谐振电路及高频脉冲变压器得到高压脉冲信号,高压脉冲经整流给负载电容充电,电源应用电压电流双闭环控制系统,输出电压、电流经采样及放大后,反馈到电源控制芯片SG3525,芯片SG3525通过判断反馈信号的大小,控制输出脉冲宽度调制驱动信号的占空比。激光器放电频率为25Hz时,电源输出电压为37kV,峰值输出功率为13.05kW,充电效率为0.826。结果表明,该高频高压充电电源适合用作CO2激光器的高压充电电源。 相似文献
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Fujiwara Osamu 《电子科学学刊(英文版)》2008,25(3):384-388
Characteristic measurement of contact discharge currents are made through a hand-held metal rod from charged human body. Correlation coefficients are obtained, through Statistic Package for Social Science (SPSS), for various charge voltages, which is based on the effect test of electrode contact approach speeds on discharge current parameters of current peaks, maximum rising slope and spark lengths. Discharge parameters at charge voltage 300V are independent on approach speed. For charge voltages equal to and higher than 500V, the contact approach speed has strong positive correlation with discharge parameters of the peak current and the maximum rising slope, whereas has strong negative correlation with the spark length. 相似文献
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Yeu-Haw Yang Chung-Yu Wu 《Electron Devices, IEEE Transactions on》1989,36(7):1336-1347
A criterion for transient latchup of p-n-p-n structures initiated by current pulses is described. Based on the circuit-orient model, the terminal currents and voltages of the transistors as a function of the pulsed triggering currents are characterized, and the charge storage within p-n-p-n structures is investigated. It is found that, to maintain the regeneration process, the change of charge stored in junction depletion capacitances of a p-n-p-n structure must be greater than a certain value independent of the triggering currents. Thus, the criterion is constructed in terms of the constant charge storage within a p-n-p-n structure. Applying the criterion, latchup immunity against pulsed triggering currents can be evaluated with respect to process and device parameters. Both SPICE simulations and experimental results confirm the validity of the proposed transient criterion. It is found that the large transit time of bipolar transistors and large well-substrate junction depletion capacitance lead to higher latchup immunity against pulsed triggering currents 相似文献
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Analytical Charge and Capacitance Models of Undoped Cylindrical Surrounding-Gate MOSFETs 总被引:2,自引:0,他引:2
Moldovan O. Iniguez B. Jimenez D. Roig J. 《Electron Devices, IEEE Transactions on》2007,54(1):162-165
We present an analytical and continuous charge model for cylindrical undoped surrounding-gate MOSFETs, from which analytical expressions of all total capacitances are obtained. The model is based on a unified charge control model derived from Poisson equation. The drain current, charge, and capacitances are written as continuous explicit functions of the applied voltages. The calculated capacitance characteristics show excellent agreement with three-dimensional numerical device simulations 相似文献
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Lopez-Martin A.J. Ramirez-Angulo J. Carvajal R.G. Algueta J.M. 《Electronics letters》2008,44(23):1335-1336
Current mirrors are, together with differential pairs, the most common analogue building blocks in modern analogue and mixed-signal integrated circuits. Desirable features of current mirrors include: low standby power dissipation, wide input and output current swings, low supply voltage requirements, accurate current copy, and high linearity. Conventional class A topologies are unable to achieve simultaneously low quiescent power consumption and wide current swings, since they have maximum input and output currents limited by the DC bias currents. To overcome this shortcoming, class AB current mirrors have been proposed, which feature maximum currents not limited by the quiescent currents and reduced sensitivity to process tolerances [1]. Unfortunately, the additional circuitry required to achieve class AB operation often increases supply voltage requirements. For instance, the most common approach to achieve a class AB CMOS current mirror requires stacking of two MOS gate?source voltages [2]. This additional circuitry also often increases standby power consumption and adds extra intrinsic capacitances at the internal nodes. Another common issue is that quiescent currents are often dependent on supply voltage, process variations or temperature [2]. Other approaches are based on SC dynamic biasing [3], requiring the generation of two non-overlapping clock signals and suffering from charge injection errors. 相似文献
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A capacitance model for a GaAs MESFET suitable for implementation in the circuit analysis program SPICE is presented. The model consists of nonlinear capacitances that are a function of two voltages. Such a model gives rise to ordinary nonlinear capacitances and transcapacitances. The placement of these elements in the Y matrix is shown. The empirical equations for the gate charge of a GaAs MESFET given provide an accurate SPICE model for the gate charge and capacitances of a MESFET. A comparison of measured capacitance values with the modeled values gives close enough agreement for circuit simulation purposes 相似文献
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An experiment is reported on anisotropic etching in a CF4–O2plasma produced by high-voltage gas discharge. The process is applied to SiO2and is also effected on SiC, Si, C (diamond), and As2S3. It is shown that the etch rate is mainly dependent on the oxygen percentage, plasma parameters, and the wafer temperature. It is established that etch rate is maximal at oxygen percentages of 0.8–1.5%, discharge currents of 80–140 mA, and wafer temperatures of 390–440 K. The etching is found to be uniform within 1%. 相似文献
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《IEEE transactions on circuits and systems. I, Regular papers》2005,52(8):1481-1488
We propose a novel configuration of linearized subthreshold operational transconductance amplifier (OTA) for low-power, low-voltage, and low-frequency applications. By using multiple input floating-gate (MIFG) MOS devices and implementing a cubic-distortion-term-canceling technique, the linear range of the OTA is up to 1.1 Vpp under a 1.5-V supply for less than 1% of transconductance variation, according to testing results from a circuit designed in a double-poly, 0.8-$muhbox m$ , CMOS process. The power consumption of the OTA remains below 1$muW$ for biasing currents in the range between 1–200 nA. The offset voltage due to secondary effects (contributed by parasitic capacitances, errors and mismatches of parameters, charge entrapment, etc.) is of the order of a few ten millivolts, and can be canceled by adjusting biasing voltages of input MIFG MOS transistors. 相似文献
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SiC power MOSFETs designed for blocking voltages of 10 kV and higher face the problem of high drift layer resistance that gives rise to a high internal power dissipation in the ON -state. For this reason, the ON-state current density must be severely restricted to keep the power dissipation below the package limit. We have designed, optimized, and fabricated high-voltage SiC p-channel doubly-implanted metal-oxide-semiconductor insulated gate bipolar transistors (IGBTs) on 20-kV blocking layers for use as the next generation of power switches. These IGBTs exhibit significant conductivity modulation in the drift layer, which reduces the ON-state resistance. Assuming a 300 W/cm2 power package limit, the maximum currents of the experimental IGBTs are 1.2x and 2.1x higher than the theoretical maximum current of a 20-kV MOSFET at room temperature and 177 degC, respectively. 相似文献