Fluxless Bonding of Large Silicon Chips to Ceramic Packages Using Electroplated Eutectic Au/Sn/Au Structures

A fluxless process of bonding large silicon chips to ceramic packages has been developed using a Au-Sn eutectic solder. The solder was initially electroplated in the form of a Au/Sn/Au multilayer structure on a ceramic package and reflowed at 430°C for 10 min to achieve a uniform eutectic 80Au-20Sn composition. A 9 mm × 9 mm silicon chip deposited with Cr/Au dual layers was then bonded to the ceramic package at 320°C for 3 min. The reflow and bonding processes were performed in a 50-mTorr vacuum to suppress oxidation. Therefore, no flux was used. Even without any flux, high-quality joints were produced. Microstructure and composition of the joints were studied using scanning electron microscopy with energy-dispersive x-ray spectro- scopy. Scanning acoustic microscopy was used to verify the joint quality over the entire bonding area. To employ the x-ray diffraction method, samples were made by reflowing the Au/Sn/Au structure plated on a package. This was followed by a bonding process, without a Si chip, so that x-rays could scan the solder surface. Joints exhibited a typical eutectic structure and consisted of (Au,Ni)Sn and (Au,Ni)₅Sn phases. This novel fluxless bonding method can be applied to packaging of a variety of devices on ceramic packages. Its fluxless nature is particularly valuable for packaging devices that cannot be exposed to flux such as sensors, optical devices, medical devices, and laser diodes.     

60 GHz broadband 0=1-level RF-via interconnect for RF-MEMS packaging

The RF-via interconnect structure from the 0- to the 1-level package for coplanar RF-MEMS devices packaging is evaluated. The 0/1-level interconnect structure was designed and optimised using the electromagnetic simulation tool. The structure was then successfully fabricated and characterised up to 67 GHz. The measured and simulated results show good agreement, demonstrating DC-to-60 GHz broadband interconnect performance through the two levels package with return loss below 15 dB and insertion loss within 0.6 dB.     

共晶焊料焊接的孔隙率研究

大功率或高功率密度的高可靠集成电路等通常采用合金焊料焊接芯片,以降低封装热阻和提高芯片焊接的可靠性。合金焊料焊接方式主要有真空烧结、保护气氛下静压烧结、共晶摩擦焊等。不同焊接工艺有其不同的适应性和焊接可靠性。文章以高可靠封装常用金基焊料的共晶焊接为例,探讨在相同封装结构、不同共晶焊接工艺下焊接层孔隙率,以及相同工艺设备、工艺条件下随芯片尺寸增大孔隙率的变化趋势。研究结果表明:金-硅共晶摩擦焊工艺的孔隙率低于金-锡真空烧结工艺和金-锡保护气氛静压烧结;同一焊接工艺,随着芯片尺寸变大,其孔隙率变化不显著,但单个空洞的尺寸有明显增大趋势。     

Wafer-level hermetic MEMS packaging by anodic bonding and its reliability issues

This paper reviews wafer-level hermetic packaging technology using anodic bonding from several reliability points of view. First, reliability risk factors of high temperature, high voltage and electrochemical O₂ generation during anodic bonding are discussed. Next, electrical interconnections through a hermetic package, i.e. electrical feedthrough, is discussed. The reliability of both hermetic sealing and electrical feedthrough must be simultaneously satisfied. In the last part of this paper, a new wafer-level MEMS packaging material, anodically-bondable low temperature cofired ceramic (LTCC) wafer, is introduced, and its reliability data on hermetic sealing, electrical interconnection and flip-chip mounting on a printed circuit board (PCB) are described.     

复合型微通道热沉设计与制作技术研究

从大功率半导体激光器可靠性封装和应用考虑,利用商用有限元软件Abaqus与CFdesign对微通道热沉材料、结构进行优化设计,结合相应的制造工艺流程制备实用化复合型微通道热沉。微通道热沉尺寸为27 mm×10.8 mm×1.5 mm,并利用大功率半导体激光阵列器件对所制备热沉进行散热能力、封装产生的"微笑效应"进行了测试,复合微通道热沉热阻约0.3 K/W,"微笑"值远小于无氧铜微通道封装线阵列,可以控制在1μm以下。复合型微通道热沉能满足半导体激光阵列器件高功率集成输出的散热需求与硬焊料封装的可靠性要求。     

MBE生长的跨导为186mS/mm的AlGaN/GaN HEMT

用分子束外延 ( MBE)技术研制出了 Al Ga N/Ga N高电子迁移率晶体管 ( HEMT)材料 ,其室温迁移率为 10 35cm2 /V· s、二维电子气浓度为 1.0× 10 13 cm - 2 ;77K迁移率为 2 6 53cm2 /V· s、二维电子气浓度为 9.6× 10 12 cm- 2 。用此材料研制了栅长为 1μm、栅宽为 80μm、源 -漏间距为 4μm的 Al Ga N/Ga N HEMT,其室温最大非本征跨导为 186 m S/mm、最大漏极饱和电流密度为 92 5m A/mm、特征频率为 18.8GH z。另外 ,还研制了具有 2 0个栅指 (总栅宽为 2 0× 80μm =1.6 mm )的大尺寸器件 ,该器件的最大漏极饱和电流为 1.33A。     

A 4K-bit static I2L memory

A 4096-bit ECL random-access memory using high-density I²L memory cell has been developed. Novel ECL circuit techniques and I²L flip-flop memory cells are introduced for realizing high-speed performance, low-power operation, and small chip size. It operates typically under 20-ns access time and 300 mW of power dissipation, realizing 1.46 pJ/bit of access time and power-per-bit product, a figure of merit of memory devices. The memory cell and chip size of 1122 µm²(33 µm × 34 µm) and 9.9 mm²(3 mm × 3.3 mm), respectively, are achieved with V-groove isolated bipolar process technology. The memory is organized into 4096 words × 1 bit, and is packaged into 18-pin DIP and also 18-pad leadless chip carrier package. Development results have shown that the n-p-n-coupled superintegrated I²L flip-flop memory cell is very promising for high-speed and low-power static RAM's above 4K-bit/chip area.     

AuSn合金在电子封装中的应用及研究进展

AuSn合金焊料因其具有优良的抗腐蚀、抗疲劳特性和高强度、高可靠性等优点而在气密性封装、射频和微波封装、发光二极管(LED)、倒装芯片(Flip-chip)、激光二极管(LD)、芯片尺寸封装(CSP)等方面得到广泛的应用。从电子封装无铅化和合金焊料的可靠性等方面,对AuSn合金焊料的物相结构和材料性能进行了讨论,并对AuSn合金焊料在电子封装中的应用及其研究进展进行了总结和展望。     

单片行波功率放大器

报道了一个单片行波功率放大器的研究结果。单级放大器电路采用6个栅宽为420μn的GaAsMESFET作为有源器件，通过采用栅串联电容和漏线阻抗渐变技术，在（1-13）GHz频率范围内线性增益为7．5±0．5dB，输出功率大于0．5W，功率附加效率为16％，输入输出驻波比在1．2—2，1之间。采用离子注入、背面通孔等先进工艺制作在厚度为0．1mm的GaAs基片上，芯片面积为3．7mm×1．85mm。将两个这样的芯片级联得到13±1dB的线性增益。     

An approach of numerical multi-objective optimization in stacked packaging

The main aim for the development of small electronic packages is supported by an ongoing development of portable communication devices. Thin silicon dies are believed to improve the device performance as well as its reliability. Additionally, novel packaging techniques such as stacked packaging reduce packaging cost and size, and improve the functionality and reliability. In the case of the stacked packages, wafers are stacked to form a 3D multi-chip package. On the other hand, the electronic market requires novel and efficient numerical designing tools to deal properly with the optimization. The goal of the current work was to design a reliable numerical model of the stacked package and afterwards perform numerical multi-objective optimization in reference to a number of variables, which influence the stacked package reliability.     

MEMS中的封装技术研究

MEMS中的封装工艺与半导体工艺中的封装具有一定的相似性 ,因此 ,早期MEMS的封装大多借用半导体中现成的工艺。本文首先介绍了封装的主要形式 ,然后着重阐述了晶圆级封装与芯片级封装[1] 。最后给出了一些商业化的实例     

Comparison of power cycling reliability of flexible PCB interconnect smaller/thinner and larger/thicker power devices with topside Sn-3.5Ag solder joints

The power cycling reliability of flexible printed circuit board (PCB) interconnect smaller/thinner (ST) 9.5 mm × 5.5 mm × 0.07 mm and larger/thicker (LT) 13.5 mm × 13.5 mm × 0.5 mm single Si diode samples have been studied. With the assumption of creep strain accumulation-induced fatigue cracking as the failure mechanism of the Sn-3.5Ag solder joints, finite element (FE) simulations predicted a higher power cycling reliability of soldering the flexible PCB on a ST Si diode than on a LT Si diode under similar power cycling conditions. Then the power cycling test results of 10 samples for each type are reported and discussed. The samples were constructed with commercially available ST Si diodes with 3.2/0.5/0.3 μm thick AlSiCu/NiP/Pd topside metallization and LT Si diodes with 5/0.1/1/1 μm thick Al/Ti/Ni/Ag topside metallization. In contradiction with the FE prediction, most ST Si diode samples were less reliable than those LT Si diode samples. This can be attributed to the fact that the failure of the ST diode samples was associated with the weak bonding and hence the shear-induced local delamination of the topside solder joints from the AlSiCu metallization, while the failure of the LT diode samples was mainly caused by the creep strain accumulation-induced fatigue cracking within the solder joints. Such results can be used to not only provide better understanding of the different failure mechanisms, but also demonstrate the importance of employing an appropriate topside metallization on the power devices.     

Active fiber-solder-ferrule alignment method for high-performance opto-electronic device packaging

In optical communication systems, the transceivers, including both transmitters and receivers, are the key components of system quality and bandwidth. Fiber-solder-ferrule (FSF) assembly has been widely adopted in packaging high performance transceivers such as dual-in-line package and butterfly package. The flexibility and size of the fiber and ferrule, traditional FSF packaging process is done manually and the average accuracy of the fiber position is around 80 /spl mu/m. In this case, approximately 1 out of 5 FSF assemblies will have an accuracy of less than 20 /spl mu/m, which past research shows is sufficient to maintain 90% coupling efficiency of the optoelectronic devices. This study proposes a novel method for automating the fiber-solder-ferrule packaging process based on thorough system analysis. Finally, a packaging system is developed to improve the accuracy of the fiber position to up to 20 /spl mu/m.     

长期贮存对气密性封装的影响研究

密封微电子器件在对可靠性要求较高领域占有绝对的地位,为了研究长期室内自然贮存对密封微电子封装性能的影响,对贮存在北京某研究所库房的多种气密性封装微电子器件进行试验分析。运用破坏性物理分析(DPA)方法检验样品的密封性、内部形貌、键合强度和芯片粘贴强度等,总结出长期贮存对气密性封装器件封装性能影响的结论;并根据密封性测试结果对器件分组,分别得到密封合格与不合格产品长期贮存后封装性能的实测数据,对密封性能对元器件贮存可靠性的影响进行研究,为元器件的筛选和贮存提供借鉴。     

一种并行多路数字光模块的设计与实现北大核心CSCD

并行多路数字光模块在短距离光通信中有广泛应用,并行多路数字光模块的电芯片、光芯片大都采用裸芯片,针对非气密封装会使裸芯片暴露在空气中导致氧化、可靠性不高的问题,本文提出了一种全气密封并行多路数字光模块的设计方法,采用LTCC基板四周设置焊环及管壳设计环框的新型结构,实现了数字光模块基板与管壳的直接焊接,从而实现了并行多路数字光模块的全气密性设计,解决了数字光模块非气密封设计难题。以12路收发一体数字光模块为例,本文不仅介绍了并行多路数字光模块的设计原理、并行多路光路耦合的设计方法,而且给出了全气密封并行多路数字光模块的完整结构和实现方法,试验表明,气密性(最大漏率)为5×10~(-9)P·m~3·s~(-1)。本文提出的设计结构对并行多路数字光模块的全气密性设计具有重要的参考价值。     

Cantilever RF-MEMS for monolithic integration with phased array antennas on a PCB

This article presents the development and operation of a novel electrostatic metal-to-metal contact cantilever radio-frequency microelectromechanical system (RF-MEMS) switch for monolithic integration with microstrip phased array antennas (PAAs) on a printed circuit board. The switch is fabricated using simple photolithography techniques on a Rogers 4003c substrate, with a footprint of 200 µm × 100 µm, based on a 1 µm-thick copper cantilever. An alternative wet-etching technique for effectively releasing the cantilever is described. Electrostatic and electromagnetic measurements show that the RF-MEMS presents an actuation voltage of 90 V for metal-to-metal contact, an isolation of ?8.7 dB, insertion loss of ?2.5 dB and a return loss of ?15 dB on a 50 Ω microstrip line at 12.5 GHz. For proof-of-concept, a beam-steering 2 × 2 microstrip PAA, based on two 1-bit phase shifters suitable for the monolithic integration of the RF-MEMS, has been designed and measured at 12.5 GHz. Measurements show that the beam-steering system presents effective radiation characteristics with scanning capabilities from broadside towards 29° in the H-plane.     

封装腔体内氢气含量控制

目前,对密封腔体内的水汽、二氧化碳、氧气含量的研究比较多,内部水汽含量控制在≤5 000 ppm、氧气控制在≤2 000 ppm、二氧化碳控制在≤4 000 ppm、氦气控制在≤1 000 ppm的密封工艺技术已解决[9],氢气含量控制的研究则未见报道。对于一些气密性要求高的封装应用领域,还需要控制氢气含量,如MEMS、GaAs电路等。分析了平行缝焊、Au80Sn20合金封帽的导电胶、合金烧结的器件的内部氢气含量,并分析了125℃168 h和125℃1 000 h贮存前后氢气含量的变化情况;在试验的基础上,提出了氢气的主要来源和针对性的工艺措施,并取得了期望的结果：密封器件经过125℃、1 000 h贮存后的氢气含量也能控制在≤4 000 ppm。     

电镀技术在凸点制备工艺中的应用

简要回顾了微电子封装的发展历程;描述了FC、BGA、CSP以及WLP的基本概念;归纳了凸点类型以及各种凸点的不同用途;着重介绍了电镀金、金锡、锡铅、锡银和化学镀镍凸点的工艺过程,最后简单介绍了制备凸点的电镀设备。     

Packaging of MMICs in multilayer LCP substrates

A 13-25-GHz GaAs bare die low noise amplifier is embedded inside a multilayer liquid crystal polymer (LCP) package made from seven layers of thin-film LCP. This new packaging topology has inherently unique properties that could make it an attractive alternative in some instances to traditional metal and ceramic hermetic packages. LCP is a near-hermetic material and its lamination process is at a relatively low temperature (285/spl deg/C versus >800/spl deg/C for ceramics). The active device is enclosed in a package consisting of several laminated C0/sub 2/ laser machined LCP superstrate layers. Measurements demonstrate that the LCP package and the 285/spl deg/C packaging process have minimal effects on the monolithic microwave integrated circuit radio frequency (RF) performance. These findings show that both active and passive devices can be integrated together in a homogeneous laminated multilayer LCP package. This active/passive compatibility demonstrates a unique capability of LCP to form compact, vertically integrated (3-D) RF system-on-a-package modules.     

金属陶瓷贴片封装的S波段六位数控移相器

介绍了一款自主设计采用0.25μm GaAs PHMET开关工艺制作的的S波段六位数控移相器芯片和金属陶瓷表贴管壳内的设计方法和研制结果.该移相器在工作频带2.8～3.6 GHz内64个移相态的移相精度RMS＜1.0°、插入损耗IL＜5 dB、输入输出驻波比VSWR＜1.5、幅度均衡△IL＜0.3 dB、1分贝压缩输入...