A 2.4-GHz Resistive Feedback LNA in 0.13-$mu$m CMOS

A $g_{m}$-boosted resistive feedback low-noise amplifier (LNA) using a series inductor matching network and its application to a 2.4 GHz LNA is presented. While keeping the advantage of easy and reliable input matching of a resistive feedback topology, it takes an extra advantage of $g_{m}$ -boosting as in inductively degenerated topology. The gain of the LNA increases by the $Q$ -factor of the series RLC input network, and its noise figure (NF) is reduced by a similar factor. By exploiting the $g_{m}$-boosting property, the proposed fully integrated LNA achieves a noise figure of 2.0 dB, S21 of 24 dB, and IIP3 of ${- 11}~ hbox{dBm}$ while consuming 2.6 mW from a 1.2 V supply, and occupies 0.6 ${hbox {mm}}^{2}$ in 0.13-$mu{hbox {m}}$ CMOS, which provides the best figure of merit. This paper also includes an LNA of the same topology with an external input matching network which has an NF of 1.2 dB.      

3-GHz Silicon Photodiodes Integrated in a 0.18-$mu$m CMOS Technology

A new PIN photodiode (PD) structure with deep n-well (DNW) fabricated in an epitaxial substrate complementary metal–oxide–semiconductor (epi-CMOS) process is presented. The DNW buried inside the epitaxial layer intensifies the electric field deep inside the epi-layer significantly, and helps the electrons generated inside the epi-layer to drift faster to the cathode. Therefore, this new structure reduces the carrier transit time and enhances the PD bandwidth. A PD with an area of $70times 70 mu$m $^{2}$ fabricated in a 0.18- $mu$m epi-CMOS achieves 3-dB bandwidth of 3.1 GHz in the small signal and 2.6 GHz in the large signal, both with a 15-V bias voltage and 850-nm optical illumination. The responsivity is measured 0.14 A/W, corresponding to a quantum efficiency of 20%, at low bias. The responsivity increases to 0.4 A/W or 58% quantum efficiency at 16.2-V bias in the avalanche mode.      

A 51 to 65 GHz Low-Power Bulk-Driven Mixer Using 0.13 $mu$m CMOS Technology

A low-voltage and low-power down-conversion bulk-driven mixer using standard 0.13 $mu$ m CMOS technology is presented in this letter. To work on a low supply voltage and low power consumption applications while maintaining reasonable performance, the bulk-driven technique is selected in this V-band mixer design. The mixer has a conversion gain of $0 pm 1.5$ dB from 51 to 65 GHz with low supply voltage of 1 V and low power consumption of 3 mW. To our knowledge, the MMIC is the highest frequency CMOS bulk-driven mixer to date with good conversion gain and low power consumption among the recently published active mixers around 60 GHz.      

A K-Band High-Gain Down-Conversion Mixer in 0.18 $mu$m CMOS Technology

A high gain CMOS down conversion mixer with a gain enhancement technique is presented. This technique includes negative resistance generation, parasitic capacitance cancellation and current-injection. These are implemented with an additional circuitry. This mixer has a conversion gain of 9.12 dB, input 1 dB compression point of -11 dBm at 24 GHz, while consuming 16.2 mW from 1.8 V supply. Between 22 and 26 GHz, the LO-to-RF and RF-to-LO isolations are better than 35 dB and 26 dB, respectively.     

A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-$mu$m CMOS

In this paper, a 6-bit 1-GS/s 49 mW two-channel two-step analog-to-digital converter (ADC) without calibration is implemented in 0.13- $mu{hbox {m}}$ CMOS process. The proposed multiplying digital-to-analog converter (MDAC) processes the analog signal with two clock periods for one conversion: half for sampling, half for Coarse ADC (CADC) resolving, and one for residue amplification. A self-timing technique is used to prevent disturbance at the beginning of the residue amplification. The reduction of the MDAC output swing by enhancing the accuracy of CADC increases the output devices' over-drive voltage and decreases output loading. The proposed design methods allow closed-loop MDAC to operate at high speed while maintaining low power consumption. The measured SFDR, SNR, and SNDR are 40.7 dB, 33.8 dB, and 33.7 dB, respectively, at the Nyquist rate input. The ADC power dissipation is 49 mW and corresponds to a figure-of-merit (FoM) of 1.24 pJ/conv.-step. The active area occupies 0.16$~{hbox {mm}}^{2}$.      

A 24 GHz Amplitude Monopulse Comparator in 0.13 $mu$m CMOS

This letter presents the design and implementation of a wideband 24 GHz amplitude monopulse comparator in 0.13 $mu$m CMOS technology. The circuit results in 9.6 dB gain in the sum channel at 24 GHz with a 3-dB bandwidth of 23.0–25.2 GHz, and a sum/difference ratio of $> 25$ dB at 20–26 GHz. The measured input P1 dB is ${-}14.4$ dBm at 24 GHz. The chip is only 0.55$,times,$ 0.50 mm$^{2}$ (without pads) and consumes 44 mA from a 1.5 V supply, including the input active baluns and the differential to single-ended output stages (28 mA without the input and output stages). To our knowledge, this is the first demonstration of a high performance mm-wave CMOS monopulse comparator RFIC.      

All-Silicon 1.55-$mu$m High-Resolution Photon Counting and Timing

We investigate the performances at 1.55- $mu{hbox{m}}$ wavelength of silicon single photon avalanche diodes (SPADs), demonstrating their suitable applicability in laser characterizations and ultra-sensitive autocorrelation measurements. We investigate the photon detection efficiency and the two-photon absorption process of both lightly doped thick SPADs and heavily doped thin SPADs. Finally, we report the accurate pulse-shape characterization of a 1.55- $mu{hbox{m}}$ pulsed laser by means of a thin silicon SPAD that exploits the best intrinsic time resolution of 25 ps with wide dynamic range and low measurement time.      

Ultra-Low-Voltage 20-GHz Frequency Dividers Using Transformer Feedback in 0.18-$mu$ m CMOS Process

This paper presents the design and analysis of ultra- low-voltage (ULV) high-frequency dividers using transformer feedback. Specifically, a differential-input differential-output injection-locked (IL) divider topology with transformer feedback and a wideband transformer-coupled (TC) divider with quadrature outputs are demonstrated, both of which can operate well at supply voltages as low as the device's threshold voltages. Fabricated in a standard 0.18-mum CMOS process, the ULV-IL divider measures an input frequency range from 16.1 GHz to 20 GHz while consuming a total power from 2.75 mW to 4.35 mW at 0.5 V supply, and the TC-divider measures an input frequency range of 27.8% from 15.1 GHz to 20 GHz with IQ sideband rejection of - 31 dBc while consuming power from 11.4 mW to 13.6 mW at 0.6 V supply.     

Bipolar Cascade Superluminescent Diodes at the 1.04-$mu$m Wavelength Regime

In this study, we investigate the performance of GaAs-based bipolar cascade superluminescent diodes with different cavity lengths. The device operates around the important bio-optical therapeutic 1.04- $muhbox{m}$ wavelength window. The introduction of tunnel junctions tends to minimize the nonuniform carrier distribution between distinct multiple quantum-wells (QWs), which is a problem in conventional SLDs, whose electroluminescent spectra are governed by the center wavelength of QWs near the p-side. Our devices exhibit nice electrical characteristics of low leakage current and overcome the limitation of nonuniform carrier distribution, thereby presenting a promising prospect for the near infrared white-light sources.      

A Fully Integrated 0.13- $mu$m CMOS 40-Gb/s Serial Link Transceiver

A fully integrated 40-Gb/s transceiver fabricated in a 0.13-$mu$m CMOS technology is presented. The receiver operates at a 20-GHz clock performing half-rate clock and data recovery. Despite the low ${rm f}_{rm T}$ of 70 GHz, the input sampler achieves 10-mV sensitivity using pulsed latches and inductive-peaking techniques. In order to minimize the feedback latency in the bang-bang controlled CDR loop, the proportional control is directly applied to the VCO, bypassing the charge pump and the loop filter. In addition, the phase detection logic operates at 20 GHz, eliminating the need for the deserializers for the early/late timing signals. The four clock phases for the half-rate CDR are generated by a quadrature LC-VCO with microstrip resonators. A linear equalizer that tunes the resistive loading of an inductively-peaked CML buffer can improve the eye opening by 20% while operating at 39 Gb/s. The prototype transceiver occupies 3.4$, times ,$2.9 mm$^{2}$ with power dissipation of 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 2$^{15}-1$ PRBS data is 1.85 ${rm ps}_{rm rms}$ over a WB-PBGA package, an 8-mm PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable. The recovered divided-by-16 clock jitter is 1.77 ${rm ps}_{rm rms}$ and the measured BER of the transceiver is less than $10^{- 14}$ .      

High-Temperature Continuous-Wave Single-Mode Operation of 1.3-$mu$m p-Doped InAs–GaAs Quantum-Dot VCSELs

In this letter, we have demonstrated continuous-wave single-mode operation of 1.3-$mu{hbox {m}}$ InAs–GaAs quantum-dot (QD) vertical-cavity surface-emitting lasers (VCSELs) with p-type modulation-doped QD active region from 20 $^{circ}hbox{C}$ to 60 $^{circ}hbox{C}$ . The highest output power of 0.435 mW and lowest threshold current of 1.2 mA under single-mode operation are achieved. The temperature-dependent output characteristics of QD-VCSELs are investigated. Single-mode operation with a sidemode suppression ratio of 34 dB is observed at room temperature. The critical size of oxide aperture for single-mode operation is discussed.      

A Slew Controlled LVDS Output Driver Circuit in 0.18 $mu$m CMOS Technology

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50 fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation at low supply voltages using a conventional 0.18 $muhbox{m}$ CMOS technology feasible. The output driver circuit consumes 4.5 mA while driving an external 100 $Omega $ resistor with an output voltage swing of $V_{OD} = $400 mV, achieving a normalized power dissipation of 3.42 mW/Gbps. The area of the LVDS driver circuit is 0.067 ${hbox{mm}}^{2}$ and the measured output jitter is $sigma _{rms} = $4.5 ps. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5 Gbps where the speed will be limited by the load $RC$ time constant.      

A Wideband PLL-Based G/FSK Transmitter in 0.18 $mu$m CMOS

A wideband phase-locked loop (PLL)-based G/FSK transmitter (TX) architecture is presented in this paper. In the proposed TX, the G/FSK data is applied outside the loop; hence, the data rate is not constrained by the PLL bandwidth. In addition, the PLL remains locked all the time, preventing the carrier frequency from drifting. In this architecture, the G/FSK modulation signal is generated from a proposed Sigma-Delta modulated Phase Rotator $(SigmaDelta{hbox{-PR}})$. By properly combining the multi-phase signals from the PLL output, the $SigmaDelta{hbox{-PR}}$ effectively operates as a fractional frequency divider, which can synthesize modulation signals with fine-resolution frequencies. The proposed $SigmaDelta{hbox{-PR}}$ adopts the input signal as the phase transition trigger, facilitating a glitch-free operation. The impact of the $SigmaDelta{hbox{-PR}}$ on the TX output noise is also analyzed in this paper. The proposed TX with the $SigmaDelta{hbox{-PR}}$ is digitally programmable and can generate various G/FSK signals for different applications. Fabricated in a 0.18 $muhbox{m}$ CMOS technology, the proposed TX draws 6.3 mA from a 1.4 V supply, and delivers an output power of $-$11 dBm. With a maximum data rate of 6 Mb/s, the TX achieves an energy efficiency of 1.5 nJ/bit.      

Continuous-Wave Electrically Pumped 1.55-$mu$m Edge-Emitting Platelet Ridge Laser Diodes on Silicon

We report the successful integration on silicon of small footprint, low-threshold electrically pumped edge-emitting lasers by a new approach incorporating microcleaving technology to produce 6-$mu$ m-thick platelet lasers with cleaved facets, microscale pick. and place assembly to position them on the substrate, and diaphragm pressure solder bonding to attach/connect them permanently in place. InP-based ridge-waveguide platelet lasers integrated on silicon lase at 1550-nm continuous-wave to 55 $^{circ}$C (pulsed to 80 $^{circ}$C) with output powers as high as 26.8 mW, external differential quantum efficiencies as high as 81%, and threshold currents as low as 18 mA.      

Short-Injector Quantum Cascade Laser Emitting at 8-$mu$m Wavelength With High Slope Efficiency

This letter presents experimental results of a three-alloy-based short-injector quantum cascade laser (QCL). The investigated 4-mm-long device shows a pulsed threshold current density of 1.24 kA/cm² , a slope efficiency of 1.4 W/A, a characteristic temperature above 250 K, and a peak average output power above 726 mW at room temperature. A good high-temperature performance is attributed to the diagonal transition design and better depopulation of the lower laser levels at higher temperatures. The laser emission wavelength at room temperature is 8 mum, resulting in a low voltage defect of 71 meV per period for the QCL structure.     

A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-$mu$m CMOS Technology

A 10-Gb/s current mode logic (CML) input/output (I/O) circuit for backplane interconnect is fabricated in 0.18-mu m 1P6M CMOS process. Comparing with conventional I/O circuit, this work consists of input equalizer, limiting amplifier with active-load inductive peaking, duty cycle correction and CML output buffer. To enhance circuit bandwidth for 10-GB/s operation, several techniques include active load inductive peaking and active feedback with current buffer in Cherry-Hooper topology. With these techniques, it reduces 30%-65% of the chip area comparing with on-chip inductor peaking method. This design also passes the interoperability test with switch fabric successfully. It provides 600- mV_pp differential voltage swing in driving 50-Omega output loads, 40-dB input dynamic range, 40-dB voltage gain, and 8-mV input sensitivity. The total power consumption is only 85 mW in 1.8-V supply and the chip feature die size is 700 mum times 400 mum.     

The Performance of Acoustic-Optical $Q$-switched Mode-Locking 1.34 $mu$m Nd:GdVO$_{4}$ Laser

A diode-end-pumped $Q$ -switched mode-locking $hbox{Nd:GdVO}_{4}$ laser operating at 1.34 $mu{hbox {m}}$ with an acousto-optical (AO) Q-switch in a compact V-type cavity was realized in our experiment for the first time. When the AO Q-switch repetition rate was 10 kHz, the maximum average output power of 750 mW and the pulse energy of 75 $muhbox{J}$ were obtained at the maximum incident pump power of 9 W. The mode-locking modulation depth of about 100% was obtained at certain pump power over the threshold. The mode-locked pulse inside in the $Q$-switched pulse had a repetition rate of 341 MHz, and its average pulsewidth was estimated to be about 350 ps. A developed rate equation model for the $Q$ -switched and mode-locked lasers with an AO Q-switch were proposed by using the hyperbolic secant functional methods. The results of numerical calculations of the rate equations were in good agreement with the experimental results.      

A 5.6 GHz Low Power Balanced VCO in 0.18 $mu$m CMOS

A 5.6 GHz balanced voltage-controlled oscillator (VCO) is designed and implemented in a 0.18 mum CMOS 1P6M process. It consists of two single-ended complementary Colpitts LC-tank VCOs coupled by two pairs of varactors. At the supply voltage of 1.2 V, the output phase noise of the VCO is -119.13 dBc/Hz at 1MHz offset frequency from the carrier frequency of 5.6 GHz, and the figure of merit is -190.29 dBc/Hz. Total VCO core power consumption is 2.4 mW. Tuning range is about 600 MHz, from 5.36 to 5.96 GHz, while the control voltage was tuned from 0 to 1.2 V.     

A 0.6 V Low-Power Wide-Range Delay-Locked Loop in 0.18 $mu$m CMOS

In this letter, a delay-locked loop (DLL) suitable for low-power and low-voltage operations is presented. To overcome the performance limitations, such as a restricted locking range and elevated output jitters, a novel voltage-controlled delay cell and a phase/frequency detector with a start controller are employed in the proposed DLL. Using a standard 0.18 mum CMOS process, the fabricated circuit exhibits a locking range from 85 to 550 MHz. The measured peak-to-peak and rms jitters at 550 MHz are 25.6 and 3.8 ps, respectively. Operated at a supply voltage of 0.6 V, the power consumption of the DLL circuit varies from 2.4 to 4.2 mW within the entire locking range.     

A 10–40 GHz Broadband Subharmonic Monolithic Mixer in 0.18 $mu$ m CMOS Technology

A 10–40 GHz broadband subharmonic monolithic passive mixer using the standard 0.18 $mu$ m CMOS process is demonstrated. The proposed mixer is composed of a two-stage Wilkinson power combiner, a short stub and a low-pass filter. Likewise, the mixer utilizes a pair of anti-parallel gate-drain-connected diodes to achieve subharmonic mixing mechanism. The two-stage Wilkinson power combiner is used to excite a radio frequency (RF) and local oscillation (LO) signals into diodes and to perform broadband operation. The low-pass filter supports an IF frequency range from dc to 2.5 GHz. This proposed configuration leads to a die size of less than 1.1$,times,$ 0.67 mm$^{2}$ . The measured results demonstrate a conversion loss of 15.6–17.6 dB, an LO-to-RF isolation better than 12 dB, a high 2LO-to-RF isolation of 51–59 dB over 10–40 GHz RF bandwidth, and a 1 dB compression power of 8 dBm.