CMOS低相位噪声压控振荡器的设计

基于65 nm CMOS标准工艺库,设计了一个工作频率在10 GHz的具有低相位噪声的CMOS电感电容型压控振荡器。该压控振荡器选用CMOS互补交叉耦合型电路结构,采用威尔逊型尾电流源负反馈技术来降低相位噪声。仿真结果表明,此压控振荡器工作频率覆盖范围为9.9~11.2 GHz,调谐范围为12.3%,中心频率为10.5 GHz,在频率偏移中心频率1 MHz下的相位噪声为-113.3 dBc/Hz,核心功耗为2.25 mW。     

3GHz低功耗低相位噪声的带自偏置电流源的LC压控振荡器

利用0.18μm CMOS工艺实现了一个全集成的工作于3GHz的低功耗、低相位噪声的压控振荡器,且带有自偏置电流源.通过对改进的电流源进行优化,在噪声与功耗之间达到了折中.该压控振荡器可工作于2.83至3.25GHz频段内,调谐范围达到13.8%.当工作于3.22GHz时,测得的相位噪声在1MHz频偏处为-111dBc/Hz.在1.8V电源电压下,核心模块消耗电流小于2mA.表明该电路适合5GHz的无线局域网接收机以及3.4至3.6GHz的全球微波互联接入(WiMAX)应用.     

3GHz低功耗低相位噪声的带自偏置电流源的LC压控振荡器

利用0.18μm CMOS 工艺实现了一个全集成的工作于3GHz的低功耗、低相位噪声的压控振荡器,且带有自偏置电流源. 通过对改进的电流源进行优化,在噪声与功耗之间达到了折中. 该压控振荡器可工作于2.83至.25GHz频段内,调谐范围达到13.8%. 当工作于3.22GHz时,测得的相位噪声在1MHz频偏处为-111dBc/Hz. 在1.8V电源电压下,核心模块消耗电流小于2mA. 表明该电路适合5GHz的无线局域网接收机以及3.4至3.6GHz的全球微波互联接入（WiMAX）应用.     

卫星电视天线射频电路中LC压控振荡器设计

设计了一款应用于卫星电视天线电路中低功耗、低相噪的宽带单片集成压控振荡器。该振荡器利用PMOS尾电流源和MIM电容阵列结构。在保证调谐范围的前提下,有效地降低了相位噪声。使得该压控振荡器实现了3.384～4.022 GHz频段的覆盖,在中心频率为3.7 GHz时,100 Hz和1 MHz频偏处的相位噪声分别为-90.4 dBc/Hz和-119.1 dBc/Hz,工作电压下为1.8 V,功耗仅为2.5 mW。     

射频卫星电视天线电路中LC压控振荡器设计

本文设计了一款应用于卫星电视天线电路中低功耗、低相噪的宽带单片集成压控振荡器。该振荡器利用PMOS尾电流源和MIM电容阵列结构。在保证调谐范围的前提下,有效的降低了相位噪声。使得该压控振荡器实现了3.384GHz~4.022GHz频段的覆盖,在中心频率为3.7GHz时,100Hz和1MHz频偏处的相位噪声分别为-90.4dBc/Hz和-119.1dBc/Hz,工作电压下为1.8V,功耗仅为2.5mW。     

超低电压正交压控振荡器设计

提出一种新的低压正交压控振荡器(QVCO)结构,该结构由两个完全相同的低压压控振荡器经过背栅耦合方式实现.背栅耦合方式使压控振荡器实现正交的输出时钟并且降低了功耗和输出相位噪声.该设计中的QVCO电路采用中芯国际0.13μm 1P8M标准CMOS工艺,可以工作在0.35V的电源电压下,总的功耗为1.75mW,输出时钟频率为5.34GHz,偏离主频1MHz处的相位噪声为-110.5dBc/Hz,对应该相位噪声的FOM(FigureOf-Merit)为-182.62dBc/Hz,频率调谐范围为4.92~5.34GHz.该QVCO可以在更低的电源电压下实现低的相位噪声,且拥有较高的FOM值.     

一种提供5位频带切换控制的5GHz压控振荡器

设计了一种提供5位频带切换控制的5GHz电容电感压控振荡器,采用NMOS-PMOS交叉耦合结构,并且为消除电流源的闪烁噪声而应用电阻偏置调节工作电流.电路采用TSMC RF0.18μm CMOS工艺进行仿真,仿真结果显示,在1.8V电源电压下,在偏离中心频率1MHz处的相位噪声为-120.8dBc/Hz,调谐范围为24.6%,功耗仅为2.3mW.     

基于GaAs工艺的36GHz压控振荡器

利用法国OMMIC公司的0.2μm GaAs PHEMT工艺,设计实现了一个36GHz压控振荡器电路.该电路采用完全差分的调谐振荡器结构,通过引进容性源极耦合差动电流放大器和调谐负载电路,提高了电路的性能.测试表明:该压控振荡器中心频率为36GHz,调谐范围约为800MHz,在偏离中心频率10MHz处的单边带相位噪声为-98.83dBc/Hz.芯片面积为0.5mm×1mm,采用-5V单电源供电,核心单元功耗约为200mW.     

基于GaAs工艺的36GHz压控振荡器

利用法国OMMIC公司的0.2μm GaAs PHEMT工艺,设计实现了一个36GHz压控振荡器电路.该电路采用完全差分的调谐振荡器结构,通过引进容性源极耦合差动电流放大器和调谐负载电路,提高了电路的性能.测试表明:该压控振荡器中心频率为36GHz,调谐范围约为800MHz,在偏离中心频率10MHz处的单边带相位噪声为-98.83dBc/Hz.芯片面积为0.5mm×1mm,采用-5V单电源供电,核心单元功耗约为200mW.     

低相位噪声压控振荡器设计

分析了LC压控振荡器(VCO)相位噪声,通过改进电路结构,采用PMOS和NMOS管做负阻管,在尾电流源处加入电感电容滤波,优化电感设计,设计了一种高性能压控振荡器.采用TSMC 0.18 μm IP6M CMOS RF工艺,利用Cadence中的Spectre RF工具对电路进行仿真.在电路的偏置电流为6 mA、电源电压VDD=1.8 V时,输入控制电压为0.8～1.8 V,输出频率变化为1.29～1.51 GHz,调谐范围为12.9%,相位噪声为-134.4 dBc/Hz@1MHz,功耗仅为10.8 mW.     

Low-Phase Noise Hartley Differential CMOS Voltage Controlled Oscillator

This letter presents a novel Hartley low phase noise differential CMOS voltage-controlled oscillator (VCO). The low noise CMOS VCO has been implemented with the TSMC 0.18-mum 1P6M CMOS technology and adopts full PMOS to achieve a better phase noise performance. The VCO operates from 4.02 to 4.5GHz with 11.3% tuning range. The measured phase noise at 1-MHz offset is about -119dBc/Hz at 4.02GHz and 122dBc/Hz at 4.5GHz. The power consumption of the VCO core is 6.75mW     

2GHz低功耗差分控制的CMOS单片LC压控振荡器

设计了工作在2GHz,差分控制的单片LC压控振荡器,并利用0.18μm CMOS工艺实现.利用模拟和数字(4位二进制开关电容阵列)调频技术,压控振荡器的调频范围达到16.15%(1.8998～2.2335GHz).在2.158GHz工作频率下,在1MHz频偏处的相位噪声为-118.17dBc/Hz.应用给出的开关设计,相位噪声在不同的数字位控制下变化不超过3dB.由于利用pn结二级管作为变容管,在调频范围内,相位噪声仅改变约2dB.压控振荡器在1.8V电源电压下消耗2.1mA电流并能够在1.5V电源电压下正常工作.     

Design and Scaling of W-Band SiGe BiCMOS VCOs

This paper discusses the design of 77-106 GHz Colpitts VCOs fabricated in two generations of SiGe BiCMOS technology, with MOS and HBT varactors, and with integrated inductors. Based on a study of the optimal biasing conditions for minimum phase noise, it is shown that VCOs can be used to monitor the mm-wave noise performance of SiGe HBTs. Measurements show a 106 GHz VCO operating from 2.5 V with phase noise of -101.3 dBc/Hz at 1 MHz offset, which delivers +2.5 dBm of differential output power at 25degC, with operation verified up to 125degC. A BiCMOS VCO with a differential MOS-HBT cascode output buffer using 130 nm MOSFETs delivers +10.5 dBm of output power at 87 GHz.     

K- and Q-bands CMOS frequency sources with X-band quadrature VCO

Fully integrated 10-, 20-, and 40-GHz frequency sources are presented, which are implemented with a 0.18-/spl mu/m CMOS process. A 10-GHz quadrature voltage-controlled oscillator (QVCO) is designed to have output with a low dc level, which can be effectively followed by a frequency multiplier. The proposed multipliers generate signals of 20 and 40 GHz using the harmonics of the QVCO. To have more harmonic power, a frequency doubler with pinchoff clipping is used without any buffers or dc-level shifters. The QVCO has a low phase noise of -118.67 dBc/Hz at a 1-MHz offset frequency with a 1.8-V power supply. The transistor size effect on phase noise is investigated. The frequency doubler has a low phase noise of -111.67 dBc/Hz at a 1-MHz offset frequency is measured, which is 7 dB higher than a phase noise of the QVCO. The doubler can be tuned between 19.8-22 GHz and the output is -6.83 dBm. A fourth-order frequency multiplier, which is used to obtain 40-GHz outputs, shows a phase noise of -102.0 dBc/Hz at 1-MHz offset frequency with the output power of -18.0 dBm. A large tuning range of 39.3-43.67 GHz (10%) is observed.     

Design of wide-band CMOS VCO for multiband wireless LAN applications

In this paper, a general design methodology of low-voltage wide-band voltage-controlled oscillator (VCO) suitable for wireless LAN (WLAN) application is described. The applications of high-quality passives for the resonator are introduced: 1) a single-loop horseshoe inductor with Q > 20 between 2 and 5 GHz for good phase noise performance; and 2) accumulation MOS (AMOS) varactors with C/sub max//C/sub min/ ratio of 6 to provide wide-band tuning capability at low-voltage supply. The adverse effect of AMOS varactors due to high sensitivity is examined. Amendment using bandswitching topology is suggested, and a phase noise improvement of 7 dB is measured to prove the concept. The measured VCO operates on a 1-V supply with a wide tuning range of 58.7% between 3.0 and 5.6 GHz when tuned between /spl plusmn/0.7 V. The phase noise is -120 dBc/Hz at 3.0 GHz, and -114.5 dBc/Hz at 5.6 GHz, with the nominal power dissipation between 2 and 3 mW across the whole tuning range. The best phase noise at 1-MHz offset is -124 dBc/Hz at the frequency of 3 GHz, a supply voltage of 1.4 V, and power dissipation of 8.4 mW. When the supply is reduced to 0.83 V, the VCO dissipates less than 1 mW at 5.6 GHz. Using this design methodology, the feasibility of generating two local oscillator frequencies (2.4-GHz ISM and 5-GHz U-NII) for WLAN transceiver using a single VCO with only one monolithic inductor is demonstrated. The VCO is fabricated in a 0.13-/spl mu/m partially depleted silicon-on-insulator CMOS process.     

Fundamental low phase noise InP-based DHBT VCO operating up to 89 GHz

A fundamental low phase noise W-band VCO extended by an output buffer using InP/InGaAs DHBT technology is reported. The fully integrated differential VCO exhibits operation frequencies ranging from 83 to 89 GHz. At 87 GHz, a minimum phase noise of -102 dBc/Hz at 1 MHz offset frequency has been achieved. Within the tuning range, a single ended output power up to 5 dBm was measured, resulting in a total signal power of 8 dBm.     

Design of Sub-1 mW CMOS LC VCO based on current reused topology with Q-enhancement and body-biased technique

A CMOS LC voltage controlled oscillator (VCO) based on current reused topology with low phase noise and low power consumption is presented for IEEE 802.11a (Seller et al. A 10 GHz distributed voltage controlled oscillator for WLAN application in a VLSI 65 nm CMOS process, in: IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 3–5 June, 2007, pp. 115–118.) application. The chip1 is designed with the tail current-shaping technique to obtain the phase noise −116.1 dBc/Hz and power consumption 3.71 mW at the operating frequency 5.2 GHz under supply voltage 1.4 V. The second chip of proposed VCO can achieve power consumption Sub 1 mW and is still able to maintain good phase noise. The current reused and body-biased architecture can reduce power consumption, and better phase noise performance is obtained through raising the Q value. The measurement result of the VCO oscillation frequency range is from 5.082 GHz to 5.958 GHz with tuning range of 15.8%. The measured phase noise is −115.88 dBc/Hz at 1 MHz offset at the operation frequency of 5.815 GHz. and the dc core current consumption is 0.71 mA at a supply voltage of 1.4 V. Its figure of merit (FOM) is −191 dBc/Hz. Two circuits were taped out by TSMC 0.18 μm 1P6M process.     

A 5-GHz low-voltage and low-power CMOS LC voltage controlled oscillator for 802.11a wireless LAN applications

In this paper, a low phase noise and low power 5.15?GHz LC-tank VCO is presented and analysed. The phase noise achieved is??91,??116 and??126?dBc/Hz at 100?KHz, 1?MHz and 3?MHz offsets respectively from the carrier frequency of 5.15?GHz, with 1.8?V power supply voltage and giving a very low power consumption of about 2.5?mW by considering the proposed oscillator topology, which consumes less power than the classical oscillator using the traditional differential transconductor pair. A broad tuning range has been achieved by means of standard mode PMOS varactors. The tunability of the designed VCO covers 530?MHz, from 4.78?GHz up to 5.31?GHz. Predicted performance has been verified by analyses and simulations using ELDO-RF tool with 0.35?µm CMOS TSMC parameters.     

60GHz宽调谐范围推—推压控振荡器设计

基于65nmCMOS工艺实现了60GHz推—推压控振荡器（VCO）设计。采用互补交叉耦合去尾电流源结构以降低相位噪声。压控振荡器输出包含两级缓冲放大器,第二级缓冲放大器偏置在截止区附近以增大二次谐波的输出功率。在1.2/0.8V电源电压下,压控振荡器核心和缓冲放大器分别消耗2.43mW和2.95mW。在偏离中心频率1MHz处相位噪声为-90.7dBc/Hz。输出功率为-2.92dBm。特别的,压控振荡器的调谐范围达到9.2GHz（15.3%）,与调谐范围相关的性能指标FOMT为-182.7dBc/Hz。该压控振荡器可应用于57GHz～64GHz开放频段超高速短距离无线通信。     

A 21.5/43-GHz dual-frequency balanced Colpitts VCO in SiGe technology

A balanced Colpitts voltage-controlled oscillator (VCO) is designed and fabricated in a commercially available 0.25-/spl mu/m SiGe BiCMOS process. It has the characteristics of the push-push VCO, i.e., the VCO has simultaneously a differential output at a fundamental frequency of 21.5 GHz and a single-ended output at the second harmonic frequency of 43 GHz. A differential tuning technique is applied to reduce the phase noise. The measured phase noise at 1-MHz offset is -113 dBc/Hz at 21.5 GHz and -107 dBc/Hz at 43 GHz. The corresponding output power is about -6 and -17 dBm, respectively, with a 5% tuning range and a 130-mW dc power consumption.