High-performance VLSI architectures for turbo decoders with QPP interleaver

This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW – SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of ‘mod’ operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.     

LTE turbo 解码器设计

本文提出一种可以用于lte小基站的turbo码解码器设计, 它支持LTE标准中的188种不同长度的TURBO码解码。设计采用了最多16路的并行解码,迭代次数可设定。解码器提采用了一种改进的软输入软输出设计。设计采用了轮流计算前向状态矩阵,和后项状态矩阵。这样可以缩短基二算法的关键路径,同时分支传输概率也可以直接用于计算不再需要保存。分组数据利用列地址映射,和行数据交换完成整个码的交织计算,利用相反的过程完成解交织计算。每个时钟都可以产生交织与解交织数据,用于解码和存储运算。     

Processor-based turbo interleaver for multiple third-generation wireless standards

A software turbo interleaver running on a SIMD processor is presented for a turbo decoder supporting multiple 3G wireless standards. To hide the timing overhead of interleaver changing, the interleaver generation is split into two parts, preprocessing and incremental on-the-fly generation. Applying the proposed approach, we implemented a W-CDMA and cdma2000 interleaver that generates one interleaved address per cycle and occupies 10% area of the ROM implementation.     

Adaptive Selection of Parameters of S-Random Interleaver in Wireless Data Transmission Systems with Turbo Coding

The paper proposes an adaptive method for selecting the parameters of S-random interleaver of turbo-code codex in wireless data transmission systems under conditions of a priori uncertainty for enhancing the reliability of data transmission and reducing the computational complexity of the coding/decoding process of turbo codes. This method is based on the adaptive selection of parameters of S-random interleaver depending on values of the normalized quantity of sign reversals of a posteriori-a priori log-likelihood function ratios (LLFR) regarding the transmitted data bits of turbo-code decoder. The results of simulation modeling show that the rational parameters of S separation of data bit interleaving for S-random interleaver are obtained depending on the values of signal-to-noise ratio in channel and the normalized number of sign reversals of a posteriori-a priori LLFR of interactive turbo-code decoder. As a result, the energy gain of coding can be obtained, the complexity of its hardware and software implementation can be reduced, and reliability of data transmission can be enhanced as compared to the known results, for example, the fourth generation mobile communication system 4G LTE-Advanced.     

Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support

This paper presents a unified, radix-4 implementation of turbo decoder, covering multiple standards such as DVB, WiMAX, 3GPP-LTE and HSPA Evolution. The radix-4, parallel interleaver is the bottleneck while using the same turbo-decoding architecture for multiple standards. This paper covers the issues associated with design of radix-4 parallel interleaver to reach to flexible turbo-decoder architecture. Radix-4, parallel interleaver algorithms and their mapping on to hardware architecture is presented for multi-mode operations. The overheads associated with hardware multiplexing are found to be least significant. Other than flexibility for the turbo decoder implementation, the low silicon cost and low power aspects are also addressed by optimizing the storage scheme for branch metrics and extrinsic information. The proposed unified architecture for radix-4 turbo decoding consumes 0.65 mm² area in total in 65 nm CMOS process. With 4 SISO blocks used in parallel and 6 iterations, it can achieve a throughput up to 173.3 Mbps while consuming 570 mW power in total. It provides a good trade-off between silicon cost, power consumption and throughput with silicon efficiency of 0.005 mm²/Mbps and energy efficiency of 0.55 nJ/b/iter.     

Double-Binary Circular Turbo Decoding Based on Border Metric Encoding

This brief presents an energy-efficient soft-input soft-output (SISO) decoder based on border metric encoding, which is especially suitable for nonbinary circular turbo codes. In the proposed method, the size of the branch memory is reduced to half and the dummy calculation is removed at the cost of a small-sized memory that holds encoded border metrics. Due to the infrequent accesses to the border memory and its small size, the energy consumed for SISO decoding is reduced by 26.2%. Based on the proposed SISO decoder and the dedicated hardware interleaver, a double-binary tail-biting turbo decoder is designed for the WiMAX standard using a 0.18-mum CMOS process, which can support 24.26 Mbps at 200 MHz.     

一种低开销双二元turbo译码器设计

设计一种低开销双二元turbo译码器,提出了一种能够适应滑动窗算法的交织器结构,通过与传统方案中的交织器联合使用,大大降低了交织与解交织过程所需要的存储单元.同时将取模归一化(modulo normalization)技术运用到双二元turbo译码器加比选(ACS)模块的设计上,缩短了关键路径的延时,提高了时钟频率和吞吐量.采用FPGA对译码器进行了验证,提出的译码器和传统的译码器相比,存储资源节省12%,和使用存储器存储交织/解交织地址的译码器相比,存储资源节省97%.     

Parallel concatenated codes with unequal error protection

We show how parallel concatenated codes (PCCs, also known as “turbo codes”) can be endowed with unequal error protection (UEP). Given the two component encoders of the PCC encoder and the desired interleaver size, UEP is achieved by: (1) suitably positioning the different importance classes of information symbols into the encoder input frame; (2) puncturing the PCC redundancy symbols with a nonuniform pattern; and (3) choosing the interleaver of the PCC encoder in a class of interleavers that guarantees isolation of the importance classes. By controlling the amount of redundancy assigned to each importance class and the class positioning in the input frame, a whole family of UEP PCCs with different UEP levels can be obtained from the same component encoders and interleaver size. From a practical viewpoint, a family of UEP PCCs can be decoded by the same “turbo” iterative decoder, provided that the decoder hardware implementation allows for programmable puncturing and interleaving     

Design and Architecture of Low‐Latency High‐Speed Turbo Decoders

In this paper, we propose and present implementation results of a high‐speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix‐4, center to top, parallel decoding, and early‐stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real‐time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix‐4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field‐programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.     

基于FPGA的Turbo译码交织器设计

介绍了一种Turbo译码交织器的现场可编程门阵列（Field Programmable Gate Array，FPGA）硬件实现方案，将交织算法的软件编程和FPGA内部的硬件存储块相结合，有效地降低了译码器的硬件实现复杂度，减小了译码延时，并且给出了具体的译码器内交织器FPGA实现原理框图。     

Adaptive Channel Estimation Aided Log-Map Turbo Decoder Implementation for DS-CDMA Based Mobile Systems

Practical implementation of convolutional turbo codec is impeded by the difficulty of real-time execution in high transmission rate communication systems due to high computational complexity, iterative block decoding structure, as well as the requirement of accurate on-line channel reliability estimation for maximum-likelihood decoding. Relying on innovative channel estimation techniques involving DS-CDMA specific noise/interference variance estimation and fading channel variation tracking, this paper provides a low-complexity all-digital design of an iterative SISO log-MAP turbo decoder for DS-CDMA based mobile communication systems. The issues of quantization and data flow in both pre-decoder processing module and iterative trellis decoding module are prudently addressed to ensure highly efficient hardware implementation. The efficient design strategies applied confine the decoding complexity while leading to an excellent performance within 0.2 dB of the software decoder.     

基于无冲突多项式交织器的高速并行Turbo解码器

提出了基于高次多项式无冲突交织器的Turbo码并行解码的优化实现方法,解码器采用MAX-Log-MAP算法,完成了从Matlab算法设计验证到RTL设计、FPGA验证,并在LTE无线通信链路中验证.设计的Turbo并行高速解码器半次迭代的效率为6.9 bit/cycle,在最高迭代为5.5次、时钟频率为309MHz下,达到207Mb/s的吞吐率,满足高速无线通信系统的要求,交织和解交织采用存储器映射方法.该设计节约了计算电路和存储量.     

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture

This paper introduces a turbo decoder that utilizes multiple soft-in/soft-out (SISO) decoders to decode one codeword. In addition, each SISO decoder is modified to allow simultaneous execution over multiple successive trellis stages. The design issues related to the architecture with parallel high-radix SISO decoders are discussed. First, a contention-free interleaver for the hybrid parallelism is presented to overcome the complicated collision problem as well as reduce interconnection network complexity. Second, two techniques for the high-speed add-compare-select (ACS) circuits are given to lessen area overhead of the SISO decoder. Third, a modification of the processing schedule is made for higher operating efficiency. Two designs with parallel architecture have been implemented. The first design with 32 SISO decoders, each of which processes 2 symbols per cycle, has 160 Mb/s and 0.22 nJ/b/iter after measurement. The second design uses 16 SISO decoders to deal with 4 symbols per cycle and achieves 100% efficiency, leading to 1000 Mb/s and 0.15 nJ/b/iter in post-layout simulation.      

Design of fixed-point iterative decoders for concatenated codeswith interleavers

We discuss the effects of quantization on the performance of the iterative decoding algorithm of concatenated codes with interleavers. Quantization refers here to the log-likelihood ratios coming from the soft demodulator and to the extrinsic information passed from one stage of the decoder to the next. We discuss the cases of a single soft-input soft-output (SISO) module, in its additive log-likelihood version (L-SISO), performing sequentially all iterations (an implementation solution coping with medium-low data rate as compared with the hardware clock), and that of a pipelined structure in which a dedicated hardware is in charge of each SISO operation (an implementation suitable for high data rates). We give design rules in both cases, and show that a suitable rescaling of the extrinsic information yields almost ideal performance with the same number of bits (five) representing both log-likelihood ratios and extrinsic information at any decoder stage     

Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems

For high-mobility 4G applications of LTE-A and WiMAX-2 systems, this paper presents a dual-standard turbo decoder design with the following three techniques. 1) Circular parallel decoding reduces decoding latency and improves throughput rate. 2) Collision-free vectorizable dual-standard parallel interleaver enhances hardware utilization of the interleaving address generator. 3) One-bank extrinsic buffer design with bit-level extrinsic information exchange reduces size of the extrinsic buffer compared with the two-bank extrinsic buffer design. Furthermore, a multi-standard turbo decoder chip is fabricated in a core area of 3.38 mm² by 90 nm CMOS process. This chip is maximally measured at 152 MHz with 186.1 Mbps for LTE-A standard and 179.3 Mbps for WiMAX-2 standard.     

Very Low-Complexity Hardware Interleaver for Turbo Decoding

This brief presents a very low complexity hardware interleaver implementation for turbo code in wideband CDMA (W-CDMA) systems. Algorithmic transformations are extensively exploited to reduce the computation complexity and latency. Novel VLSI architectures are developed. The hardware implementation results show that an entire turbo interleave pattern generation unit consumes only 4 k gates, which is an order of magnitude smaller than conventional designs.     

A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-/spl mu/m CMOS

A channel decoder chip compliant with the 3GPP mobile wireless standard is described. It supports both data and voice calls simultaneously in a unified turbo/Viterbi decoder architecture. For voice services, the decoder can process over 128 voice channels encoded with rate 1/2 or 1/3, constraint length 9 convolutional codes. For data services, the turbo decoder is capable of processing any mix of rate 1/3, constraint length 4 turbo encoded data streams with an aggregate data rate of up to 2.5 Mb/s with 10 iterations per block (or 4.1 Mb/s with six iterations). The turbo decoder uses the logMAP algorithm with a programmable logsum correction table. It features an interleaver address processor that computes the 3GPP interleaver addresses for all block sizes enabling it to quickly switch context to support different data services for several users. The decoder also contains the 3GPP first channel de-interleaving function and a post-decoder bit error rate estimation unit. The chip is fabricated in a 0.18-/spl mu/m six-layer metal CMOS technology, has an active area of 9 mm/sup 2/, and has a peak clock frequency of 110.8 MHz at 1.8 V (nominal). The power consumption is 306 mW when turbo decoding a 2-Mb/s data stream with ten iterations per block and eight voice calls simultaneously.     

Interleaving on Parallel DSP Architectures

Today's communications systems especially in the field of wireless communications rely on many different algorithms to provide applications with constantly increasing data rates and higher quality. This development combined with the wireless channel characteristics as well as the invention of turbo codes has particularly increased the importance of interleaver algorithms. In this paper, we demonstrate the feasibility to exploit the hardware parallelism in order to accelerate the interleaving procedure. Based on a heuristic algorithm, the possible speedup for different interleavers as a function of the degree of parallelism of the hardware is presented. The parallelization is generic in the sense that the assumed underlying hardware is based on a parallel datapath DSP architecture and therefore provides the flexibility of software solutions.     

Multistage recursive interleaver for turbo codes in DS-CDMA mobileradio

A multistage recursive block interleaver (MIL) is proposed for the turbo code internal interleaver. Unlike conventional block interleavers, the MIL repeats permutations of rows and columns in a recursive manner until reaching the final interleaving length. The bit error rate (BER) and frame error rate (FER) performance with turbo coding and MIL under frequency-selective Rayleigh fading are evaluated by computer simulation for direct-sequence code-division multiple-access mobile radio. The performance of rate-1/3 turbo codes with MIL is compared with pseudorandom and S-random interleavers assuming a spreading chip rate of 4.096 Mcps and an information bit rate of 32 kbps. When the interleaving length is 3068 bits, turbo coding with MIL outperforms the pseudorandom interleaver by 0.4 dB at an average BER of 10^-6 on a fading channel using the ITU-R defined Vehicular-B power-delay profile with the maximum Doppler frequency of f_D = 80 Hz. The results also show that turbo coding with MIL provides superior performance to convolutional and Reed-Solomon concatenated coding; the gain over concatenated coding is as much as 0.6 dB     

Parallel turbo coding interleavers: avoiding collisions in accessesto storage elements

High-speed, low latency convolutional turbo codes require a parallel decoder architecture. To maximise the gain in speed, the interleaver also should have a parallel structure. Here, a class of optimum parallel interleavers regarding the access to storage elements is presented. They combine regularity (easy implementation) with no latency in data transfer between the decoder module and intrinsic/extrinsic values memories, and show excellent BER performance