New hot-carrier-degradation mode in thin-film SOI nMOSFET's

A new hot-carrier degradation mode peculiar to MOSFET's fabricated on thin-film SOI is described. This degradation mode, which occurs in nMOSFET's more easily than in pMOSFET's, is due to suppression of parasitic bipolar action caused by recombination of excess carriers through hot-carrier-induced front interface-traps. Threshold voltage is significantly shifted by this phenomenon. The reliability lifetime defined by threshold voltage shift and drain current degradation is also discussed, considering the new degradation mode     

Measurement and modeling of self-heating in SOI nMOSFET's

Self-heating in SOI nMOSFET's is measured and modeled. Temperature rises in excess of 100 K are observed for SOI devices under static operating conditions. The measured temperature rise agrees well with the predictions of an analytical model and is a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation. Under dynamic circuit conditions, the channel temperatures are much lower than predicted from the static power dissipation. This work provides the foundation for the extraction of device modeling parameters for dynamic operation (at constant temperature) from static device characterization data (where temperature varies widely). Self-heating does not greatly reduce the electromigration reliability of SOI circuits, but might influence SOI device design, e.g., requiring a thinner buried oxide layer for particular applications and scaled geometries     

Subthreshold slope of thin-film SOI MOSFET's

Silicon-on-insulator (SOI) n-channel transistors have been made in thin (90 nm) silicon films. Both modeling and experimental results show that excellent subthreshold slopes can be obtained (62 mV/ decade) when the silicon film thickness is smaller than the maximum depletion depth in the transistor channel. For comparison, the subthreshold slope of transistors made in thicker films is also reported.     

Subthreshold slope in thin-film SOI MOSFETs

The subthreshold conduction regime in thick- and thin-film SOI MOSFETs is studied. Using the depletion approximation, a one-dimensional analytical expression for the subthreshold slope is derived, and equivalence with a simple capacitive network is proven. The model accounts for the influence of the back interface properties on the subthreshold swing in the thin-film regime. The coupling between front and back surface potential and the influence of the backside conduction on the front interface characteristics are accounted for. The case of double gate control is studied in more detail. Experimental verification of the model with measured subthreshold slopes in thin-form MOSFET devices is given     

Time-dependent snapback in thin-film SOI MOSFET's

During pulsed stressing of SOI MOSFETs for ESD characterization, the turn-on voltage of the parasitic bipolar transistor was observed to be a function of the stress pulse-width. This observation can be understood in terms of a capacitive charging model. The theory behind this time-dependent snapback is presented in this letter along with the experimental results. Comparisons with bulk-Si devices indicate that this phenomenon is specific to SOI and is a manifestation of the floating body effect     

Special mechanisms in thin-film SOI MOSFETs

The main special mechanisms that govern the operation of thin-film SOI MOSFETs are reviewed. The influence of the most important technological and electrical parameters, e.g. the film and buried oxide thicknesses, film and silicon substrate doping, channel length, substrate bias, and interface defects, is discussed. The electrical properties of fully depleted thin-film SOI MOS transistors are improved, especially the driving current and the subthreshold swing. We address the advantages of thin-film SOI devices in relation to scaling rules down to deep submicron transistors, as well as the main parasitic phenomena, e.g. the kink, latch, breakdown, self-heating and hot-carrier degradation effects. Finally, the low temperature properties and potential quantum effects are outlined.     

LOCOS-induced stress effects on thin-film SOI devices

LOCOS-induced stress effects on thin-film SOI devices are investigated. We show that as the field oxide thickness increases, degradation (enhancement) of nMOSFET's (pMOSFET's) I-V characteristics becomes increasingly pronounced. The total degradation or enhancement of I-V characteristics can reach ~40% of drive current for devices under certain processing conditions. Estimated stress results using four-point bending measurement show that the stress level on the silicon film is of order 1200 MPa for devices with ~40% of I-V degradation/enhancement. We attribute the stress phenomenon to the volumetric expansion of field oxide during the LOCOS process     

Single-transistor-latch-induced degradation of front- andback-channel thin-film SOI transistors

The front- and back-channel transistor characteristics in thin-film silicon-on-insulator (SOI) MOSFETs have been studied before and after front-channel hot-carrier stress resulting from single-transistor latch. This stress causes the following significant changes: (a) a reduction of the front-channel current for a given gate voltage, (b) an increase in front-channel drain-source breakdown voltage when measured in the reverse mode, and (c) a decrease in the back-channel transconductance. These changes can be attributed to the hot-carrier induced interface traps on both front and back interfaces near the drain junction     

Reduction of kink effect in thin-film SOI MOSFETs

Numerical simulation is used to show that potential and electric field distribution within thin, fully depleted SOI devices is quite different from that observed within thicker, partially depleted devices. Reduction of drain electric field and of source potential barrier brings about a dramatic decrease of kink effect     

一种能够抑制部分耗尽SOI nMOSFET浮体效应的新型Schottkty体接触结构的模拟

提出了一种新型的Schottky体接触结构,能够有效抑制部分耗尽SOI nMOSFET的浮体效应.这种结构可以通过在源区形成一个浅的n+-p结和二次侧墙,然后生长厚的硅化物以穿透这个浅结的方法来实现.模拟结果表明这种结构能够成功抑制SOI nMOSFET中存在的反常亚阈值斜率和kink效应,漏端击穿电压也有显著提高.这种抑制浮体效应的方法不增加器件面积,而且与体硅MOSFET工艺完全兼容.     

Tantalum-gate thin-film SOI nMOS and pMOS for low-powerapplications

The threshold voltages of thin-film fully-depleted silicon-on-insulator (FDSOI) nMOS and pMOS have been controlled by employing tantalum (Ta) as the gate materials. Ta-gate FDSOI MOSFET's have excellent threshold voltage control for 1.0 V application on low impurity concentration SOI layers in both nMOS and pMOS. The low-temperature processing after the gate oxidation step leads to good on/off characteristics in Ta-gate SOI MOSFET's because of no reaction between Ta gate electrode and SiO₂ gate insulator. This technology makes it possible to drastically decrease the number of the process steps for CMOS fabrication, because the same gate material is available for both nMOS and pMOS     

Degradation in thin-film SOI MOSFET's caused by single-transistorlatch

The measurement of anomalous hot-carrier damage in thin-film n-channel SOI MOSFETs is reported. Due to the presence of a parasitic bipolar transistor between the source and drain, the minimum drain voltage for breakdown in these devices occurs when the device is biased in subthreshold. Using charge-pumping measurements, it is shown that if the device is biased in this regime, where single-transistor latch occurs, hot holes are injected into the gate oxide near the drain. Consequently, the maximum allowable drain voltage for these devices is governed by the parasitic bipolar properties of the SOI MOSFET     

Surface potential at threshold in thin-film SOI MOSFET's

The usual condition for threshold in bulk MOSFETs, of equal rates of change with gate voltage of the inversion and bulk charges, is suitably modified to describe threshold in fully depleted SOI MOSFETs. Using this modified condition the value of the surface potential at threshold in fully depleted transistors is obtained analytically in terms of device dimensions, film doping level, and applied voltages. The results are in excellent agreement with one-dimensional numerical simulations, and it is shown that the surface potential at threshold may differ significantly from 2φ_F, the value conventionally assumed     

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

Previous conflicting reports concerning fully depleted SOI device hot electron reliability may result from overestimation of channel electric field (E_m). Experimental results using SOI MOSFET's with body contacts indicate that E_m is just a weak function of thin-film SOI thickness (T_si and that E_m can be significantly lower than in a bulk device with drain junction depth (X _j) comparable to SOI's T_si. The theoretical correlation between SOI MOSFET's gate current and substrate current are experimentally confirmed. This provides a means (I_G) of studying E_m in SOI device without body contacts. Thin-film SOI MOSFET's have better prospects for meeting breakdown voltage and hot-electron reliability requirements than previously thought     

Reduction of floating substrate effect in thin-film SOI MOSFETs

The presence of a floating substrate in SOI transistors gives rise to a decrease of threshold voltage when drain voltage is increased. When the devices are made in a very thin silicon film, the latter is completely depleted when the device is in the 'on' state, and no part of the film can act as a floating substrate. This brings about a dramatic decrease of the so-called 'kink effect'.     

On the high-temperature subthreshold slope of thin-film SOI MOSFETs

This paper addresses the validity of the classical expression for the subthreshold swing (S) in SOI metal-oxide semiconductor field effect transistors (MOSFETs) at high temperature. Using numerical simulation, it is shown that two effects invalidate the classical expression of S at high temperature. Firstly, the depletion approximation becomes invalid and intrinsic free carriers must be taken into account to determine the effective body capacitance. Secondly, the charge-sheet model for the inversion layer becomes inaccurate due to a lowering of the electric field at the surface and a broadening of the inversion layer thickness in weak inversion. These effects must be taken into account to predict accurately the high-temperature subthreshold characteristics of both partially depleted and fully depleted SOI MOSFETs     

Current-voltage characteristics of thin-film SOI MOSFET's in strong inversion

A simple analytic model for the steady-state current-voltage characteristics of strongly inverted silicon-on-insulator (SOI) MOSFET's is developed. The model, simplified by a key approximation that the inversion charge density is described well by a linear function of the Surface potential, clearly shows the dependence of the drain current on the device parameters and on the terminal voltages, including the back-gate (substrate) bias. The analysis is supported by measurements of current-voltage characteristics of thin-film (laser-recrystallized) SOI MOSFET's. The dependence of carrier mobility on the terminal voltages, especially the back-gate bias, is analyzed and shown to underlie discrepancies between the theoretical (constant mobility) and experimental results at high gate voltages. The mobility dependence on the back-gate bias enhances the strong influence of the back gate on the drain current, especially when the device is saturated.     

Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's

The charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI: e.g,, recrystallized Si on SiO2) MOSFET's is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived. The expressions clearly show the dependence of the linear-region channel conductance on the back-gate bias and on the device parameters, including those of the back silicon-insulator interface. The analysis is supported by current-voltage measurements of laser-recrystallized SOI MOSFET's. The results suggest how the back-gate bias may be used to optimize the performance of the SOI MOSFET in particular applications.     

The ESD protection mechanisms and the related failure modes and mechanisms observed in SOI snapback nMOSFET's

The objective of this paper is to discuss the characteristics of SOI nMOSFET's that can be exploited to clamp HBM ESD stresses and to explain the related failure modes and mechanism observed in these devices. The influence on the HBM ESD protection capability of the first order main parameter: the nMOSFET gate length is investigated. The ESD protection capability for both positive and negative polarity HBM stresses is elaborated and compared. The ESD clamping and device failure mechanisms limiting the ESD protection performance are identified.