Scan chain design for shift power reduction in scan-based testing

Test power of VLSI systems has become a challenging issue nowadays.The scan shift power dominates the average test power and restricts clock frequency of the shift phase,leading to excessive thermal accumulation and long test time.This paper proposes a scan chain design technique to solve the above problems.Based on weighted transition metric (WTM),the proposed extended WTM (EWTM) that is utilized to guide the scan chain design algorithm can estimate the scan shift power in both the shift-in and shift-out p...     

一种基于轮流扫描捕获的低功耗低费用BIST方法

过高的测试功耗和过长的测试应用时间是基于伪随机内建自测试(BIST)的扫描测试所面临的两大主要问题.提出了一种基于扫描子链轮流扫描捕获的BIST方法.在提出的方法中,每条扫描链被划分成N(N>1)条子链,使用扫描链阻塞技术,同一时刻每条扫描链中只有一条扫描子链活跃,扫描子链轮流进行扫描和捕获,有效地降低了扫描移位和响应捕获期间扫描单元的翻转频率.同时,为检测抗随机故障提出了一种适用于所提出测试方法的线性反馈移位寄存器(LFSR)种子产生算法.在ISCAS89基准电路上进行的实验表明,提出的方案不但降低约(N-1)?N的平均功耗和峰值功耗,而且显著地减少随机测试的测试应用时间和LFSR重播种的种子存储量.     

带时间参数的测试产生

进延测试对于高速集成电路非常重要。本文介绍一个带时间参烽的时延测试产生系统。该系统使用一个时刻逻辑值来表示一个波形,并将输入波形限制为只有唯一的一个输入在０时刻有跳变,其它输入为稳定的０或１,从而实现了波形敏化条件下的时延测试产生,与以往的不考察时间因素的时延测试产生系统相比,带时间参烽的测试产生提高了故障覆盖率,并且更接近于电路的实际。     

扫描链故障确定性诊断向量生成算法

扫描技术是一种广泛采用的结构化可测试性设计方法,是提高测试质量的有效手段.但由于扫描链及其控制逻辑可能会占到整个芯片面积的30%,因此扫描链故障导致的失效可能会达到失效总数的50%.提出一种扫描链故障确定性诊断向量生成算法:首先建立了诊断扫描链故障的电路模型,利用该模型可以采用现有固定型故障测试生成工具产生扫描链诊断向量;然后提出一种故障响应分析方法,以有效地降低候选故障对的数量,从而在保障诊断质量的前提下减少诊断向量数目,缩短了诊断过程的时间.实验结果表明,在测试诊断精确度、故障分辨率和向量生成时间方面,该算法均优于已有的扫描链诊断向量生成方法.     

基于多扫描链的内建自测试技术中的测试向量生成

针对基于多扫描链的内建自测试技术,提出了一种测试向量生存方法。该方法用一个线性反馈移位寄存器（LFSR）作为伪随机测试向量生成器,同时给所有扫描链输入测试向量,并通过构造具有最小相关度的多扫描链克服扫描链间的相关性对故障覆盖率的影响。此外该方法经过模拟确定难测故障集,并针对这外难测故障集利用ATPG生成最小确定性测试向量集。最后丙依据得到的最小测试向量集来设计位改变逻辑电路,利用们改变逻辑电路控制改变扫描链上特定的值来实现对难测故障的检测,从而实现被测电路和故障完全检测。     

Scan BIST with biased scan test signals

The conventional test-per-scan built-in self-test （BIST） scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flipflops are shifted out while shifting in the next test vector like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the test signals of the scan chains. Different biased random values are assigned to the test signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly, and most circuits can obtain complete fault coverage or very close to complete fault coverage.     

A Universal BIST Approach for Virtex-Ultrascale Architecture

Interconnected cells, Configurable Logic Blocks (CLBs), and input/output (I/O) pads are all present in every Field Programmable Gate Array (FPGA) structure. The interconnects are formed by the physical paths for connecting the blocks . The combinational and sequential circuits are used in the logic blocks to execute logical functions. The FPGA includes two different tests called interconnect testing and logical testing. Instead of using an additional circuitry, the Built-in-Self-Test (BIST) logic is coded into an FPGA, which is then reconfigured to perform its specific operation after the testing is completed. As a result, additional test circuits for the FPGA board are no longer required. The FPGA BIST has no area overhead or performance reduction issues like conventional BIST. A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation. In this work, the Configurable Logic Blocks (CLBs) of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture. To evaluate the CLBs’ capabilities including distributed modes of operation of Random Access Memory (RAM), several types of configurations are created. These setups have the ability to identify 100% stuck-at failures in every CLB. This method is suitable for all phases of FPGA testing and has no overhead or performance cost.     

一种逻辑仿真测试平台的设计

目前在开发网络设备的大规模数字系统中，仿真验证阶段自动化程度不高，以至投人的人力大、产品开发周期长。该文针对这种情况，提出了ATM、IP、SDH领域内的一种逻辑仿真测试平台(以下简称平台)的程序设计方案。平台由仿真器启动，支持激励数据的自动化生成和分析验证的自动化进行，并且平台的通用性设计使得它可以在不同的操作系统下适用于较多的逻辑业务。实践表明，根据该设计方案开发的平台，在各个部门的推广使用，明显提高了部门的生产效率，显著缩短了产品的开发周期，节省了人力。     

Test generation from state based use case models

We present a strategy for the automatic generation of test cases from parametrised use case templates that capture control flow, state, input and output. Our approach allows test scenario selection based on particular traces or states of the model. The templates are internally represented as CSP processes with explicit input and output alphabets, and test generation is expressed as counter-examples of refinement checking, mechanised using the FDR tool. Soundness is addressed through an input–output conformance relation formally defined in the CSP traces model. This purely process algebraic characterisation of testing has some potential advantages, mainly an easy automation of conformance verification and test case generation via model checking, without the need to develop any explicit algorithm.     

A built-in test module for fault isolation

A broad-level implementation of signature analysis that uses a built-in test module called a testing switch is presented. It is shown how board designers can incorporate the testing-switch modules to reduce the time it takes to isolate faulty chips. Both the test time and the power overhead are better with the testing-switch implementation than with schemes using built-in logic block observer circuits. The proposed technique is especially useful when boundary scan and self-test cannot be implemented in every chip of a board     

一种基于模型的并发系统测试目的描述

提出了带约束事件的时序逻辑TLCE,用于描述系统运行中输入/输出事件之间的时序关系以及对事件参数的数据相关性约束。阐述了一种基于模型的并发系统测试框架,采用TLCE描述测试目的以引导测试用例生成。缓存一致性协议和会议协议的实例研究中所生成的测试用例集显著优于随机测试用例集。这说明了TLCE作为测试目的描述的有效性。     

基于LDRA Testbed的软件完整性静态测试方法研究

根据软件测试工具LDRA Testbed的特点,本文提出了一种基于LDRA Testbed的软件完整性静态测试方案。该方案策略性选取四种测试方法,详细描述了每种方法的测试过程,输入项和输出项。实际运用中表明此方案极大提高了测试效率和测试规范性。     

Built-In Self-Test Structures

A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit response. This article surveys the structures that are used to implement these self-test functions. The various techniques used to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/O bonding pads so that the pads can be accessed via a scan path (external or boundary scan path) is described. Most designs use linear-feedback shift registers for both test pattern generation and response analysis. The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.     

普及型教学计算机系统的设计与实现

文章介绍了对计算机硬件系列的课程教学和实验研制的一种全新的实验计算机系统。该计算机８位字长,硬件（包括ＣＰＵ）子系统和软件（包括指令系统）子系统完全自行设计,配置合理,设计新颖,实验性能强。运算器部件选用位片结构器件实现,控制器部分采用微程序或组合逻辑方案实现,在监控程序支持下,能接入多种外设,在不同方式下完成输入／输出操作。有比较高的性能／价格比,使用效果令人满意。     

Built-In Self-Test Techniques

A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit response. This article surveys the structures that are used to implement these self-test functions. The various techniques used to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/O bonding pads so that the pads can be accessed via a scan path (external or boundary scan path) is described. Most designs use linear-feedback shift registers for both test pattern generation and response analysis. The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.     

大规模数字集成电路标准矩阵功能测试新方法

本文提出了一种对VLSI电路功能测试的方法,可以同时检测和定位VLSI电路输入和输出端上的固定故障和桥接故障,而不需要知道它们的内部逻辑结构。因而,对于简化测试过程、降低测试成本,具有十分重要的实际意义。     

Software testing based on SDL specifications with save

The signal save construct is one of the features distinguishing SDL from traditional high-level specification and programming languages. However, this feature increases the difficulties of testing SDL-specified software. We present a testing approach consisting of the following three phases: SDL specifications are first abstracted into finite state machines with save constructs, called SDL-machines; the resulting SDL-machines are then transformed into equivalent finite state machines without save constructs if this is possible; and, finally, test cases are selected from the resulting finite state machines. Since there are many existing methods for the first and third phases, we mainly concentrate upon the second phase and come up with a method of transforming SDL-machines into equivalent finite state machines, which preserve the same input/output relationship as in the original SDL-machines. The transformation method is useful not only for testing but also for verifying SDL-specified software     

一类具有排队现象的工作流图的性能分析

基于极大代数方法,描述一类具有排队现象的工作流图中AND和XOR的时间逻辑关系.AND逻辑表示输出事件当且仅当输入事件都完成时发生,XOR逻辑表示在数个输入事件中按概率只有一个会发生并导致输出事件的发生.以AND和XOR基本模块构建这类工作流图模型,进行系统的性能分析,并给出顾客输出时间间隔下界的估计方法.通过实例仿真验证了建模、分析方法的可行性和有效性.     

UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting

Industry has used scan-based designs widely to promote test quality. However, for larger designs, the growing test data volume has significantly increased test cost because of excessively long test times and elevated tester memory and external test channel requirements. To address these problems, researchers have proposed numerous test compression architectures. In this article, we propose a flexible scan test methodology called universal multicasting scan (UMC scan). It has three major features: First, it provides a better than state-of-the-art test compression ratio using multicasting. Second, it accepts any existing test patterns and doesn't need ATPG support. Third, unlike most previous multicasting schemes that use mapping logic to partition the scan chains into hard configurations, UMC scan's compatible scan chain groups are defined by control bits, as in the segmented addressable scan (SAS) architecture. We have developed several techniques to reduce the extra control bits so that the overall test compression ratio can approach that of the ideal multicasting scheme.     

Semantics guided regression test cost reduction

Software maintainers are faced with the task of regression testing: retesting a modified program on an often large number of test cases. The cost of regression testing can be reduced if the size of the program is reduced and if old test cases and results can be reused. Two complimentary algorithms for reducing the cost of regression testing are presented. The first produces a program called Differences that captures the semantic change between Certified, a previously tested program, and Modified, a changed version of Certified. It is more efficient to test Differences, because it omits unchanged computations. The program Differences is computed using a combination of program slices. The second algorithm identifies test cases for which Certified and Modified produce the same output and existing test cases that test new components in Modified. The algorithm is based on the notion of common execution patterns. Program components with common execution patterns have the same execution pattern during some call to their procedure. They are computed using a calling context slice. Whereas an interprocedural slice includes the program components necessary to capture all possible executions of a statement, a calling context slice includes only those program components necessary to capture the execution of a statement in a particular calling context. Together with Differences, it is possible to test Modified by running Differences on a smaller number of test cases. This is more efficient than running Modified on a large number of test cases. A prototype implementation has been built to examine and illustrate these algorithms