EPON技术在平价商店物价监管平台建设中的应用

为满足物价部门对平价商店信息点价格数据采集和物价监管的需要,从网络系统的安全性、灵活性和易维护性等角度考虑,采用EPON组网技术,设计了一套平价商店物价监管网络服务支撑平台解决方案,并以六安市物价监管平台建设为例,阐述了网络建设中的网络架构、光分配网设计和多业务控制网关数据配置等具体实践。     

The Design of a High-Performance Error-Correcting Coding Scheme for the Canadian Broadcast Telidon System Based on Reed-Solomon Codes

Error correction can greatly improve the performance and extend the range of broadcast teletext systems. In this paper, the requirements for an error-correcting scheme for broadcast teletext in North America (NABTS) are set down. An error-correction scheme which meets all these requirements is then described. The simplest case employs the one parity bit in each 8 bit byte and no suffix of parity check bits at the end of each data block. The next level also uses a single byte of parity check bits at the end of each data block. Adding a second byte of parity checks at the end of each data block results in a Reed-Solomon code, called theCcode, for each data block. Adding one data block of parity checks afterh - 1data blocks results in a set ofhdata packets being encoded into a bundle, in which verticalCcodes provide powerful interleaving. In a final alternative, two data blocks hold the check bytes for the vertical codewords, and the most powerful coding scheme, the double bundle code, results. The detailed mathematical definitions of the various codes are referred to or described, formulas for performance calculations are referred to, and performance curves are presented for the AWGN channel as well as for measured field data. These performance curves are discussed and compared to the performance of a difference set cyclic code, originally designed for the Japanese teletext system, which corrects any 8 bits in error in a packet.     

An 860-Mb/s (8158,7136) Low-Density Parity-Check Encoder

Low-density parity-check codes achieve coding performance which approaches the Shannon limit. An (8158,7136) encoder was implemented in a five-metal, 0.25-$muhbox m$CMOS process. Use of generator polynomial reconstruction, partial product multiplication and functional sharing in the parity register results in a highly efficient design. Only 1492 flip-flops along with a programmable 21-bit look-ahead scheme are used to achieve an 860-Mb/s data throughput for this rate 7/8 LDPC code. A comparable two-stage encoder requires 8176 flip-flops.     

Modifying real convolutional codes for protecting digital filteringsystems

A method is presented for protecting the overall realization of digital filters implemented with very dense high-speed electronic devices against both hard and soft errors at the data sample level using the error-detecting properties of real convolutional codes. The normal filter system is surrounded with parallel parity channels defined by a real systematic rate k/n convolutional code. Erroneous behavior is detected by comparing externally the calculated and regenerated parity samples. Significant complexity reductions are possible by modifying the code structure, without loss of error protection, yielding simplified parity channels with finite impulse response (FIR) structures with computational rates decimated by k . The code modification procedure is described. The code modification process has been automated in a computer algorithm. The effects of parity filter quantizations are analyzed and a bound on the mean-square error in the parity comparison is given     

VLSI Implementation of Forward Error Control Technique for ATM Networks

In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very‐large‐scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a 5 ° 5 matrix of data cells in a Virtex‐E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.     

基于FPGA的参数可调RS422接口电路设计实现

介绍了一种基于FPGA的波特率可变、数据位和停止位长度可调、奇偶校验功能可选的RS422串行信号接口电路设计。该设计以Altera的Cyclone系列芯片EP3C80F780I7作为控制芯片,以ADI的ADM2687EBRIZ作为RS422差分信号处理芯片。此外,该设计所有运算功能均采用硬件逻辑实现,具有可靠性高、通用性强的特点。     

Interleaver design for turbo codes

The performance of a turbo code with short block length depends critically on the interleaver design. There are two major criteria in the design of an interleaver: the distance spectrum of the code and the correlation between the information input data and the soft output of each decoder corresponding to its parity bits. This paper describes a new interleaver design for turbo codes with short block length based on these two criteria. A deterministic interleaver suitable for turbo codes is also described. Simulation results compare the new interleaver design to different existing interleavers     

On the Exploitation of Narrow-Width Values for Improving Register File Reliability

Protecting the register value and its data buses is crucial to reliable computing in high-performance microprocessors due to the increasing susceptibility of CMOS circuitry to soft errors induced by high-energy particle strikes. Since the register file is in the critical path of the processor pipeline, any reliable design that increases either the pressure on the register file or the register file access latency is not desirable. In this paper, we propose to exploit narrow-width register values, which present the majority of the generated values, for making a duplicate of the value within the same data item; this in-register duplication (IRD) eliminates the requirement for additional copy registers. The datapath pipeline is augmented to efficiently incorporate parity encoding and parity checking such that error recovery is seamlessly supported in IRD and the parity checking is overlapped with the execution stage to avoid increasing the critical path. A detailed architectural vulnerability factor (AVF) analysis shows that IRD significantly reduces the AVF from 8.4% in a conventional unprotected register file to 0.1% in an IRD register file. Our experimental evaluation using the SPEC CINT2000 benchmark suite also shows that IRD provides superior read-with-duplicate (RWD) and error detection/recovery rates under heavy error injection as compared to previous reliability schemes, while only incurring a small power overhead.      

Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders

Many recent reconfigurable/multi-mode quasi-cyclic low density parity check (QC-LDPC) decoder designs have shown appealing implementation results in the literature. However, most of them are based on datapath multiplexing techniques with ad hoc matrix arrangement. There is still room for further interconnection reduction, throughput enhancement, and a more sophisticated early termination scheme. In this paper, we will focus on these issues and present a two-level design approach, which optimizes the design at (1) matrix merging level, and (2) module design level. First, direct multiplexing datapaths between multiple modes leads to great overhead on wiring complexity. In order to mitigate this problem, we merge multiple parity check matrices by proposing an efficient algorithm at matrix merging level, which helps to minimize multiplexer and wiring overhead. Second, for efficient decoding issues, we propose two design techniques at module design level. One is data wrapping scheme. It enhances the decoding throughput by using the data-wrapped memory with the proposed reconfigurable data-switching circuits (R-DSC) to conquer the data alignment problem and achieve multi-mode reconfigurability. The other is the adaptive early termination (AET) scheme. It can save the unnecessary decoding procedures under both high-SNR and low-SNR regions. Finally, to verify our design approach, we implement a triple-mode LDPC decoder chip which is compatible to IEEE 802.11n standard by using UMC 90 nm CMOS technology. This chip only occupies 3.32 mm² and features high core utilization up to 70% with low power dissipation of 135.3 mW. The prototyping chip not only validates the proposed approach, but also outperforms the state-of-the-art QC-LDPC decoders for IEEE 802.11n systems.     

基于高斯近似的IRA码构造算法研究

介绍了非规则重复累积码(IRA)的结构,对其Tanner图和校验矩阵进行了分析。IRA码的构造分为优化度分布和设计奇偶校验矩阵2部分。在AWGN信道下,对给定的噪声方差,采用高斯近似的方法优化度分布并得出优化结果。根据度分布和相应规则设计奇偶校验矩阵,给出了设计步骤。对设计出的码进行计算机仿真,结果表明这类码相对于计算机随机构造的LDPC码能带来性能上的提高,且随码长增加,码的性能有明显改善。     

A CMOS mainframe processor with 0.5-μm channel length

A processor chip set with IBM/370 architecture is implemented on five CMOS VLSI chips containing 2.8 million transistors with an effective channel length of 0.5 μm. The chip set consists of the instruction and the fixed-point processor, two cache chips with 16 KB of data and instructions, and the floating-point processor. The chips are implemented in a 1.0-μm technology with three layers of metal. An automatic design system based on the sea-of-gates technique and the standard cell approach was used. The worst-case operating frequency of the chip set is 35 MHz (typically 50 MHz). Four chips of the processor are packaged on a ceramic multichip module. Level-sensitive scan design, built-in self-test, and parity check guarantee high test coverage and reliability     

基于量子元胞自动机的奇偶校验系统分块设计

量子元胞自动机(QCA)是一种纳米范围内不含晶体管的计算范例。基于QCA提出了QCA奇偶校验系统电路的分块设计方法。首先设计了异或门、奇偶判断单元,再运用分块设计思想构建了奇数产生电路和奇偶校验电路的结构,所设计的电路拥有尺寸极小和功耗极低等优点,QCADesigner软件仿真结果验证了设计的有效性。     

A general construction of constrained parity-check codes for optical recording

This paper proposes a general and systematic code design method to efficiently combine constrained codes with parity-check (PC) codes for optical recording. The proposed constrained PC code includes two component codes: the normal constrained (NC) code and the parity-related constrained (PRC) code. They are designed based on the same finite state machine (FSM). The rates of the designed codes are only a few tenths below the theoretical maximum. The PC constraint is defined by the generator matrix (or generator polynomial) of a linear binary PC code, which can detect any type of dominant error events or error event combinations of the system. Error propagation due to parity bits is avoided, since both component codes are protected by PCs. Two approaches are proposed to design the code in the non-return-to-zero-inverse (NRZI) format and the non-return-to-zero (NRZ) format, respectively. Designing the codes in NRZ format may reduce the number of parity bits required for error detection and simplify post-processing for error correction. Examples of several newly designed codes are illustrated. Simulation results with the Blu-Ray disc (BD) systems show that the new d = 1 constrained 4-bit PC code significantly outperforms the rate 2/3 code without parity, at both nominal density and high density.     

An LSI Implementation of an Intelligent CRC Computer and Programmable Character Comparator

Manufacturers of MOS microprocessors have been expanding their product families to include function or task oriented LSI peripheral controllers. In the data communications area, circuits such as universal synchronous/asynchronous receiver/transmitters, bit oriented data link controllers, and multiprotocol handlers have greatly simplified systems design. This paper describes a totally unique device-the polynomial generator checker (WC) that monitors transactions on a data bus and performs functions such as programmable character comparisons, parity generation/checking, and "intelligent" block error generation/checking. An overview of character oriented data link controls and cyclic redundancy check/longitudinal redundancy check (CRC/LRC) provides an introduction to the functions and applications of the PGC. Several innovative architectural constructs be described that enable the device to fit within the die cavity of a 16 pin dual-in-like package.     

Design of serial concatenated MSK schemes based on density evolution

We consider the design of convolutional codes and low density parity check (LDPC) codes with minimum-shift keying (MSK) when the receiver employs iterative decoding and demodulation. The main idea proposed is the design of coded schemes that are well matched to the iterative decoding algorithm being used rather than to hypothetical maximum-likelihood decoding. We first show that the design is crucially dependent on whether the continuous phase encoder (CPE) is realized in recursive form or in nonrecursive form. We then consider the design of convolutionally coded systems and low density parity check codes with MSK to obtain near-capacity performance. With convolutional codes, we show that it is possible to improve the performance significantly by using a mixture of recursive and nonrecursive realizations for the CPE. For low density parity check codes, we show that codes designed for binary phase shift keying are optimal for MSK only if the nonrecursive realization is used; for the recursive realization, we design new LDPC codes based on the concept of density evolution. We show that these codes outperform the best known codes for MSK and have lower decoding complexity.     

PEEC: a channel-adaptive feedback-based error

Reliable transmission is a challenging task over wireless LANs since wireless links are known to be susceptible to errors. Although the current IEEE802.11 standard ARQ error control protocol performs relatively well over channels with very low bit error rates (BERs), this performance deteriorates rapidly as the BER increases. This paper investigates the problem of reliable transmission in a contention free wireless LAN and introduces a packet embedded error control (PEEC) protocol, which employs packet-embedded parity symbols instead of ARQ-based retransmission for error recovery. Specifically, depending on receiver feedback, PEEC adaptively estimates channel conditions and administers the transmission of (data and parity) symbols within a packet. This enables successful recovery of both new data and old unrecovered data from prior transmissions. In addition to theoretically analyzing PEEC, the performance of the proposed scheme is extensively analyzed over real channel traces collected on 802.11b WLANs. We compare PEEC performance with the performance of the IEEE802.il standard ARQ protocol as well as contemporary protocols such as enhanced ARQ and the hybrid ARQ/FEC. Our analysis and experimental simulations show that PEEC outperforms all three competing protocols over a wide range of actual 802.11b WLAN collected traces. Finally, the design and implementation of PEEC using an adaptive low-density-parity-check (A-LDPC) decoder is presented.     

基于VB的主从机串行通信系统设计

串行通信是数据采集系统中最常用的通信手段之一。设计并研制了基于VB的LED大屏幕显示串行数据通信系统,具有编程灵活、控制通信对象容易的优点。通过8250的奇偶校验位与单片机的SM2位的配合,实现了PC机与多个单片机的串行数据通信。介绍了基于VB6.0进行串行通信的流程和编程,较好地解决了同时使用通信方式0与方式1时引起的RXD端口的冲突问题。实验证明,该设计简单、实用,提高了系统设计的效率。     

高效容错可逆的汉明码编码和检测电路

为了检验传输过程中数据的可靠性,设计了容错可逆的汉明码电路。提出了一种新型的可逆逻辑门（FVG）,它是一种四变量奇偶保持门能容错,并且完成了FVG门等价的量子实现。利用FVG 门和现有的容错可逆门,实现了汉明码编码电路和检测电路。以(7,4)汉明码设计为实例,根据量子代价和延迟对其进行性能评估,结果证明该电路比现有电路的性能提高10% ? 20%,仿真实验结果显示,电路逻辑结构正确,性能可靠。     

Design of VHDL-based totally self-checking finite-state machine anddata-path descriptions

This paper presents a complete methodology to design a totally self-checking (TSC) sequential system based on the generic architecture of finite-state machine and data path (FSMD), such as the one deriving from VHDL specifications. The control part of the system is designed to be self-checking by adopting a state assignment providing a constant Hamming distance between each pair of binary codes. The design of the data path is based on both classical methodologies (e.g., parity, Berger code) and ad hoc strategies (e.g., multiplexer cycle) suited for the specific circuit structure. Self-checking properties and costs are evaluated on a set of benchmark FSM's and on a number of VHDL circuits     

比特交织Turbo编码调制的8PSK符号映射

基于对Turbo编码器输出的系统比特和校验比特的不等错误保护(UEP),提出了一种新的比特交织Turbo编码调制(BITCM)的8PSK符号映射方案,即对于码率为1/3的Turbo码,校验比特映射到8PSK星座点中具有较好传输性能的比特位置上,而系统比特映射到较差传输性能的比特位置上。实现新映射方案的关键是比特交织器的设计。仿真结果表明,新的映射方案在AWGN信道下,误码率为10-3时,可获得大于0.2dB的信噪比增益,而这一增益的获得并没有牺牲频谱效率和增加系统的复杂性。