A very low-noise CMOS preamplifier for capacitive sensors

A CMOS preamplifier optimized for piezoelectric transducers is presented. The extensive use of CMOS-compatible lateral bipolar transistors (CLBTs) and careful layout leads to a very low noise along with good untrimmed DC and AC characteristics. These features make it competitive with bipolar and JFET realizations. In addition, long coaxial lines can be driven without significant alteration of performance using the two uncommitted on-chip buffers. This circuit was fabricated in a standard 3-μm p-well CMOS technology, opening perspectives to monolithic integration of data acquisition subsystems     

A low-noise CMOS preamplifier operating at 4.2 K

A low-noise CMOS readout preamplifier operating at liquid helium temperatures is described, In conjunction with magnetic field sensors applying SQUIDs (superconducting quantum interference devices) the preamplifier can be used to measure biomagnetic fields of human brain and heart noninvasively. The input of the folded cascode amplifier can be attached directly to a low impedance SQUID output. This way the commonly used discrete LC tank resonator circuit for impedance matching can be omitted. An equivalent noise voltage density of 0.3 nV/√Hz at 500 kHz has been measured. Despite the occurrence of the kink effect and other abnormalities in MOS transistor characteristics at 4.2 K, during the tests no abnormal operation has been observed. Such a preamplifier circuit is essential in simplifying the expensive shielding currently used in biomagnetic diagnosis systems     

Low power CMOS preamplifier for neural recording applications

A fully-differential bandpass CMOS (complementary metal oxide semiconductor) preamplifier for extracellular neural recording is presented. The capacitive-coupled and capacitive-feedback topology is adopted. The preamplifier has a midband gain of 20.4 dB and a DC gain of 0. The -3 dB upper cut-off frequency of the preamplifier is 6.7 kHz. The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands. It has an input-referred noise of 8.2 μVrms integrated from 0.15 Hz to 6.7 kHz for recording the local field potentials and the mixed neural spikes with a power dissipation of 23.1 μW from a 3.3 V supply. A bandgap reference circuitry is also designed for providing the biasing voltage and current. The 0.22 mm2 prototype chip, including the preamplifier and its biasing circuitry, is fabricated in the 0.35-μm N-well CMOS 2P4M process.     

用于神经记录的低功耗CMOS前置放大器

本文提出了一种应用于胞外神经记录的全差分带通CMOS前置放大器。这种放大器采用“容性耦合结合容性反馈”式拓扑结构。放大器具有20.4 dB的中带增益,且无直流增益。高频-3 dB截止频率为6.7 KHz,而低频-3 dB截止频率可根据不同频段场电位或动作电位的放大需求作出调整。在3.3 V供电下,放大器的通带设置为0.15 Hz到6.7 KHz（可同时记录本地场电位和神经元峰电位）,测得输入参考噪声为8.2 μVrms,功耗仅为23.1 μW。文中也设计了为前置放大器提供偏置电压和偏置电流的带隙参考电路。该原型芯片基于0.35-μm N阱CMOS 2P4M工艺设计与制造,包括前置放大器和偏置电路在内,有源区面积为0.22 mm2。     

CMOS charge-transfer preamplifier for offset-fluctuationcancellation in low-power A/D converters

We have developed a low-power, high-accuracy comparator composed of a dynamic latch and a CMOS charge transfer preamplifier (CT preamplifier). The CT preamplifier amplifies the input signal with no static power dissipation, and the operation is almost insensitive to the device parameter fluctuations. The low-power and high-accuracy comparator has been realized by combining the CT preamplifier with a dynamic latch circuit. The fluctuation in the offset voltage of a dynamic latch is reduced by a factor of the preamplifier gain. A 4-bit flash A/D converter circuit has been designed and fabricated by 0.6-μm CMOS process. Low differential nonlinearity of less than ±4 mV has been verified by the measurements on test circuits, showing 8-bit resolution capability. Very low power operation at 4.3 μW per MS/s per comparator has also been achieved     

一种带三级预放大的高速高精度CMOS比较器

比较器的设计对于A/D,D/A转换器的精度至关重要。为了满足12位高分辨率的A/D转换器的需要,设计了一种高精度CMOS比较器,采用三级差分比较和一级动态正反馈的Latch结构实现了高比较精度。论文对该比较器的电路结构,增益,带宽,输入失调消除原理和锁存时间常数进行了分析,并利用Hynix 0.5um CMOS工艺提供的器件模型进行了仿真,在20MHZ频率下,比较器的精度达到了400uV。测试结果显示,在16MHZ频率下,比较器的精度达到了600uV。在电源电压为5V时,功耗为78uw。芯片面积是210um *180um 。该比较器已经成功用于一种10MSPS 12位A/D转换器中。该器件还可以用于13位以下的其他A/D转换器电路。     

A high-speed and high-resolution CMOS comparator with three-stage preamplifier

The accuracy of A/D and D/A converters depend largely upon their inner comparators. To guarantee 12-bit high resolution for an A/D converter, a precise CMOS comparator consisting of a three-stage differential preamplifier together with a positive feedback latch is proposed. Circuit structure, gain, the principle of input offset voltage storage and latching time constant for the comparator will be analyzed and optimized in this article. With 0.5 μm HYNIX mixed signal technology, the simulation result shows that the circuit has a precision of 400 μV at 20 MHz. The test result shows that the circuit has a precision of 600 μV at 16 MHz, and dissipates only 78 μW of power dissipation at 5 V. The size of the chip is 210 × 180 μm2. The comparator has been successfully used in a 10 MSPS 12-bit A/D converter. The circuit can be also used in a less than 13-bit A/D converter.     

Wideband fully differential CMOS transimpedance preamplifier

A fully differential transimpedance amplifier has been designed and implemented in 0.18 /spl mu/m standard digital CMOS technology. The parallel feedback circuit topology is adopted to broaden the bandwidth. It can operate at 10 Gbit/s with the dynamic range from 25 /spl mu/A up to 2.5 mA. The power consumption is only 88 mW under 2 V supply voltage.     

A 0.8nV/√Hz CMOS preamplifier for IC-magneto-resistive readelements

The first CMOS preamplifier IC for magnetoresistive (MR) read elements for use in state-of-the-art tape drives is presented. The circuit's noise performance of 0.8 nV/√Hz includes noise contributions from both the amplifier and the integrated current source needed to bias the MR elements. It will be shown that a single-ended input architecture is highly attractive for MR preamps because it offers advantages such as lowest noise levels and substantially reduced power and area consumption. Also, a current-mode amplifier (CMA) has been developed to enhance the preamp's bandwidth, large-signal capability and PSRR. The quad preamp has been implemented in a 1.2 μm CMOS process and measures 4.5×4.24 mm²     

Low-noise low-power CMOS preamplifier for multisite extracellular neuronal recordings

This paper reports the design and the experimental results of a fully integrated, low-noise, low-power standard CMOS preamplifier circuit used to record the extracellular electrophysiological activity of in vitro biological neuronal cultures. Our goal is to use the preamplifier in a fully integrated, multi-channel, bi-directional neuro-electronic interface.Among others, two main requirements must be addressed when designing such kind of integrated recording systems: noise performance and very low frequency disturbance rejection. These two requirements need to be satisfied together with a small silicon area design, to be able to integrate a large number of recording channels (i.e. up to thousands) onto a single die. A prototype preamplifier circuit has been designed and implemented; in this paper we report the experimental results.While satisfying the above requirements, our circuit offers state-of-the-art smallest area occupation (0.13 mm²) and consumes 4.5 μW. Sub-threshold-biased lateral pnp transistors, used to implement very high resistance value integrated resistors, have been characterized to determine the resistance spread.The fabricated prototype, coupled with a commercial Micro-Electrode Array (MEA), has been successfully employed to record the extracellular electrophysiological spontaneous activity, both of muscular cardiac cells (cardiomyocytes) and of spinal cord neurons from murines.     

Low-voltage CMOS current-mode preamplifier: analysis and design

This paper presents the analysis and design of a new low-voltage fully balanced differential CMOS current-mode preamplifier for multi-Gbps series data communications. The minimum supply voltage of the proposed preamplifier is V/sub T/+V/sub sat/. The preamplifier employs a balanced configuration to achieve large bandwidth and to minimize the effect of bias-dependent mismatches. Two new bandwidth enhancement techniques, namely inductive series peaking and current feedback that are specific to low-voltage CMOS current-mode circuits, are introduced. The inductive series peaking technique utilizes the resonant characteristics of LC networks to achieve both a flat frequency response and maximum bandwidth. Current feedback extends bandwidth, lowers input impedance, and improves dynamic range. The employment of both techniques further increases the bandwidth, reduces the value of the series peaking inductor, and improves noise performance of the pre-amplifier at high frequencies. The preamplifier has been designed using a 0.18-/spl mu/m 6-metal 1-poly 1.8-V CMOS technology. Simulation results from Spectre with BSIM3.3 device models that account for device parasitics demonstrate that the preamplifier has a flat frequency response with 25.3 dB dc current gain or equivalently 60 dB/spl Omega/ transimpedance gain with a 50-/spl Omega/ load and bandwidth of 2.15 GHz.     

2.5 Gb/s CMOS preamplifier for low-cost fiber-optic receivers

This paper reports an optical preamplifier intended for low-cost fiber-optic receivers. The preamplifier is based on a resistive shunt-feedback topology, is power-optimized and employs two different frequency compensation techniques, phantom zeros and shunt-peaking. The circuit is designed in a 1.8 V 0.18 μm CMOS technology. Experimental results report a transresistance of 58 dBΩ and a bandwidth of 1.5 GHz, respectively. Eye diagrams obtained at 2.5 Gb/s show a total jitter of 18 ps and a bit error rate (BER) of 10⁻¹² when the input current amplitude (I_in) is equal to or higher than 8.5 μA. Higher bit rates up to 3 Gb/s also have been tested achieving a BER of 10⁻¹² when I_in ≥9.5 μA. The power consumption and die active area are 23.7 mW and 0.017 mm², respectively.     

Design and characterization of a CMOS preamplifier for quantum well infrared photodetectors

A preamplifier based on the source-follower direct injection (SFDI) topology for use in read-out integrated circuits (ROIC) of quantum-well infrared photodetectors focal plane arrays (QWIP-FPA) is demonstrated. The fabricated circuit shows high linearity, high integration time (from hundreds of μs to few ms) and low current detection capabilities for a wide range of input current (order of few pA). This performance was achieved through the use of a Poly1-Poly2 capacitor that, although presenting some penalties in area consumption, provides a higher linearity, lower leakage current and higher temperature stability than all others capacitors found in literature. Secondary effects such as charge injection and clock feed-through are observed in the experimental results and classical techniques, like the use of DUMMY transistor, are shown to be effective in minimizing these effects and maximizing the linearity of the response. The overall results indicate that this circuit architecture has a great potential to be practically integrated in larger QWIP-FPA ROICs, showing an improved performance relating to previous works in literature.     

Noise performance design of CMOS preamplifier for the active semiconductor neural probe

A systematic design guideline is presented for the noise performance of preamplifier for semiconductor neural probe which contains on-chip electronic circuitry. The overall signal-to-noise ratio (SNR) is calculated considering the spectral characteristics of the measured extracellular action potential and the low-frequency noise spectrum of the CMOS device from typical fabrication processes. An analytical expression of the output noise power is derived, and utilized to tailor the frequency response and device parameters which are controllable by the circuit designer. An analysis of the output SNR of a two-stage CMOS differential amplifier is given and the major factors which have significant effects on the SNR are determined. We showed that a little deviation of the input device sizes and transconductance ratio from the optimal values can significantly deteriorate the SNR. Quantitative information of the preamplifier circuit parameters for satisfactory noise performance is provided.     

硅基光电探测器前置放大电路的输入级CMOS实现

介绍前置电路对光电探测器性能的影响和给出一种适用于硅基光电探测器前置放大电路的输入级CMOS实现。     

A high-resolution technique for multidimensional NMR spectroscopy

A scheme for estimating frequencies and damping factors of multidimensional nuclear magnetic resonance (NMR) data is presented-multidimensional NMR data can be modeled as the sum of several multidimensional damped sinusoids. The estimated frequencies and damping factors of multidimensional NMR data play important roles in determining protein structures. The authors present a high-resolution subspace method for estimating the parameters of NMR data, Unlike other methods, this algorithm makes full use of the rank-deficiency and Hankel properties of the prediction matrix composed of NMR data. Hence, it can estimate the signal parameters under low signal-to-noise ratio (SNR) by using a few data points. The effectiveness of the new algorithm is confirmed by computer simulations and it is tested by experimental data     

带AGC的CMOS光接收机前置放大器的设计

设计了一种带有自动增益控制电路（AGC）的动态范围较宽的互补型金属氧化物半导体（CMOS）光接收机跨阻前置放大器（TIA）。该放大器的工作电压为3.3V。采用0．25μm CMOS工艺库仿真，结果表明：小信号输入时，跨阻增益可达76kΩ，单端输出信号在输入信号为0dBm时为281mV。     

Novel cell-AGC technique for burst-mode CMOS preamplifier with widedynamic range and high sensitivity for ATM-PON system

We propose a novel cell-AGC technique for an ATM-cell-based burst optical receiver on a 156-Mb/s subscriber system. The cell-AGC controls transimpedance gain according to the burst-cell power and enables reception of burst signals with low extinction ratio. In addition, to realize high sensitivity, we developed an amplifier that is stable under changes in ambient conditions and deviations of transistor characteristics on IC. By adopting these techniques in a CMOS preamplifier IC, the detectable power difference between burst cells was enlarged to more than 30 dB, and the minimum sensitivity was improved to less than -39.3 dBm. These performances show that our new IC fully satisfies the high-sensitivity specification of an ATM-PON system, and incorporating this IC in the system makes it more flexible and economical     

应用于10Gb/s光接收机的全差分CMOS跨阻前置电路设计

设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 mVpp的差分电压信号。该全差分前置放大电路采用0.18 m CMOS工艺进行设计,当光电二极管电容为250 fF时,该光接收机前置放大电路的跨阻增益为92 dB,-3 dB带宽为7.9 GHz,平均等效输入噪声电流谱密度约为23 pA/(0~8 GHz)。该电路采用电源电压为1.8 V时,跨阻放大器功耗为28 mW,限幅放大器功耗为80 mW,输出缓冲器功耗为40 mW,其芯片面积为800 m1 700 m。