Pulse frequency modulation based CMOS image sensor for subretinal stimulation

We have developed a CMOS image sensor based on pulse frequency modulation for subretinal implantation. The sensor chip forms part of the proposed intraocular retinal prosthesis system where data and power transmission are provided wirelessly from an extraocular unit. Image sensing and electrical stimulus are integrated onto the same chip. Image of sufficient resolution has been demonstrated using 16/spl times/16 pixels. Biphasic current stimulus pulses at above threshold levels of the human retina (500 /spl mu/A) at varying frame rates (4 Hz to 8 kHz) have been achieved. The implant chip was fabricated using standard CMOS technology.     

Low-power logic circuit and SRAM cell applications with silicon on depletion Layer CMOS (SODEL CMOS) technology

In this paper, the switching performance of Silicon on Depletion Layer CMOS (SODEL CMOS) is investigated with a view to realizing high-speed and low-power CMOS applications. Thanks to smaller parasitic capacitance, the propagation delay time (/spl tau//sub pd/) in SODEL CMOS has been improved by up to 25% compared to that of conventional bulk CMOS in five stacked nFET inverters at the same V/sub dd/. It is also confirmed that about 30% better power-delay product can be realized at the same /spl tau//sub pd/ with reduced V/sub dd/ in SODEL CMOS. In SRAM cell applications, SODEL CMOS shows high Static Noise Margin (SNM) of /spl sim/95 mV at V/sub dd/=0.6 V. Smaller bitline delay is expected and confirmed in SODEL CMOS SRAM by SPICE simulations. Latch-up immunity for /spl alpha/-particle irradiation in SODEL CMOS was also found to be comparable to that of conventional bulk CMOS. Therefore, SODEL CMOS device and circuit technology is expected to provide a better solution for low-power system-on-a-chip (SoC).     

1.0-/spl mu/m n-Well CMOS/Bipolar Technology

High-performance 1.0-/spl mu/m n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-/spl mu/m CMOS with a new "hot carrier resistant" seIf-defined Polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors. it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n/sup +/-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n/sup +/-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.     

SOS/CMOS as a High-Performance LSI Device

To realize a high-performance LSI, the devices used should satisfy the following requirements: 1) high-speed operation, 2) low power consumption, 3) easy designability, and 4) high integration capability. SOS/CMOS has been examined both experimentally and theoretically for these aspects. Ideal CMOS operation with /spl tau//sub pd/ ~ 100 ps with 0.1-pJ energy required to switch an inverter is obtained. 1-GHz operation is confirmed on dynamic 1/16 frequency dividers with 1.0-/spl mu/m effective channel-length devices. Using the same device, a maximum multiplying time, /spl tau//sub mul/ ~ 25 ns at 5 V with 15-mW average power at 10/sup 7/ multiplications/s is obtained on a 4 X 4 parallel multiplier. The above result agrees with circuit simulation predictions without including stray capacitance associated with the wiring. The same simulation predicts rmul ~ 60 ns with a maximum power dissipation of 200 mW at 16-MHz operation for a 16 X 16 parallel multiplier. This prediction is also confirmed experimentally. These facts indicate good designability of SOS/CMOS. For larger scale integration capability estimation, power dissipation and wiring delay were examined theoretically for bulk NMOS, bulk CMOS, and SOS/CMOS. The results indicate that for smaller scale integration, bulk NMOS and SOS/CMOS operate faster than bulk CMOS. However, for larger scale integration, SOS/CMOS operates faster than bulk CMOS which, in turn, operates faster than bulk NMOS.     

Test structures to measure the heat capacity of CMOS layersandwiches

We report novel thermal characterization microstructures to measure the heat capacity of CMOS thin film sandwiches. This parameter is relevant, e.g., for the dynamic response of thermal CMOS microtransducers and for the thermal management of integrated circuits. The test structures were fabricated using a commercial 2-μm CMOS process, followed by maskless micromachining. The propagation of heat waves in the structures is monitored, which provides the thermal conductivity and heat capacity of CMOS thin film sandwiches. At 300 K, volumetric heat capacities of (1.71±0.12)×10⁶ Jm ^-3K^-1 and (2.41±1.88)×10⁶ Jm^-3K^-1 were obtained for the sandwich of CMOS dielectrics and for the lower CMOS metal, respectively. These values do not deviate significantly from available bulk data of such materials     

SOS/CMOS as a high-performance LSI device

To realize a high-performance LSI, the devices used should satisfy the following requirements: 1) high-speed operation, 2) low power consumption, 3) easy designability, and 4) high integration capability. SOS/CMOS has been examined both experimentally and theoretically for these aspects. Ideal CMOS operation withtau_{pd} sim 100ps with 0.1-pJ energy required to switch an inverter is obtained. 1-GHz operation is confirmed on dynamic 1/16 frequency dividers with 1.0-µm effective channel-length devices. Using the same device, a maximum multiplying time,tau_{mul} sim 25ns at 5 V with 15-mW average power at 10⁷multiplications/s is obtained on a 4 × 4 parallel multiplier. The above result agrees with circuit simulation predictions without including stray capacitance associated with the wiring. The same simulation predictstau_{mul} sim 60ns with a maximum power dissipation of 200 mW at 16-MHz operation for a 16 × 16 parallel multiplier. This prediction is also confirmed experimentally. These facts indicate good designability of SOS/CMOS. For larger scale integration capability estimation, power dissipation and wiring delay were examined theoretically for bulk NMOS, bulk CMOS, and SOS/CMOS. The results indicate that for smaller scale integration, bulk NMOS and SOS/CMOS operate faster than bulk CMOS. However, for larger scale integration, SOS/CMOS operates faster than bulk CMOS which, in turn, operates faster than bulk NMOS.     

NORA: a racefree dynamic CMOS technique for pipelined logic structures

Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks /spl phi/ and /spl phi/~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C/SUP 2/MOS logic functions. Static CMOS functions can also be employed. Logic composition rules to mix dynamic CMOS, C/SUP 2/MOS, and conventional CMOS will be presented. Different from Domino technique, logic inversion is also provided. This means higher logic flexibility and less transistors for the same function. The effects of charge redistribution, noise margin, and leakage in the dynamic CMOS blocks are also analyzed. Experimental results show the feasibility of the principles discussed.     

Design of a New High Speed Amplifier Circuit for the Analog Subsystems

A high speed CMOS amplifier circuit with a new architecture especially suited for analog subsystems and a simple high speed CMOS comparator utilizing the proposed CMOS amplifier circuit are presented. The proposed circuit is simulated using 0.35 m process parameters. The configuration results in several performance improvements over a typical CMOS differential to single ended amplifier. Design details and simulation results show that the newly designed CMOS amplifier circuit and the high speed CMOS comparator are applicable to high speed analog subsystems, especially the flash A/D converter.     

Optical I/O Technology for Tera-Scale Computing

This paper describes both a near term and a long term optical interconnect solution, the first based on a packaging architecture and the second based on a monolithic photonic CMOS architecture. The packaging-based optical I/O architecture implemented with 90 nm CMOS transceiver circuits, 1 × 12 VCSEL/detector arrays and polymer waveguides achieves 10 Gb/s/channel at 11 pJ/b. A simple TX pre-emphasis technique enables a potential 18 Gb/s at 9.6 pJ/b link efficiency. Analysis predicts this architecture to reach less than 1 pJ/b at the 16 nm CMOS technology node. A photonic CMOS process enables higher bandwidth and lower energy-per-bit for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides and polycrystalline germanium (Ge) detectors into a CMOS logic process. Experimental results for the photonic CMOS ring resonator modulators and Ge detectors demonstrate performance above 20 Gb/s and analysis predicts that photonic CMOS will eventually enable energy efficiency better than 0.3 pJ/b with 16 nm CMOS. Optical interconnect technologies such as these using multi-lane communication or wavelength division multiplexing have the potential to achieve TB/s interconnect and enable platforms suitable for the tera-scale computing era.     

CMOS/SOS器件长期可靠性试验

用本所研制的CMOS/SOS器件作了两项试验,即CMOS/SOS4012长期可靠性试验和不同版图设计、不同器件工艺研制的CMOS/SOS长期可靠性对比试验。试验结果表明:不同版图设计和器件工艺对CMOS/SOS器件可靠性有较大的影响;改进了版图和器件工艺研制的CMOS/SOS器件达到了较高的可靠性;不同栅介质结构的CMOS/SOS器件在高温加电运行中,阈值电压的变化是不同的。     

纳米技术将推动IC产业继续前进

在未来10～15年内有两条主流将引导IC产业的发展:一条是延续摩尔定律、纳米SiCMOS技术,以提高芯片的速度和频率;另一条是超越摩尔定律。后者分成三个支流:双核和多核处理器、纳米SiCMOS技术,以提高芯片性能;在单个封装内集成整个系统,纳米SiCMOS技术,以提高芯片容量和功能;采用纳米技术研发纳米CMOS器件以外的纳米器件,如碳纳米管、共振隧穿器件等,以突破SiCMOS技术为主。     

Prediction of CMOS APS design enabling maximum photoresponse for scalable CMOS technologies

This brief represents the CMOS active pixel sensor (APS) photoresponse model use for maximum pixel photosignal prediction in scalable CMOS technologies. We have proposed a simple approximation determining the technology-scaling effect on the overall device photoresponse. Based on the above approximation and the data obtained from the CMOS 0.5 /spl mu/m process thorough investigation we have theoretically predicted, designed, measured and compared the optimal (in the output photosignal sense) pixel in a more advanced, CMOS 0.35 /spl mu/m technology. Comparison of both, our theoretically predicted and modeled results and the results obtained from the measurements of an actual pixel array gives excellent agreement. It verifies the presented scaling-effect approximation and validates the usefulness of our model for design optimization in scalable CMOS technologies.     

Asynchronous gate-diffusion-input (GDI) circuits

Novel gate-diffusion input (GDI) circuits are applied to asynchronous design. A variety of GDI implementations are compared with typical CMOS asynchronous circuits. Dynamic GDI state holding elements are 2/spl times/ smaller than CMOS C-elements, 30% faster, and consume 85% less power, but certain CMOS elements are preferred when static storage is called for. A GDI bundled controller outperforms CMOS on all accounts, having 1/3 the delay and requiring less than half the area while consuming the same power. A combination CMOS-GDI circuit provides the optimal solution for qDI combinational logic, saving 1/3 the power, half the area, and 10% in delay relative to a CMOS implementation. GDI circuits also provide some measure of enhanced hazard tolerance.     

Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS

This paper presents low-voltage circuit topologies for 40-Gb/s communications in 90-nm and 65-nm CMOS. A retiming flip-flop implemented in two different 90-nm CMOS technologies employs a MOS-CML Master-Slave latch topology with only two vertically stacked transistors. Operation at 40 Gb/s is achieved by a combination of low and high-V_T MOSFETs in the latch. Full-rate retiming with jitter reduction is demonstrated up to 40 Gb/s. Low-power broadband amplifiers based on resistor-inductor transimpedance feedback are realized in 90-nm and 65-nm CMOS to investigate the portability of high-speed building blocks between technology nodes. Experiments show that the transimpedance amplifier based on the CMOS inverter can reach 40-Gb/s operation with a record power consumption of 0.15 mW/Gb/s. A comparison between CMOS technologies underlines the importance of General Purpose rather than Low Power processes for high-speed digital design.     

A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOItechnology

A 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22-μm partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MHz CMOS8S SOI processor, the adder compensates for floating body effects in SOI devices which cause history effects, bipolar currents, and lower noise margins on dynamic circuits     

1.0-µm n-well CMOS/bipolar technology

High-performance 1.0-µm n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-µm CMOS with a new "hot carrier resistant" self-defined polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors, it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n⁺-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n⁺-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.     

A miniature 25-GHz 9-dB CMOS cascaded single-stage distributed amplifier

A 25-GHz complementary metal oxide semiconductor (CMOS) cascaded single-stage distributed amplifier (CSSDA) using standard 0.18-/spl mu/m CMOS technology is presented in this letter. It demonstrates the highest gain-bandwidth product (GBP) with smallest chip area reported for a fully-integrated CMOS wideband amplifier using a standard Si-based integrated circuit process. The chip size including testing pads is only 0.36mm/sup 2/, and the ratio of GBP to chip size achieves 552GHz/mm/sup 2/. This circuit is the first CSSDA realized in CMOS technology, and represents state-of-the-art performances.     

CMOS CCII– based on modified dual output-OTA for high frequency applications

A negative CMOS second generation current conveyor (CMOS CCII–) based on modified dual output CMOS folded cascode operational transconductance amplifier (CMOS DO-OTA) is presented. The proposed folded cascode CMOS DO-OTA with attractive features for high frequency operation such as high output impedance, wide bandwidth, high slew rate, with low power consumption is used in the realisation. The proposed CMOS DO-OTA and CMOS CCII– with high performance parameters can be used in many high frequency applications. The proposed CMOS CCII– achieves 1.37 GHz (?3 dB BW), 1.8 ns settling time, 48 V/μs slew rate, and low power consumption around 3.25 mW for ±2.5 V supply. P-Spice simulation results are included for 0.5 μm MIETEC CMOS technology.     

Simple and quick turnaround time fabrication process for deepsubmicrometer CMOS generation

Process simplification and turnaround time reduction for deep submicrometer CMOS fabrication are discussed. Process step analysis is carried out for standard 1Poly/1Metal CMOS structure, and consequently, both isolation and gate formation processes are extracted as items for process simplification. A combination of shallow trench isolation with retrograde well structure and single mask step well/gate doping technique is proposed for deep submicrometer CMOS fabrication. This simplified CMOS process can achieve a reduction of five mask steps and eliminates both well drive-in annealing and field oxidation without performance deterioration. As a result, a 10% process step reduction and a 20% manufacturing turnaround time reduction have been realized in comparison to the standard 1Poly/1Metal CMOS process with LOCOS isolation     

Energy-efficient skewed static logic with dual Vt: design and synthesis

In this paper, we describe skewed static logic (S/sup 2/L) with topology-dependent dual Vt which exhibits an energy-efficient operation. S/sup 2/L consumes less dynamic and static power compared to monotonic static (MS) CMOS. Speed degradation of S/sup 2/L, if any, can be offset by an accelerator circuit. We have designed NAND-NOR gate chains using 0.18-/spl mu/m CMOS technology and verified that S/sup 2/L reduces energy-delay product over MS CMOS by 27%-50%. We have also designed 32-b carry-lookahead adders and verified that S/sup 2/L with dual Vt reduces delay by 43% and energy-delay product by 31% for 1-V power supply over conventional CMOS circuit. Synthesis algorithm for S/sup 2/L is developed and the experimental results show S/sup 2/L consumes 23% less power than MS CMOS with minor increase in delay.