基于Matlab与DSP的FIR数字滤波器软硬件实现

给出了利用Matlab与DSP技术相结合的语音信号FIR滤波的软件、硬件实现方法。分析了FIR滤波器的特性，给出了FIR滤波器的Matlab仿真，介绍了在DSP硬件系统中的实现过程，实现了对语音信号的FIR滤波处理。     

DVB-S信道处理系统中基带脉冲整形插值滤波器的FPGA设计

在简要分析卫星数字视频广播DVB-S系统发送端信道处理系统设计理论的基础上,针对其中的基带脉冲整形插值滤波器,通过其DSP软件实现方法和FPGA硬件实现方法的详细比较,最终选用FPGA硬件方法来实现内插的有限冲击响应(FIR)数字滤波器.通过MATLAB仿真为该插值滤波器建立了完整的数学模型,同时结合系统的要求及协议标准,提出了该插值滤波器的FPGA 优化设计实现方法.     

一种基于SCA的DSP软件无线电框架实现

在通信行业采甩SDR已是大势所趋,无论是民用还是军用领域都广泛采用这一概念。但是还没有一个框架能将DSP纳入到SDR系统中。为了提高SDR系统的性能,同时保证波形软件的可移植性和通用性,基于软件通信体系结构在DSP上设计实现了软件无线电框架。规范了在软件无线电产品中使用DSP的方法,提高了DSP波形组件的模块化程度及在不同平台上的可移植性和可重用性,使基于SCA的SDR的性能得以提高。     

一种低复杂度的基站信道处理器实现方法

本文提出了一种降低基站信道处理器计算复杂度的方法.通过利用插值二阶多项式滤波器对IDFT滤波器组进行整形处理,IDFT滤波器组可以直接用作基站信道处理器.实现此信道处理器的复杂度更低,因此适合在以软件无线电技术实现的基站中采用.理论分析和仿真结果表明,在保持系统性能基本不变的条件下,该方法在实现信道滤波器方面比K.C.Zangi等^[1]提出的开放滤波器组(OFB)信道处理器提高效率17%.     

软件无线接收数字前端的实现

基于软件无线电(SDR)基本思想,提出数字前端概念,对数字前端的组成、功能和基于CORDIC算法的数字下变频、多速率滤波等关键技术进行了介绍。设计了一种软件无线电接收系统,实验表明该设计方案扩展性和移植性好,技术性能达到要求。仿照GSM接收系统技术参数,设计了多速率滤波器,仿真表明,数字前端采用多速率滤波器,能节省成本。对SDR的发展进行了展望。     

基于FPGA的FIR数字滤波器设计与实现

简要介绍了FIR数字滤波器的结构特点和基本原理,提出基于FPGA和DSP Builder的FIR数字滤波器的基本设计流程和实现方案。在Matlab/Simulink环境下,采用DSP Builder模块搭建FIR模型,根据FDATool工具对FIR滤波器进行了设计,然后进行系统级仿真和ModelSim功能仿真,其仿真结果表明其数字滤波器的滤波效果良好。通过SignalCompiler把模型转换成VHDL语言加入到FPGA的硬件设计中,从QuartusⅡ软件中的虚拟逻辑分析工具SignalTapⅡ中得到数字滤波器实时的结果波形图,结果符合预期。     

基于DSP Builder的数字下变频技术

数字下变频(DDC)是软件无线电的核心技术之一,其通过下变频和抽取可将高频数据流信号变成易于后端数字信号处理器(DSP)实时处理的低频低数据流信号。文中讨论数字下变频技术的实现原理,从基于FPGA技术的DSP应用出发,基于DSP Builder软件进行了数字下变频技术研究。并通过对自定义数字信号进行正交混频下变频和两级(CIC滤波器、FIR滤波器)抽取实验,证明了此技术的简单高效和较高实用价值。     

FIR滤波器的DSP实现

介绍了FIR滤波器的基本结构及设计方法,结合实例,给定滤波器的数字指标。利用FDATool来确定FIR滤波器抽头系数。基于DSP平台,采用MATLB产生待滤波输入信号导入到用C语言实现的FIR低通滤波器中,并且在CCS上仿真,对仿真结果与理论值进行比较。波形仿真结果和理论值相吻和表明设计的系统是正确、稳定的。不同的应用场合,FIR滤波器要求有不同性能,只要修改本设计中滤波器的系数,就可以实现性能不同的FIR滤波器。     

软件无线电中的信道化技术研究

软件无线电通信利用多频段和多模式的无线通信进行互连互通,具有极大的灵活性和适应性。文章围绕无线电接收机的信道化技术、带通采样理论等展开论述,利用CIC,HBF和FIR级联设计下变频抽取系统的实际方案作为论据,对基于软件无线电技术的信道化技术等展开论述,探讨软件无线电多速率信号等处理技术要点。     

基于DSP的数字正交解调器的设计与实现

随着软件无线电技术的迅速发展,数字正交解调技术也越来越成熟.介绍了一种基于希尔伯特带通滤波器的正交解调的数字实现方案,并在TI公司的DSP集成开发环境CCS软件中进行软件仿真并验证了该方案的可行性;最后在以DSP、FPGA等芯片为主的硬件平台上进行硬件仿真测试,同样验证了该方案的正确性与准确性.     

A Reconfigurable Channel Filter for Software Defined Radio Using RNS

This paper presents a high-speed FIR channel filter using residue number system (RNS) whose frequency response can be reconfigured to adapt to a multitude of channel filtering specifications of a multi-standard software defined radio (SDR) receiver. The channel filters in the channelizer of an SDR extract multiple narrowband channels corresponding to different communication standards from the wideband input signal. The proposed architecture has been synthesized on TSMC 0.18 μm CMOS standard cell technology. Synthesis result shows that the proposed reconfigurable FIR channel filter, for a Digital Advanced Mobile Phone Systems (D-AMPS) example, offers speed improvement of 42% and AT complexity reduction of 26% over existing reconfigurable FIR method.     

Low power and high-speed implementation of fir filters for software defined radio receivers

The most computationally intensive part of the wideband receiver of a software defined radio (SDR) is the intermediate frequency (IF) processing block. Digital filtering is the main task in IF processing. The computational complexity of finite impulse response (FIR) filters used in the IF processing block is dominated by the number of adders (subtracters) employed in the multipliers. This paper presents a method to implement FIR filters for SDR receivers using minimum number of adders. We use an arithmetic scheme, known as pseudo floating-point (PFP) representation to encode the filter coefficients. By employing a span reduction technique, we show that the filter coefficients can be coded using considerably fewer bits than conventional 24-bit and 16-bit fixed-point filters. Simulation results show that the magnitude responses of the filters coded in PFP meet the attenuation requirements of wireless communication standard specifications. The proposed method offers average reductions of 40% in the number of adders and 80% in the number of full adders needed for the coefficient multipliers over conventional FIR filter implementation methods     

Design of transmit FIR filters for FDM data transmission systems

The design of transmit finite-impulse response (FIR) filters with few coefficients in frequency division multiplexing data transmission systems is considered. In these systems, quality objectives are imposed for transmission over channels affected by additive white Gaussian noise (AWGN) and over channels affected by AWGN plus adjacent channel interference (ACI). The goal of this letter is: given that an adaptive receive filter, possibly cooperating with an adaptive decision feedback equalizer, is used for the AWGN channel and for the AWGN plus ACI channel, what is the best fixed FIR transmit filter to use for both channel cases? This goal is achieved by optimizing the compromise between the performance of the system on the two mentioned channels. Also, the advantages of the proposed design over a rival method based on a fixed receive filter are demonstrated.     

A Low Complexity Reconfigurable Multi-stage Channel Filter Architecture for Resource-Constrained Software Radio Handsets

Software defined radio (SDR) is emerging as a powerful platform for future generation cellular systems, due to its capability to operate conforming to multiple mobile radio standards. Channelizer in an SDR operates at the highest sampling rate and hence a low complexity design is needed for the most computationally intensive part of the SDR receiver. The channel filters in the channelizer extracts radio channels of varying bandwidths, corresponding to various communication standards from the wideband input signal. An architecture for implementing low complexity, low power and reconfigurable channel filter for the SDR mobile handsets, based on multi-stage frequency response masking (FRM) is proposed in this paper. The proposed architecture is unique in a way that it is able to effectively exploit the redundancy in multi-stage realization by utilizing the common masking filters and also capable of extracting varying bandwidth channels. Design examples show that the proposed architecture offers 47.5% complexity reduction and 18.1% power reduction over single-stage FRM approach.     

A direct approach to H2 optimal deconvolution ofperiodic digital channels

This paper studies the H₂ optimal deconvolution problem for periodic finite impulse response (FIR) and infinite impulse response (IIR) channels. It shows that the H₂ norm of a periodic filter can be directly quantified in terms of periodic system matrices and linear matrix inequalities (LMIs) without resorting to the commonly used lifting technique. The optimal signal reconstruction problem is then formulated as an optimization problem subject to a set of matrix inequality constraints. Under this framework, the optimization of both the FIR and IIR periodic deconvolution filters can be made convex, solved using the interior point method, and computed by using the Matlab LMI Toolbox. The robust deconvolution problem for periodic FIR and IIR channels with polytopic uncertainties are further formulated and solved, also by convex optimization and the LMIs. Compared with the lifting approach to the design of periodic filters, the proposed approach is simpler yet more powerful in dealing with multiobjective deconvolution problems and channel uncertainties, especially for IIR deconvolution filter design. The obtained solutions are applied to the design of an optimal filterbank yielding satisfactory performance     

Filter design for MIMO sampling and reconstruction

We address the problem of finite impulse response (FIR) filter design for uniform multiple-input multiple-output (MIMO) sampling. This scheme encompasses Papoulis' generalized sampling and several nonuniform sampling schemes as special cases. The input signals are modeled as either continuous-time or discrete-time multiband input signals, with different band structures. We present conditions on the channel and the sampling rate that allow perfect inversion of the channel. Additionally, we provide a stronger set of conditions under which the reconstruction filters can be chosen to have frequency responses that are continuous. We also provide conditions for the existence of FIR perfect reconstruction filters, and when such do not exist, we address the optimal approximation of the ideal filters using FIR filters and a minmax l/sub 2/ end-to-end distortion criterion. The design problem is then reduced to a standard semi-infinite linear program. An example design of FIR reconstruction filters is given.     

ISI-free FIR filterbank transceivers for frequency-selectivechannels

Discrete multitone modulation transceivers (DMTs) have been shown to be very useful for data transmission over frequency-selective channels. The DMT scheme is realized by a transceiver that divides the channel into subbands. The efficiency of the scheme depends on the frequency selectivity of the transmitting and receiving filters. The receiving filters with good stopband attenuation are also desired for combating narrowband noise. The filterbank transceiver or discrete wavelet multitone (DWMT) system has been proposed as an implementation of the DMT transceiver that has better frequency band separation, but usually, intersymbol interference (ISI) cannot be completely cancelled in these filterbank transceivers, and additional equalization is required. We show how to use over interpolated filterbanks to design ISI-free FIR transceivers. A finite impulse response (FIR) transceiver with good frequency selectivity can be designed, as demonstrated by the design examples     

基于FPGA的FIR滤波器设计

数字滤波器在数字信号处理中占有很重要的地位,该文介绍了FIR滤波器的两种实现算法：乘累加算法和优化的分布式算法,其中分布式算法作为优化算法进行研究。其次,根据FIR滤波器理论,采用线性相位结构优化滤波器的设计。并给出了FIR滤波器的模块划分和FIR滤波器的主要模块的实现,最后对FIR滤波器进行了系统仿真和验证。     

Modified Metaheuristic Algorithms for the Optimal Design of Multiplier-Less Non-uniform Channel Filters

Reconfigurable non-uniform channel filters are now being widely used in software define radio (SDR). The hardware implementation of these filters requires low complexity, low chip area and low power consumption. The frequency response masking (FRM) approach is proved to be a good candidate for the realization of a sharp digital finite impulse response (FIR) filter with low complexity. To reduce the complexity further, this paper gives an optimal design method which makes the channel filters totally multiplier-less. This is done in two steps. The channel filters are designed using the FRM approach with continuous filter coefficients. To obtain multiplier-less design, these filter coefficients are converted to finite-precision coefficients using signed power of two (SPT) space and the filter coefficients are synthesized in the canonic signed-digit (CSD) format. But this may lead to degradation of the filter performance. Hence the filter coefficients synthesis in the CSD format is formulated as an optimization problem. Several meta-heuristic algorithms like Differential Evolution (DE), Artificial Bee Colony (ABC), Harmony Search Algorithm (HSA) and Gravitational Search Algorithm (GSA) are modified and deployed and the best one is selected.     

Low-Area/Power Parallel FIR Digital Filter Implementations

This paper presents a novel approach for implementing area-efficient parallel (block) finite impulse response (FIR) filters that require less hardware than traditional block FIR filter implementations. Parallel processing is a powerful technique because it can be used to increase the throughput of a FIR filter or reduce the power consumption of a FIR filter. However, a traditional block filter implementation causes a linear increase in the hardware cost (area) by a factor of L, the block size. In many design situations, this large hardware penalty cannot be tolerated. Therefore, it is important to design parallel FIR filter structures that require less area than traditional block FIR filtering structures. In this paper, we propose a method to design parallel FIR filter structures that require a less-than-linear increase in the hardware cost. A novel adjacent coefficient sharing based sub-structure sharing technique is introduced and used to reduce the hardware cost of parallel FIR filters. A novel coefficient quantization technique, referred to as a scalable maximum absolute difference (MAD) quantization process, is introduced and used to produce quantized filters with good spectrum characteristics. By using a combination of fast FIR filtering algorithms, a novel coefficient quantization process and area reduction techniques, we show that parallel FIR filters can be implemented with up to a 45% reduction in hardware compared to traditional parallel FIR filters.