A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth

This paper presents the design and experimental results of a continuous-time /spl Sigma//spl Delta/ modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time /spl Sigma//spl Delta/ modulators is solved by our proposed architecture. A prototype third-order continuous-time /spl Sigma//spl Delta/ modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 /spl times/ 2.4 mm/sup 2/. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.     

A cascaded continuous-time /spl Sigma//spl Delta/ Modulator with 67-dB dynamic range in 10-MHz bandwidth

This paper presents the design of a 2-2 cascaded continuous-time sigma-delta modulator. The cascaded modulator comprises two stages with second-order continuous-time resonator loopfilters, 4-bit quantizers, and feedback digital-to-analog converters. The digital noise cancellation filter design is determined using continuous-time to discrete-time transformation of the sigma-delta loopfilter transfer functions. The required matching between the analog and digital filter coefficients is achieved by means of simple digital calibration of the noise cancellation filter. Measurement results of a 0.18-/spl mu/m CMOS prototype chip demonstrate 67-dB dynamic range in a 10-MHz bandwidth at 8 times oversampling for a single continuous-time cascaded modulator. Two cascaded modulators in quadrature configuration provide 20-MHz aggregate bandwidth. Measured anti-alias suppression is over 50 dB for input signals in the band from 150 to 170 MHz around the sampling frequency of 160 MHz.     

Silicon thermooptical micromodulator with 700-kHz -3-dB bandwidth

A silicon Fabry-Perot waveguide modulator, operating at the fiber optic communication wavelengths of 1.3 and 1.55 μm, has been entirely fabricated using microelectronic techniques. The planar optical cavity has been defined by plasma etching and has a length of 100 μm. The device, based on the thermooptic effect, is electrically driven and exhibits a maximum modulation depths of 60%. The measured -3 dB bandwidth is 700 kHz, which is by far the best result ever reported, to our knowledge, for thermooptic effect based modulators     

A 5-MHz bandwidth 78.1-dB SNDR 2-2 MASH delta-sigma modulator

ABSTRACT

This paper presents a 4-bit, 2–2 multi-stage noise shaping (MASH) delta-sigma modulator (DSM) fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The DSM was designed using a cascade-of-integrators with a feedforward (CIFF) structure. The first integrator was designed to reduce the loading effect of the system’s front-end circuit using a switched-resistor integrator instead of the conventional switched-capacitor method. The CIFF structure requires an active adder, which is generally implemented with a high-bandwidth high-swing amplifier. In this paper, the active adder is eliminated and an adder-less integrator is implemented in the MASH DSM. The DSM prototype has an over-sampling ratio (OSR) of 16 and a 160 MHz sampling frequency. The prototype’s measured signal-to-noise ratio (SNR) is 82.4 dB and the signal-to-noise-plus-distortion ratio (SNDR) is 78.1 dB for a signal bandwidth of 5 MHz. The measured total power consumption is 26 mW at a 1.8 V supply voltage, and the chip core size is 0.67 mm². The energy required per conversion step is 0.4 pJ/conv.     

A 100-MHz bandpass sigma-delta modulator with a 75-dB dynamic range for IF receivers

A fourth-order switched-capacitor bandpassΣ△modulator is presented for digital intermediatefrequency (IF) receivers.The circuit operates at a sampling frequency of 100 MHz.The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators.The modulator is implemented in a 0.13-μm standard CMOS process.The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB,respectively,over a bandwidth of 200 kHz centered at 25 MHz,and the power dissipation is 8.2 mW at a 1.2 V supply.     

一种适用于中频接收机的具有75dB动态范围的100MHz带通$\Sigma \Delta$调制器

本文介绍了一款适用于中频接收机的四阶开关电容带通$\Sigma \Delta$调制器,采样频率为100MHz。为优化谐振器的性能,文中提出了考虑运算放大器非理想特性后谐振器的传输函数。本文设计的调制器采用0.13-um标准CMOS工艺,在25MHz附近200KHz信号带宽内测得的SNDR和DR分别为68dB和75dB。调制器工作在1.2V电源电压下,总功耗为8.2mW。     

A 50-MHz dB-linear programmable-gain amplifier with 98-dB dynamic range and 2-dB gain steps for 3 V power supply

A programmable-gain amplifier (PGA) circuit introduced in this paper has a dynamic gain range of 98 dB with 2 dB gain steps and is controlled by 6-bit gain control bits for a 3 V power supply. It has been fabricated in a 0.5 /spl mu/m 15 GHz f/sub T/ Si BiCMOS process and draws 13 mA. The active die area taken up by the circuit is 400 /spl mu/m /spl times/ 1170 /spl mu/m. A noise figure (NF) of 4.9 dB was measured at the maximum gain setting. In addition, an analysis of the bias current generation to provide dB-linear gain control is presented.     

A 64-MHz clock-rate /spl Sigma//spl Delta/ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency

A 64-MHz clock rate sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter (ADC) with -105-dB intermodulation distortion (IMD) at a 1.5-MHz signal frequency is reported. A linear replica bridge sampling network enables the ADC to achieve high linearity for high signal frequencies. Operating at an oversampling ratio of 29, a 2-1-1 cascade with a 2-b quantizer in the last stage reduces the quantization noise level well below that of the thermal noise. The measured signal-to-noise and distortion ratio (SNDR) in 1.1-MHz bandwidth is 88 dB, and the spurious-free-dynamic-range (SFDR) is 106 dB. The modulator and reference buffers occupy a 2.6-mm/sup 2/ die area and have been implemented with thick oxide devices, with minimum channel length of 0.35 /spl mu/m, in a dual-gate 0.18-/spl mu/m 1.8-V single-poly five-metal (SP5M) digital CMOS process. The power consumed by the ADC is 230 mW, including the decimation filters.     

A variable gain amplifier with 50-dB control range for 900-MHz applications

A variable gain amplifier for 900-MHz applications has been designed and fabricated in a BiCMOS process with f/sub T/ = 24 GHz. The amplifier has linear-in-dB gain control with a 50-dB control range. The maximum gain is 28 dB and the third-order output intercept point (OIP3) is 13.7 dBm. The gain is achieved in one gain stage with a cascoded output. The amplifier bias network and the gain-control circuitry are temperature compensated for temperature-independent gain at any gain setting. The bias network also uses a feedback loop to cancel out undesired low frequencies present at the radio-frequency input. The maximum output power is +10 dBm and the output 1-dB compression point is +8.7 dBm. Active chip area is 0.1 mm/sup 2/. The amplifier is packaged in a SOT-363 and consumes 30 mA from a 2.8-V supply.     

A 3.3-mW /spl Sigma//spl Delta/ modulator for UMTS in 0.18-/spl mu/m CMOS with 70-dB dynamic range in 2-MHz bandwidth

A quadrature fourth-order, continuous-time, /spl Sigma//spl Delta/ modulator with 1.5-b quantizer and feedback digital-to-analog converter (DAC) for a universal mobile telecommunication system (UMTS) receiver chain is presented. It achieves a dynamic range of 70 dB in a 2-MHz bandwidth and the total harmonic distortion is -74 dB at full-scale input. When used in an integrated receiver for UMTS, the dynamic range of the modulator substantially reduces the need for analog automatic gain control and its tolerance of large out-of-band interference also permits the use of only first-order prefiltering. An IC including an I and Q /spl Sigma//spl Delta/ modulator, phase-locked loop, oscillator, and bandgap dissipates 11.5 mW at 1.8 V. The active area is 0.41 mm/sup 2/ in a 0.18-/spl mu/m 1-poly 5-metal CMOS technology.     

A 3.3-V CMOS 10.7-MHz sixth-order bandpass ΣΔ modulatorwith 74-dB dynamic range

A 3.3-V bandpass ΣΔ modulator for IF sampling at 10.7 MHz in digital radio applications has been developed. The modulator presents a sixth-order single-loop architecture and features a 74-dB dynamic range in a 2OO-kHz signal bandwidth (FM signal), while for a 9-kHz signal bandwidth (AM signal) the dynamic range is 88 dB. The modulator has been integrated in a standard 0.35-μm CMOS technology using switched-capacitor technique and consumes 76 mW from a single 3.3V supply     

A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution

A wide-bandwidth continuous-time sigma-delta ADC is implemented in a 0.13-/spl mu/m CMOS. The circuit is targeted for wide-bandwidth applications such as video or wireless base-stations. The active blocks are composed of regular threshold voltage devices only. The fourth-order architecture uses an OpAmp-RC-based loop filter and a 4-bit internal quantizer operated at 300-MHz clock frequency. The converter achieves a dynamic range of 11 bits over a bandwidth of 15 MHz. The power dissipation is 70 mW from a 1.5-V supply.     

A multibit delta-sigma audio DAC with 120-dB dynamic range

A 24-bit 192-kHz sample-rate digital-to-analog converter (DAC) achieves 120-dB A-weighted dynamic range in the 20-kHz band, and consumes 310 mW with a 5-V power supply. A third-order five-bit ΔΣ architecture optimized for high-end consumer audio has been developed and used. A switched-capacitor (SC) DAC combined with infinite-impulse response (IIR) and finite-impulse response (FIR) filters is employed to increase immunity to clock jitter, and reduce analog power. Partial-range dynamic element matching (DEM) enhances mismatch shaping with reduced circuit overhead. The 7.8-mm² chip fabricated in 0.5-μ m CMOS integrates a stereo DAC and all functions required for DVD-audio playback     

A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBTlimiting amplifier

A limiting amplifier IC implemented in a silicon-germanium (SiGe) heterojunction bipolar transistor technology for low-cost 10-Gb/s applications is described. The IC employs 20 dB gain limiting cells, input overload protection, split analog-digital grounds, and on-chip isolation interface with transmission lines. A gain enhancement technique has been developed for a parallel-feedback limiting cell. The limiting amplifier sensitivity is less than 3.5 mV_pp at BER=10^-9 with 2-V_pp maximum input (55-dB dynamic range). The total gain is over 60 dB, and S₂₁ bandwidth exceeds 15 GHz at 10-mV_pp input. Parameters S₁₁ and S₂₂ are better than -10 dB in the 10-GHz frequency range. The AM to PM conversion is less than 5 ps across input dynamic range. The output differential voltage can be set from 0.2 to 2 V_pp with IC power dissipation from 250 mW to 1.1 W. The chip area is 1.2×2.6 mm². A 10-Gb/s optical receiver, built with the packaged limiting amplifier, demonstrated -19.6-dBm sensitivity. The IC can be used in 10-Gb/s fiber-optic receivers requiring high sensitivity and wide input dynamic range     

A 2-GHz analog-to-digital delta-sigma modulator for CDMA receivers with 79-dB signal-to-noise ratio in 1.23-MHz bandwidth

This paper presents the design of a second-order single-bit analog-to-digital continuous-time delta-sigma modulator (CT-/spl Delta//spl Sigma/M) that can be used in wireless CDMA receivers. The CT-/spl Delta//spl Sigma/M samples at 2 GHz, consumes 18 mW at 1.8 V and has a 79-dB signal-to-noise ratio (SNR) over a 1.23-MHz bandwidth. The CT-/spl Delta//spl Sigma/M was fabricated in a 0.18-/spl mu/m 1-poly 6-metal, CMOS technology and has an active area of approximately 0.892 mm/sup 2/. The /spl Delta//spl Sigma/M's critical performance specifications are derived from the CDMA receiver specifications.     

300-mm full-factory Simulations for 90- and 65-nm IC manufacturing

We present enabling capabilities and key results realized by the development and implementation of 300-mm full-factory simulation tools supporting Intel's 90-nm high-volume manufacturing and 65-nm technology development factories. We discuss key attributes of these simulators which are being utilized for strategic fab capacity planning, automation systems designs, and tactical manufacturing execution and decision support for continuous improvement. These simulators capture the dynamic behaviors of hundreds of production tools with thousands of production and engineering lots and integrate automated material handling systems (AMHS) behaviors in these production simulations. The paper discusses specific topical areas where these tools have found widespread use and emphasizes the importance of periodic model validation and calibration to the real factory.     

A 1-V 60-μW 85-dB dynamic range continuous-time third-order sigma-delta modulator

A 1-V third order one-bit continuous-time (CT) ΣΔ modulator is presented. Designed in the SMIC mixed-signal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ΣΔ modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dBdynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm~2.     

一种用于驻极体麦克风的数字前置放大器设计

传统的模拟麦克风由于自身抗干扰能力差,很难满足新一代音频系统对输入端的要求,本文提出了一种数字前置放大器技术,可以与驻极体麦克风进行无缝连接,能够将麦克风产生的微弱的电信号直接转换成后续数字设计平台所需的数字信号,能够对信号进行可编程增益放大,具有面向便携式应用的宽电压摆动和低功耗设计。测试结果表明数字前置放大器动态范围达到88dB,等效输入参考噪声为5μVrms,正常工作功耗为540μW,休眠模式下消耗电流不超过10μA,与传统模拟麦克风相比,数字前置放大器构成的数字麦克风可以提供更好的信噪比、更高的集成度、更低的功耗和更强的抗干扰能力。     

A 22-kHz multibit switched-capacitor sigma-delta D/A converter with92 dB dynamic range

A time- and capacitor-multiplexing technique for use in a highly linear switched-capacitor multibit DAC in sigma-delta data converters is presented. The technique uses subintervals in the sample clock to deliver multiple charge packets to holding capacitors. It avoids distortion effects caused by mismatched capacitors and finite opamp gain. A five-level switched-capacitor DAC using the proposed technique was designed as part of an audio-band multibit sigma-delta D/A converter that achieved a dynamic range of 92 dB and a THD of -93 dB with a low oversampling ratio of 32. No trimming, calibration, or dynamic matching scheme was required. The five-level SC DAC has been fabricated in a 2-μm CMOS process, and testing confirmed the anticipated theoretical results     

A 5-mW sigma-delta modulator with 84-dB dynamic range for GSM/EDGE

A sigma-delta modulator designed as part of a complete GSM/EDGE (enhanced data rate for GSM evolution) transceiver is described. High-resolution wide-band analog-to-digital converters enable the receiver to rely on digital processing, rather than analog filtering, to extract the desired signal from blocking channels. High linearity and low power consumption are the most stringent requirements for the converters in this wireless application. A single-bit 2-2-cascaded modulator operating at 13 MHz has been adopted for high linearity and stability. Low-power low-voltage techniques have been applied along with a top-down design approach in order to minimize the power dissipation. The ΣΔ modulator achieves 13.5 bits of resolution over a bandwidth of 180 kHz while dissipating 5 mW from 1.8-V and 2.4-V supplies. The circuit has been implemented in the CMOS portion of a 0.4-μm (drawn) BiCMOS technology and occupies an active area of 0.4 mm²