电阻器和电容器

MKT1826叠层式金属化聚酯薄膜电容器与卷式薄膜器件相比改善了脉冲处理和自恢复性能。这种器件从1000pF到4.7μF提供23种电容值,容许误差为±5％、±10％和±20％。 其他性能规格还有:额定电压40Vdc、     

选择NbO电容器

用铌氧化电容器，将您的通孔铝电容式印刷电路板设计变成一个较小的SMT装配怎么样？如果考虑音频系统制造商最新的反馈的话，这个主意很不错吧!     

有机薄膜电容器替代电解电容器应用分析

分析了有机薄膜电容器的结构特点及发展趋势,并通过典型电路中的电容器应用实例结合电容器的应用性能参数对比分析,总结得出了有机薄膜电容器替代电解电容器的优势。在电源旁路、滤波、电源开关等对耐纹波电流能力、损耗和电容量稳定性要求较高的电路中,有机薄膜电容器可替代钽电解电容器。     

Digital inductors and capacitors

Circuits are described for simulating inductors and capacitors by digital (hardware) techniques. Filter and oscillator applications are discussed and test results are given.     

聚吡咯固体电解电容器

分析了聚吡咯（ＰＰＹ）固体电解电容器的性能特点，诸如：等效串联电阻、损耗角正切、电容量和阻抗频率特性、温度特性、纹波特性以及“自愈”特性等。讨论了ＰＰＹ固体电解电容器研制开发过程中应注意的工序。合理的制造工艺，可使ＰＰＹ固体电解电容器接近理想电容器的性能。     

Diffused silicon nonlinear capacitors

Diffused silicon nonlinear capacitors have been fabricated by solid-state diffusion. The resulting graded p-n junction is a planar structure which permits low series resistance Rsrelative to the minimum capacitanceC_{min}, which is measured at a reverse voltage slightly less than the breakdown voltage. A cutoff frequencyf_{c} = (2piR_{s}C_{min})^{-1}is used as a figure of merit; values up to 150 kmc have been obtained. These "varactor" diodes may be used as UHF and microwave amplifiers and as harmonic generators. The noise figures of the UHF amplifiers are better than the best noise figures obtainable by present electron-tube techniques. These diodes are also efficient harmonic generators.     

电源用电容器的选择

电容器是实现电源的宽范围电压和电流组合的最关键的无源元件之一。尽管每种电容器都能储存电能，但对于特定的应用来说，电介质技术在电容器的选择中起着重要的作用。电容器在电源中最重要的应用是在存储能量、浪涌电压保护、EMI抑制和控制电路等方面。我们可以通过图1了解到针对不同的应用领域，这些电介质技术彼此竞争或互为补充的关系。储能储能型电容器通过整流器收集电荷，并将存储的能量通过变换器引线传送至电源的输出端。电压额定值为40～450Vdc、电容值在220～150 000μF之间的铝电解电容器（如EPCOS公司的B43504或B43505）…     

新型贴片式铝聚合物固态电解电容器

铝电解电容器及钽电解电容器是大家较热悉的,但对新开发的铝聚合物固态电解电容器可能就较生疏了。本文介绍CDE公司生产的ESRD及ESRE两个系列贴片式铝聚合物电解电容器的内部结构、基本参数与特性曲线及应用。主要特点ESRD及ESRE两个系列的电解电容具有极好的高频特性,允许大的纹波电流,电容量允差±20%(精度为M级),等效串联电阻ESR小,ESRD电容在100kHz时为10～45mΩ,ESRE电容在100kHz时低于10mΩ,400kHz、20℃时的阻抗为13mΩ到81mΩ,在使用温度范围内阻抗几乎不变,工作寿命长,小尺寸贴片式封装,ESRD的尺寸为7.3mm(长)×4.…     

CMOS multiplier for grounded capacitors

A CMOS circuit suited particularly to magnifying the value of a grounded unit capacitor is presented. The multiplication factor is achieved through the gain of current mirrors and its maximum value is limited solely by power consumption constraints. Solutions are then developed to reduce power dissipation, to enable the detection of small unit capacitances, and to enlarge the operating frequency bandwidth     

钽电容器的阳极选择器件结构的新进展正改善着许多应用中的ESR

开关式电源,微处理器和数字电路应用的一个共同趋势是降低高频工作时的噪声。为了做到这一点,元器件必须具备低ESR(电阻率)、高电容和高可靠性。     

Process-dependent properties of three-dimensional capacitors

Capacitance per unit of cell area in silicon MOS IC technologies can be increased by etching convolutions into the semiconductor surface beneath the electrode [1]-[4]. These convolutions are typically formed via directional dry processing (reactive ion etching (RIE)). Energetic plasma process steps, however, have been reported to result in degradation of capacitor MOS properties in both planar [5]-[9] and three-dimensional [3], [4], [10] devices. In our experiments, planar devices formed on etched surfaces display MOS behavior that is normal in all respects when standard pre-oxidation cleaning is performed. Three-dimensional devices, however, can suffer a non-trivial degradation of dielectric breakdown voltage. The degradation is found to result from field enhancement accompanying identifiable topographical features, and is not an inherent result of RIE processing. RIE and post-RIE processing parameters influence the degree of degradation. TEM examination of three-dimensional devices is employed to characterize the physical nature of RIE-fabricated devices, and the observations are correlated with electrical behavior.     

Random errors in MOS capacitors

The effects of random edge variations and deviations of oxide thickness and permittivity are examined. Making only a few basic assumptions, it is shown that edge effects introduce a relative capacitance error /spl Delta/C/C/spl alpha/C/SUP -3/4/, while the oxide variations cause /spl Delta/C/C/spl alpha/C/SUP -1/2/. Error bounds are derived for C in terms of the variances of the linear dimensions and oxide permittivity. For a capacitor C realized as a parallel connection of n unit capacitors of values C/n, the relative error caused by edge effects is n/SUP 1/4/ times larger than for a single capacitor of value C. The relative error due to oxide variations remains the same for the two realizations. All theoretical results agree with physical consideration, as well as the Monte Carlo simulations performed.     

Effectiveness of multiple decoupling capacitors

The effectiveness of using the parallel combination of large-value and small-value capacitors to increase the frequency coverage of either one and overcome the effect of lead inductance is examined. Computed and experimental results are given that show this scheme is not significantly effective. The improvement at high frequencies is at most 6 dB over the use of only the large-value capacitance     

Characteristics of titanium electrolytic capacitors

Properties of titanium electrolytic capacitors produced by a newly developed oxidation process are described. Molten-salt electrolytes were utilized in the formation of the titanium oxide film. The characteristics of the titanium electrolytic capacitors are very similar to those of tantalum electrolytic capacitors except that the leakage current is somewhat larger. The results of life tests made on the titanium capacitors are presented.     

Leaking capacitors muck up motherboards

Aluminum electrolytic capacitors with a low equivalent series resistance (ESR) are high-capacitance components that generally serve to smooth out the power supply to chips. Throughout 2002, they have been breaking open and failing in certain desktop PCs. So far, the only motherboard maker to admit to the problem is ABIT Computer Corp. (Taipei), and the only major PC maker to acknowledge being affected is IBM Corp. But the problem is likely to be more widespread. It is clear now that a faulty electrolyte is to blame for the burst capacitors. Apparently, a scientist stole the formula for an electrolyte from his employer in Japan and began using it himself at the Chinese branch of a Taiwanese electrolyte manufacturer. He or his colleagues then sold the formula to an electrolyte maker in Taiwan, which began producing it for Taiwanese and possibly other capacitor firms. Unfortunately, the formula as sold was incomplete.     

表面层型半导体陶瓷电容器

对表面层型半导体陶瓷电容器的基本结构原理、关键生产技术、关键设计参数、关键生产设备以及电容器规格和典型特性作了简要介绍。     

Low-voltage coefficient capacitors for VLSI processes

The addition of a high-quality capacitor structure to a 1-μm digital CMOS process is considered to allow the fabrication of mixed analog and digital VLSI circuits. Two approaches have been examined which require minimal changes in the existing process. The first involves a high-dose arsenic implant through the thin (225 A) gate oxide to produce n⁺ single-crystal silicon bottom plates. This approach produced a capacity of 154 nF/cm² with a maximum voltage coefficient of 210 p.p.m./V over a bias range of ±7.5 V. In the second approach the high-dose implant is performed prior to the gate oxidation. Impurity-concentration-enhanced oxidation of the n⁺ silicon bottom plates can then be exploited during the subsequent gate oxidation to grow simultaneously a capacitor dielectric of varying thickness. Capacities of 40-90 nF/cm² have been produced with voltage coefficients ranging from 35 to 125 p.p.m./V, respectively     

Optical characterization of diamond MIS capacitors

The transient photoresponse properties of diamond metal-insulator-semiconductor (MIS) capacitors have been characterized for the first time. Capacitors were fabricated on natural diamond using an electrochemical cleaning step with a CVD SiO₂ dielectric and an optional carbon implantation to create a nonuniform doping profile. Devices were found to function as integrating photodetectors and were evaluated by the spectral dependence of the transient photocapacitance (PC). We discuss a model that distinguishes between the responses due to inversion layer population and that due to bulk trap occupancy changes. Inversion charge generation was observed at all wavelengths investigated and it dominated the PC transient at photon energies above 3 eV. Possible reasons for this result are discussed and analyzed. We could not demonstrate a suitable way to use carbon implantation to form a surface n-type layer in a MIS device without degrading the device IV properties and eliminating the integrating photoresponse observed on non-implanted devices. These results suggest that diamond charge-storage devices can function only if the diamond surface is prepared properly before device fabrication     

Tunable microstrip resonators with ferroelectric capacitors

The question of increasing the tuning band of microstrip resonators that use ferroelectric capacitors for tuning in the region of increased electric lengths is considered which allows using them in the upper part of the centimeter band (Ku-band, K-band). Band properties of regular and step-irregular resonators operating at the lowest resonant frequency are analyzed.     

Ion-implanted hyperabrupt junction voltage variable capacitors

Voltage variable capacitors have been fabricated using ion implantation and a PtSi Schottky barrier to obtain a high degree of control over the doping in a hyperabrupt diode structure. Three methods for obtaining the desired doping in the hyperabrupt region have been investigated, including diffusion from a low energy predeposition and higher energy implantations with no diffusion. TheC-Vcharacteristics for two different profiles, made using diffusion to drive in an ion predeposition, agree well with theoretical calculations if a Gaussian diffusion profile peaked at the surface is assumed(D = 2.38 times 10^{-13}cm²/s for phosphorus at 1100°C in an oxygen ambient). It has been found that the device parameter spread of about 7 percent is dominated by nonuniformities in the donor concentration of the epitaxial layer. Parameter variations due to sources other than the epitaxial layer doping are about 3 percent. Low-dose channeling implantations have been made to tailor the profile such that the sensitivity-(dC/C)(V/dV) is nearly constant