A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters

In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter. Both the theoretical background and practical algorithms are presented to characterize a set of deterministic test cubes by a reasonably small number of seeds for a folding counter. Combined with classical approaches for test width compression and with pseudo-random pattern generation these new techniques provide an efficient and flexible solution for scan-based BIST. Experimental results show that the proposed scheme outperforms previously published approaches based on the reseeding of LFSRs or Johnson counters.     

BIST test pattern generator for delay testing

To detect delay faults in a digital circuit requires a test sequence applied at the nominal frequency of the circuit. Built-in self-test (BIST) is a technique that provides such testing possibilities at speed, without expensive test equipments. A BIST test pattern generator (TPG) design, targeting the detection of delay faults is proposed     

Cost/Quality Trade-off in Synthesis for BIST

This paper details our allocation for Built-in Self Test (BIST) technique used by the core part of our Testability Allocation and Control System (TACOS) called IDAT. IDAT tool objective is to fulfill the designer requirements regarding selected design and testability attributes of a circuit data-path to be synthesized. A related tool is used to synthesize a test controller for the final testable circuit. The allocation process of BIST resources in the data-path is driven by two trade-off techniques performed in order to: (1) at the local level, select the optimal set of Functional Units (FUs) to be BISTed, using a new testability analysis method and (2) at the global level, for each selected FU of this set, choose either to allocate its BIST version (when available in a library) or to connect it to an internal Test Pattern Generator (TPG) and Test Results Checker (TRC). When necessary, a last step of the process is the allocation of scan chains used to test the remaining untested interconnections. Experiments show the results of our allocation for BIST technique on three benchmarks.     

一种有效的ADC内建自测试方案

内建自测试是降低ADC电路测试成本的有效方法。通过最小二乘法和斜坡柱状图。我们得出了测试ADC电路的增益误差、失调误差、微分非线性和积分非线性的算法。根据这些测试算法。介绍了一种易于片上集成的内建自测试结构。实验结果表明，该内建自测试方案具有较高的测试精度。     

A BIST-DFT technique for DC test of analog modules

Among test techniques for analog circuits, DC test is one of the simplest method for BIST application since easy to integrate test pattern generator and response analyzer are conceivable. Precisely, this paper presents such an investigation for a CMOS operational amplifier that is latter extended to active analog filters. Since the computation of fault coverage is still a controversy question for analog cells, we develop first an evaluation technique for optimizing the tolerance band of the measurements to test. Then, using some DFT solutions we derive single DC pattern and discuss the minimal number of points to test for the detection of defects. A response analyzer is integrated with a Built-in Voltage Sensor (BIVS) and provides directly a logic pass/fail test result. Finally, the extra circuitry introduced by this BIST technique for analog modules does not exceed 5% of the total silicon area of the circuit under test and detects most of the faults.     

On Chip Signal Generators for Low Overhead ADC BIST

Testing of ADCs deeply embedded in SOCs is a significant challenge due to access limitations. ADC Built-in self-test (BIST) is considered a promising alternative to traditional test. This paper investigates implementation issues in adapting the stimulus error identification and removal (SEIR) algorithm, originally developed for production test, into a practical ADC BIST solution. Signal generators with very low transistor count and area consumption are presented. Extremely simple methods for generating small constant voltage level shifts are introduced and evaluated. Simulation results show that the generated signals, together with the level shifts, are able to test a 16-bit ADC to 16 bit accuracy levels. These results demonstrate that accurate BIST of deeply embedded analog and mixed-signal (AMS) blocks may be practically implemented on chip with very low overhead.     

一种减少BIST测试资源的高级寄存器分配算法

在高级综合阶段考虑电路的可测性有许多优点，包括降低硬件开销，减少性能的下降，并达到更高的测试效率等。本文提出了一种基于伪随机可测性方法的寄存器分配算法，来减少内建自测试（BIST）所带来的硬件开销。在基准电路上的实验结果表明：与其它BIST测试综合方法相比较，采用本论文所提的方法进行测试综合对测试资源占用最多可以降低46.8%.     

Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation

A novel low-power CMOS synchronous counter whose clock-gating logic is embedded into a carry propagation circuit is proposed. The proposed synchronous counter operates with no redundant transitions and requires fewer transistors, minimizing the switching power consumption and silicon area as compared with conventional CMOS synchronous counters. The proposed synchronous counter consisting of 16 bits was fabricated in 0.18- $muhbox{m}$ CMOS technology. The experimental result indicates that the proposed synchronous counter achieves a power saving of 64% with 15% device count reduction.      

Design for testability and built-in self test: a review

A summary is presented of a number of design-for-testability (DFT) and built-in self-test (BIST) schemes that can be used in modern VLSI circuits. The DFT methods presented are used to increase the controllability and observability of the circuit design. Partitioning, bus architectures, test-point insertion, and scan methods are discussed. On-chip hardware for real-time test-pattern generation and data compression are investigated. Several of the DFT methods are then combined to form BIST hardware configurations. Built-in evaluation and self-test (BEST), autonomous test, scan with random inputs, built-in logic block observer (BILBO), partitioning with BEST, test-point insertion with on-chip control, and combined test-pattern generation and data compression (CTGC) are considered. An overview of each BIST scheme is offered     

SOC基于LFSR的混合模式测试

随着集成电路深亚微米制造技术和设计技术迅速发展,系统芯片(SOC)作为一种解决方案得到了越来越广泛的应用。SOC的测试中,内建自测试(Built.In Self-Test,BIST)成为人们研究的热点。文中对SOC的设计特点及其BIST中的混合模式测试进行了探讨。     

SoC中低峰值功耗的BIST调度算法

本文提出了一种系统芯片(SoC)中用于降低内建自测试(Built-in Self-test，BIST)峰值功耗的调度算法。首先本文提出了基于扫描BIST的精简功耗模型，在此模型的基础上，提出了通过调整扫描周期和扫描起动时间的办法来避免过高的SoC测试峰值功耗。实验结果表明，该算法可以有效地避免BIST并行执行可能带来的过高峰值功耗。     

An Accumulator-Based Compaction Scheme For Online BIST of RAMs

Transparent built-in self test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional transparent BIST schemes, achieving considerable reduction in test time. In symmetric transparent BIST schemes proposed to date, output data compaction is performed using either single-input or multiple-input shift registers whose characteristic polynomials are modified during testing. In this paper the utilization of accumulator modules for output data compaction in symmetric transparent BIST for RAMs is proposed. It is shown that in this way the hardware overhead, the complexity of the controller, and the aliasing probability are considerably reduced.      

A concurrent built-in self-test architecture based on a self-testing RAM

Manufacturing test is carried-out once to ensure the correct operation of the circuit under test right after fabrication, while testing is carried-out periodically to ensure that the circuit under test continues to operate correctly on the field. The use of offline built-in self-test (BIST) techniques for periodic testing imposes the interruption of the normal operation of the circuit under test. On the other hand, the use of input vector monitoring concurrent BIST techniques for periodic testing provides the capability to perform the test, while the circuit under test continues to operate normally. In this paper, a novel input-vector monitoring concurrent BIST technique for combinational circuits based on a self-testing RAM, termed R-CBIST, is presented. The presented technique compares favorably to the other input vector monitoring concurrent BIST techniques proposed so far with respect to the hardware overhead, and the time required for the concurrent test to be completed (concurrent test latency). R-CBIST can be utilized to test ROM because it results in small hardware overhead, whereas there is no need to stop the ROM normal operation.     

Combining Scan Test and Built-in Self Test

For digital chips containing functional logic and embedded memories, these are usually tested separately: Scan test is used for testing functional logic; Memory Built-in Self Test (MBIST) is run for embedded memories. A new approach is proposed to exercise scan test and MBIST in parallel in order to reduce production test time and improve stress tests. It requires only small additional logic and allows to simultaneously run both test modes. In general, the approach can be used to control simultaneously scan test and any Built-in Self Test (BIST) providing a simple pass/fail result.     

Built in self test: a complete test solution for telecommunicationsystems

The technological revolution witnessed by the telecommunications industry is leading to the development of new applications, products, and protocols, which in turn solicits widely accessible, highly reliable, and high-quality networks. To meet the stringent quality and reliability requirements of today's complex communication networks, efficient test methodologies are necessary at all levels (system, board, circuit, etc.). Conventional test methodologies are being constantly challenged by ever-increasing speed and circuit size, which results in high costs associated with test hardware, test generation, and test application time. Built-in self-test offers a test methodology where the test functions are embedded into the circuit itself. The advantages of using BIST for complex telecommunication systems are numerous. Reduced test development time, low test application time, eliminating the need for very-high-speed hardware testers, provision for at-speed tests, in-field test capability, and high fault coverage are some of them. In this article we present a tutorial on the BIST methodology targeted mainly toward telecommunication systems, the test structures necessary for its incorporation both at the circuit and system levels, and test implementation at the higher levels of design abstraction     

A Design of Linearity Built-in Self-Test for Current-Steering DAC

In this paper, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters (DACs). The proposed DAC BIST scheme is designed to verify a 10-bit segmented current-steering DAC, consist of a 5-bit coarse DAC and a 5-bit fine one. This proposed BIST scheme includes a current-mode sample-and-difference circuit to increase the sampling current accuracy and control a current-controlled oscillator (ICO). In addition, only 36 measurements are required by using the selected-code method rather than 1024 measurements for the conventionally-utilized all-code method. Compared to the conventionally-utilized all-code method, about 85-% reduction of test time can be achieved.     

Code-width testing-based compact ADC BIST circuit

This paper proposes a new analog-to-digital converter (ADC) built-in self-test (BIST) scheme based on code-width and sample-difference testing that does not require a slope-calibrated ramp signal. The proposed BIST scheme can be implemented by a simple digital circuit whose gate count is only approximately 550. The proposed BIST scheme is verified by simulation with 138 test circuits of 6-b pipeline ADC with arbitrary faults. Simulation results show that it effectively detects not only the catastrophic faults but also some parametric faults. The simulated fault coverage is approximately 99%.     

Datapath BIST Insertion Using Pre-Characterized Area and Testability Data

There are several ways to insert Built-in Self-Test (BIST) circuitry on a circuit, each of them with particular consequences on area overhead, test application time and fault coverage. This paper presents a BIST insertion methodology applied to datapaths described at the RTL level that uses a database containing: (a) testability data of several types of test pattern generators (TPGs) and signature analyzers (SAs) when connected to several types of functional units and (b) area overhead due to the implementation by a datapath register of each type of those test resources. The availability of this database makes then possible to choose the best test resource types associated to each functional unit in a datapath, leading to good testability and area results.     

Symmetry Measure for Memory Test and Its Application in BIST Optimization

Programmable Built-in Self-Test (BIST) has been widely used for testing embedded memories. The main disadvantage of having programmability on BIST circuits is the size of Test Algorithm Register (TAR) that becomes very crucial in case of complex test algorithms. To optimize Programmable BIST hardware symmetric March tests are usually used in BIST engines. On the other hand, the used definitions do not reflect completely the existing symmetry in test algorithms and they also do not reflect the fact that the level of symmetry in a given test algorithm can be measured. A new method of symmetry measurement for memory test algorithms and a corresponding metric are introduced. A dependency between symmetry measure and BIST optimization range is analyzed. Optimization experiments that have been done for a number of well-known test algorithms show that the BIST hardware gain could reach 48%. However, the time overhead is negligible in comparison with the hardware gain. The experiments also show that starting from some point a monotone dependency between symmetry measure and BIST hardware area exists.