High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current I/sub g/ and to prevent boron penetration in the pFET. The thermal budget in the middle of the line (MOL) process was reduced enough to realize shallower junction depth in the S/D extension regions and to suppress gate poly-Si depletion. Finally, the current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/=0.85 V (at I/sub off/=100 nA//spl mu/m) were achieved and they are the best values for 35 nm gate length CMOS reported to date.     

Low-power logic circuit and SRAM cell applications with silicon on depletion Layer CMOS (SODEL CMOS) technology

In this paper, the switching performance of Silicon on Depletion Layer CMOS (SODEL CMOS) is investigated with a view to realizing high-speed and low-power CMOS applications. Thanks to smaller parasitic capacitance, the propagation delay time (/spl tau//sub pd/) in SODEL CMOS has been improved by up to 25% compared to that of conventional bulk CMOS in five stacked nFET inverters at the same V/sub dd/. It is also confirmed that about 30% better power-delay product can be realized at the same /spl tau//sub pd/ with reduced V/sub dd/ in SODEL CMOS. In SRAM cell applications, SODEL CMOS shows high Static Noise Margin (SNM) of /spl sim/95 mV at V/sub dd/=0.6 V. Smaller bitline delay is expected and confirmed in SODEL CMOS SRAM by SPICE simulations. Latch-up immunity for /spl alpha/-particle irradiation in SODEL CMOS was also found to be comparable to that of conventional bulk CMOS. Therefore, SODEL CMOS device and circuit technology is expected to provide a better solution for low-power system-on-a-chip (SoC).     

A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node

In this letter, we have fabricated a functional FinFET ring oscillator with a physical gate length of 25 nm and a fin width of 10 nm, the smallest ever reported. We demonstrate that these narrow (W/sub fin/ = 10 nm) and tall (H/sub fin/ = 60 - 80 nm) fins can be reliably etched with controlled profiles and that they are required to keep the short-channel effects under control, resulting in drain-induced barrier leakage characteristics of 45 mV/V at V/sub dd/ = 1 V and L/sub g/ = 25 nm for the nFET. For these ultrathin (10 nm) fins, we have succeeded in properly setting the V/sub T/ at 0.2 V without the use of metal gates. In addition to ring oscillators, we also have obtained excellent pFET FinFET devices at wider fin widths (W/sub fin/ = 65 nm) with I/sub dsat/ = 380 /spl mu/A//spl mu/m at I/sub off/ = 60 nA//spl mu/m and V/sub dd/ = -1.2 V.     

InGaAs/InP DHBTs with 120-nm collector having simultaneously high f/sub /spl tau//, f/sub max//spl ges/450 GHz

InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBT) have been designed for increased bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 450 GHz f/sub /spl tau// and 490 GHz f/sub max/, which is the highest simultaneous f/sub /spl tau// and f/sub max/ for any HBT. The devices have been scaled vertically for reduced electron collector transit time and aggressively scaled laterally to minimize the base-collector capacitance associated with thinner collectors. The dc current gain /spl beta/ is /spl ap/ 40 and V/sub BR,CEO/=3.9 V. The devices operate up to 25 mW//spl mu/m/sup 2/ dissipation (failing at J/sub e/=10 mA//spl mu/m/sup 2/, V/sub ce/=2.5 V, /spl Delta/T/sub failure/=301 K) and there is no evidence of current blocking up to J/sub e//spl ges/12 mA//spl mu/m/sup 2/ at V/sub ce/=2.0 V from the base-collector grade. The devices reported here employ a 30-nm highly doped InGaAs base, and a 120-nm collector containing an InGaAs/InAlAs superlattice grade at the base-collector junction.     

Characterization of 1.9- and 1.4-nm ultrathin gate oxynitride by oxidation of nitrogen-implanted silicon substrate

For gate oxide thinned down to 1.9 and 1.4 nm, conventional methods of incorporating nitrogen (N) in the gate oxide might become insufficient in stopping boron penetration and obtaining lower tunneling leakage. In this paper, oxynitride gate dielectric grown by oxidation of N-implanted silicon substrate has been studied. The characteristics of ultrathin gate oxynitride with equivalent oxide thickness (EOT) of 1.9 and 1.4 nm grown by this method were analyzed with MOS capacitors under the accumulation conditions and compared with pure gate oxide and gate oxide nitrided by N/sub 2/O annealing. EOT of 1.9- and 1.4-nm oxynitride gate dielectrics grown by this method have strong boron penetration resistance, and reduce gate tunneling leakage current remarkably. High-performance 36-nm gate length CMOS devices and CMOS 32 frequency dividers embedded with 57-stage/201-stage CMOS ring oscillator, respectively, have been fabricated successfully, where the EOT of gate oxynitride grown by this method is 1.4 nm. At power supply voltage V/sub DD/ of 1.5 V drive current Ion of 802 /spl mu/A//spl mu/m for NMOS and -487 /spl mu/A//spl mu/m for PMOS are achieved at off-state leakage I/sub off/ of 3.5 nA//spl mu/m for NMOS and -3.0 nA//spl mu/m for PMOS.     

A 243-GHz F/sub t/ and 208-GHz F/sub max/, 90-nm SOI CMOS SoC technology with low-power mm-wave digital and RF circuit capability

A 90-nm silicon-on-insulator (SOI) CMOS system on-chip integrates high-performance FETs with 243-GHz F/sub t/, 208-GHz F/sub max/, 1.45-mS//spl mu/m gm, and sub 1.1-dB NFmin up to 26 GHz. Inductor Q of 20, VNCAP of 1.8-fF//spl mu/m/sup 2/, varactor with a tuning range as high as 25:1, and a low-loss microstrip. Transmission lines were successfully integrated without extra masks and processing steps. SOI and its low parasitic junction capacitance enables this high level of performance and will expand the use of CMOS for millimeter-wave applications.     

High drive current NMOS with Si-SiGe heterostructure low electric field channel

A drive-current enhancement in NMOS with a compressively strained SiGe structure, which had been a difficult challenge for CMOS integration with strained SiGe high-hole-mobility PMOS, was successfully achieved using a Si-SiGe heterostructure low electric field channel of optimum thickness. A 4-nm-thick Si low-field-channel NMOS with a 4-nm-thick Si/sub 0.8/Ge/sub 0.2/ layer improved drive current by 10% with a 20% reduction in gate leakage current compared with Si-control, while suppressing threshold-voltage rolloff characteristic degradation, and demonstrated excellent I/sub on/--I/sub off/ characteristics of I/sub on/ = 1 mA//spl mu/m for I/sub off/ = 100 nA//spl mu/m. These results are the best in ever reported NMOS with a compressively strained SiGe structure and indicate that a Si-SiGe heterostructure low-field-channel NMOS integrated with a compressively strained SiGe channel PMOS is a promising candidate for high-speed CMOS in 65-nm node logic technology.     

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

This letter reports on 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At V/sub dd/ Of 1.5-V and 25/spl deg/C, drive currents of 634 /spl mu/A//spl mu/m for 90-nm L/sub gate/ NMOS and 208 /spl mu/A-/spl mu/m for 110-nm L/sub gate/ buried-channel PMOS are achieved at 25 pA//spl mu/m off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.     

InGaAs-InP mesa DHBTs with simultaneously high f/sub /spl tau// and f/sub max/ and low C/sub cb//I/sub c/ ratio

We report an InP-InGaAs-InP double heterojunction bipolar transistor (DHBT), fabricated using a conventional triple mesa structure, exhibiting a 370-GHz f/sub /spl tau// and 459-GHz f/sub max/, which is to our knowledge the highest f/sub /spl tau// reported for a mesa InP DHBT-as well as the highest simultaneous f/sub /spl tau// and f/sub max/ for any mesa HBT. The collector semiconductor was undercut to reduce the base-collector capacitance, producing a C/sub cb//I/sub c/ ratio of 0.28 ps/V at V/sub cb/=0.5 V. The V/sub BR,CEO/ is 5.6 V and the devices fail thermally only at >18 mW//spl mu/m/sup 2/, allowing dc bias from J/sub e/=4.8 mA//spl mu/m/sup 2/ at V/sub ce/=3.9 V to J/sub e/=12.5 mA//spl mu/m/sup 2/ at V/sub ce/=1.5 V. The device employs a 30 nm carbon-doped InGaAs base with graded base doping, and an InGaAs-InAlAs superlattice grade in the base-collector junction that contributes to a total depleted collector thickness of 150 nm.     

Graded base type-II InP/GaAsSb DHBT with f/sub T/=475 GHz

The first demonstration of a type-II InP/GaAsSb double heterojunction bipolar transistor (DHBT) with a compositionally graded InGaAsSb to GaAsSb base layer is presented. A device with a 0.4/spl times/6 /spl mu/m/sup 2/ emitter dimensions achieves peak f/sub T/ of 475 GHz (f/sub MAX/=265 GHz) with current density at peak f/sub T/ exceeding 12 mA//spl mu/m/sup 2/. The structure consists of a 25-nm InGaAsSb/GaAsSb graded base layer and 65-nm InP collector grown by MBE with breakdown voltage /spl sim/4 V which demonstrates the vertical scaling versus breakdown advantage over type-I DHBTs.     

15-nm base type-II InP/GaAsSb/InP DHBTs with F/sub T/=384 GHz and a 6-V BV/sub CEO/

Type-II InP/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) with a 15-nm base were fabricated by contact lithography: 0.73/spl times/11 /spl mu/m/sup 2/ emitter devices feature f/sub T/=384GHz (f/sub MAX/=262GHz) and BV/sub CEO/=6V. This is the highest f/sub T/ ever reported for InP/GaAsSb DHBTs, and an "all-technology" record f/sub T//spl times/BV/sub CEO/ product of 2304 GHz/spl middot/V. This result is credited to the favorable scaling of InP/GaAsSb/InP DHBT breakdown voltages (BV/sub CEO/) in thin collector structures.     

50-nm gate Schottky source/drain p-MOSFETs with a SiGe channel

We propose new SiGe channel p-MOSFETs with germano-silicide Schottky source/drains (S/Ds). The Schottky barrier-height (SBH) for SiGe is expected to be low enough to improve the injection of carriers into the SiGe channel and, as a result, current drivability is also expected to improve. In this work, we demonstrate the proposed Schottky S/D p-MOSFETs down to a 50-nm gate-length. The drain current and transconductance are -339 /spl mu/A//spl mu/m and 285 /spl mu/S//spl mu/m at V/sub GS/=V/sub DS/=-1.5 V, respectively. By increasing the Ge content in the SiGe channel from 30% to 35%, the drive current. and transconductance can be improved up to 23% and 18%, respectively. This is partly due to the lower barrier-height for strained Si/sub 0.65/Ge/sub 0.35/ channel than those for strained Si/sub 0.7/Ge/sub 0.3/ channel device and partly due to the lower effective mass of the holes.     

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.     

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

The authors demonstrate high-performing n-channel transistors with a HfO/sub 2//TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 /spl Aring/, a leakage current of 1.5 A/cm/sup 2/ at V/sub G/=1 V, a peak mobility of 190 cm/sup 2//V/spl middot/s, and a drive-current of 815 /spl mu/A//spl mu/m at an off-state current of 0.1 /spl mu/A//spl mu/m for V/sub DD/=1.2 V. Identical gate stacks processed with a 1000-/spl deg/C spike anneal have a higher peak mobility at 275 cm/sup 2//V/spl middot/s, but a 5-/spl Aring/ higher EOT and a reduced drive current at 610 /spl mu/A//spl mu/m. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 /spl deg/C) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V.     

A technique to improve the drive current of high-voltage I/O transistors in digital CMOS technologies

By combining a 0.12-/spl mu/m-long 1.2-V thin-oxide transistor with a 0.22-/spl mu/m-long 3.3-V thick-oxide transistor in a 0.13-/spl mu/m CMOS process, a composite MOS transistor structure with a drawn gate length of 0.34 /spl mu/m is realized. Measurements show that at V/sub GS/=1.2 V and V/sub DS/=3.3 V, the composite transistor has more than two times the drain current of the minimum channel length (0.34 /spl mu/m) 3.3-V thick-oxide transistor, while having the same breakdown voltage (V/sub BK/) as the thick-oxide transistor. Exploiting these, it should be possible to implement 3.3-V I/O transistors with better combination of drive current, threshold voltage (V/sub T/) and breakdown voltage in conventional CMOS technologies without adding any process modifications.     

An ultrathin vertical channel MOSFET for sub-100-nm applications

An ultrathin vertical channel (UTVC) MOSFET with an asymmetric gate-overlapped low-doped drain (LDD) is experimentally demonstrated. In the structure, the UTVC (15 nm) was obtained using the cost-effective solid phase epitaxy, and the boron-doped poly-Si/sub 0.5/Ge/sub 0.5/ gate was adopted to adjust the threshold voltage. The fabricated NMOSFET offers high-current drive due to the lightly doped (<1/spl times/10/sup 15/ cm/sup -3/) channel, which suppresses the electron mobility degradation. Moreover, an asymmetric gate-overlapped LDD was used to suppress the offstate leakage current and reduce the source/drain series resistance significantly as compared to the conventional symmetrical LDD. The on-current drive, offstate leakage current, subthreshold slope, and DIBL for the fabricated 50-nm devices are 325 /spl mu/A//spl mu/m, 8/spl times/10/sup -9/ /spl mu/A//spl mu/m, 87 mV/V, and 95 mV/dec, respectively.     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.     

A 22-nm damascene-gate MOSFET fabrication with 0.9-nm EOT and local channel implantation

We introduce a novel CMOS transistor fabrication technique using damascene gate with local channel implantation (LCI). This transistor has a benefit to reduce the resistance of source/drain extension (SDE) localizing the severe blanket channel implantation under the channel only. It can reduce the junction capacitance as well. This process technology is reliable for the formation of channel length down to 22 nm with smooth gate line edge roughness. Some unique processes for the small transistor fabrication are also introduced. The 22-nm nMOSFET with 0.9 nm RTO is achieved with the drive current of 930 /spl mu/A//spl mu/m for the off-current of 100 nA//spl mu/m at 1.0 V. Hot carrier reliability exceeding 10 years for 1.0 V operation is also obtained.     

High-responsivity high-gain In/sub 0.53/Ga/sub 0.47/As-InP quantum-well infrared photodetectors grown using metal-organic vapor phase epitaxy

We report the growth and fabrication of bound-to-bound In/sub 0.53/Ga/sub 0.47/As-InP quantum-well infrared photodetectors using metal-organic vapor phase epitaxy. These detectors have a peak detection wavelength of 8.5 /spl mu/m. The peak responsivities are extremely large with R/sub pk/=6.9 A/W at bias voltage V/sub b/=3.4 V and temperature T=10 K. These large responsivities arise from large detector gain that was found to be g/sub n/=82 at V/sub b/=3.8 V from dark current noise measurements at T=77 K and g/sub p/=18.4 at V/sub b/=3.4 V from photoresponse data at T=10 K. The background-limited temperature with F/1.2 optics is T/sub BLIP/=65 K for 0相似文献   

Metrics for performance benchmarking of nanoscale Si and carbon nanotube FETs including device nonidealities

This paper proposes a simple and accurate expression for inverter effective drive current for nanoscale Si and carbon nanotube FET (CNFET) performance benchmarking. The choice of I/sub eff/=(I/sub NL/+I/sub NM/+I/sub NH/-I/sub P/)/3, where I/sub NL/=I/sub DS(N-FET)/ (V/sub GS/=0.5V/sub DD/, V/sub DS/=V/sub DD/), I/sub NM/=I/sub DS(N-FET)/(V/sub GS/=0.75V/sub DD/, V/sub DS/=0.75V/sub DD/), I/sub NH/=I/sub DS(N-FET)/ (V/sub GS/=V/sub DD/, V/sub DS/=0.5V/sub DD/), and I/sub P/=I/sub SD(P-FET)/ (V/sub SG/=0.25V/sub DD/, V/sub SD/=0.25V/sub DD/), includes the effects of both the nFET and the pFET of an inverter and accurately captures the inverter delay performance over many CMOS technology nodes and in the presence of device nonidealities. The proposed metric indicates that the performance enhancement of CNFETs over Si MOSFETs is not as large as that predicted by I/sub Dsat/ in a circuit environment because of the nonideal I-V characteristics.