Critical reliability challenges in scaling SiO2-based dielectric to its limit

The limitations of silicon dioxide dielectric reliability for future CMOS scaling are investigated. Several critical aspects are examined, and new experimental results are used to form an empirical approach to a theoretical framework upon which the data is then interpreted. Experimental data over a wide range of oxide thickness, voltage, and temperature were gathered using structures with a wide range of gate-oxide areas, and over very long stress times. Resolution of seemingly contradictory observations regarding the temperature dependence of oxide breakdown is provided by this work. On the basis of these results, a unified, global picture of oxide breakdown is constructed and the resulting model is applied to project reliability limits for the wear-out of silicon dioxide. It is concluded that silicon dioxide-based dielectrics can provide reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable to the 50 nm technology node using silicon-dioxide-based gate insulators.     

Transistor off-state leakage current induced by TiSi2pre-amorphizing implant in a 0.20 μm CMOS process

We report on an anomalous off-state leakage current found in NMOS devices fabricated with a pre-amorphizing (PA) implant before titanium silicide formation. We present data which indicates that the leakage current is caused by channeling of the arsenic PA implant through the polysilicon gate. An angled PA implant is shown to prevent the channeling and allow the fabrication of well-behaved devices with low resistance titanium silicide     

Charge transport in thick SiO2-based dielectric layers

Charge transport in thick (≥ 1 μm) SiO₂-based dielectric layers was investigated by means of I(U) measurements. Investigations were carried out on thermally grown field oxide (FOX) as well as on TEOS and BPSG. Gate oxide layers (GOX) were measured as reference. C(U) measurements were performed for the determination of charges in the oxide. To determine the electrical parameters of the layers, the model from Chen and Wu[1] was developed further. The model takes into account tunnelling, capture and emission processes, impact ionization, recombination, interface states and ohmic currents.

The I(U) characteristics for all dielectrics examined can be described with the aid of the model. The FOX parameters correspond to those of GOX. The parameters of TEOS and BPSG fluctuate strongly with the process parameters. After high-temperature annealing and from measurement of the examined parameters, the insulation properties of TEOS and BPSG were found to be at least as good as those of FOX.     

A power optimized 13-b 5 Msamples/s pipelined analog-to-digitalconverter in 1.2 μm CMOS

A 13-b 5-MHz pipelined analog-to-digital converter (ADC) was designed with the goal of minimizing power dissipation. Power was reduced by using a high swing residue amplifier and by optimizing the per stage resolution. The prototype device fabricated in a 1.2 μm CMOS process displayed 80.1 dB peak signal-to-noise plus distortion ratio (SNDR) and 82.9 dB dynamic range. Integral nonlinearity (INL) is 0.8 least significant bits (LSB), and differential nonlinearity (DNL) is 0.3 LSB for a 100 kHz input. The circuit dissipates 166 mW on a 5 V supply     

High average power UV generation at 0.266 μm inBeSO4·4H2O

A report on the efficient generation of highly stable 1.7-W average power UV pulses at 0.266 μm in BeSO₄·4H₂O is presented. BeSO₄·4H₂O has been found to be a superior material for high peak-power and high average-power UV generation at 0.266 μm. A Gaussian-like beam having an average power of 1.7 W was generated without damage to the crystal at room temperature     

Laser cross-section and quantum yield of Er3+ at 2.7μm in a ZrF4-based fluoride glass

Spectroscopic determination of laser cross-section and quantum efficiency of the Er³⁺ laser transition at 2.7 μm are reported for the first time for a fluoride glass of the ZBLAN type. Comparisons with crystal values and other glass compositions are given. Emission spectra of Er³⁺ at 2.7 μm are also presented for the first time     

A 0.13 μm CMOS adaptive sigma-delta modulator for triple-mode GSM/Bluetooth/UMTS applications

This paper describes the design and experimental characterization of a 0.13 μm CMOS switched-capacitor reconfigurable cascade ΣΔ modulator intended for multi-standard GSM/Bluetooth/UMTS hand-held devices. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt the effective resolution and the output rate to different standard specifications with optimized power dissipation. This is achieved by properly combining different reconfiguration modes that include the variation in the order of the loop filter (3rd- or 4th-order), the clock frequency (40 or 80 MHz), the internal quantization (1 or 2 bits), and the bias currents of the amplifiers. The selection of the modulator topology and the design of its building blocks are based on a top-down CAD methodology that combines simulation and statistical optimization at different levels of the modulator hierarchy. Experimental measurements show a correct operation of the prototype for the three standards, featuring dynamic ranges of 83.8/75.9/58.7 dB and peak signal-to-(noise+distortion) ratios of 78.7/71.3/53.7 dB at 400 ksps/2/8 Msps, respectively. The modulator power consumption is 23.9/24.5/44.5 mW, of which 9.7/10/24.8 mW are dissipated in the analog circuitry. The multi-mode ΣΔ prototype shows an overall performance that is competitive with the current state of the art.¹     

0.3 dB minimum noise figure at 2.5 GHz of 0.13 μm Si/Si0.58Ge0.42 n-MODFETs

RF and microwave noise performances of strained Si/Si_0.58 Ge_0.42 n-MODFETs are presented for the first time. The 0.13 μm gate devices have de-embedded f_T=49 GHz, f_max =70 GHz and a record intrinsic g_m=700 mS/mm. A de-embedded minimum noise figure NF_min=0.3 dB with a 41 Ω noise resistance R_n and a 19 dB associated gain G_ass are obtained at 2.5 GHz, while NF_min=2.0 dB with G_ass=10 dB at 18 GHz. The noise parameters measured up to 18 GHz and from 10 to 180 mA/mm with high gain and low power dissipation show the potential of SiGe MODFETs for mobile communications     

The effect of remote plasma nitridation on the integrity of theultrathin gate dielectric films in 0.13 μm CMOS technology and beyond

The authors report the effect of the remote plasma nitridation (RPN) process on characteristics of ultrathin gate dielectric CMOSFETs with the thickness in the range of 18 Å~22 Å. In addition, the effect of RPN temperature on the nitrogen-profile within the gate dielectric films has been investigated. Experimental results show that the thinner the gate dielectric films, the more significant effect on reducing the gate current and thinning the thickness of gate dielectric films by the RPN process. Furthermore, the minimum dielectric thickness to block the penetration of B and N has been estimated based on the experimental results. The minimum RPN gate dielectric thickness is about 12 Å     

A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7μm CMOS ASIC

A byte-wide I/O cell with 660 MB/s data rate uses low-jitter DLL-generated clocks, self-calibrated controlled-current drivers, and linear amplifier input receivers. The CAD techniques developed allow the design to be ported to CMOS processes ranging from 0.7 μm to 0.3 μm. The chip is 0.9×3.4 mm² using 0.3 μm rules     

17-GHz 50-60 mW power amplifiers in 0.13-/spl mu/m standard CMOS

Two versions of power amplifiers with different output matching approaches for the 17-GHz band were realized in 0.13-/spl mu/m standard digital CMOS technology with 1.5-V supply voltage. The power amplifier with an external matching network delivers 17.8-dBm saturated output power with 15.6% power added efficiency (PAE). The small-signal gain is 11.5 dB. The fully integrated power amplifier delivers 17.1-dBm saturated output power with 9.3% PAE. The small-signal gain is 14.5 dB. No external radio frequency components are required.     

A 200 MHz quadrature digital synthesizer/mixer in 0.8 μm CMOS

A 200 MHz quadrature direct digital frequency synthesizer/complex mixer (QDDFSM) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc. The frequency resolution is 0.047 Hz with a corresponding switching speed of 5 ns and a tuning latency of 14 clock cycles. The chip is also capable of frequency, phase, and quadrature amplitude modulation. These modulation capabilities operate up to the maximum clocking frequency. The chip provides the capability of parallel operation of multiple chips with throughputs up to 800 MHz. The 0.8 μm triple level metal N-well CMOS chip has a complexity of 52000 transistors with a core area of 2.6×6.1 mm². Power dissipation is 2 W at 200 MHz and 5 V     

50 Gbit/s 2:1 multiplexer in 0.13 /spl mu/m CMOS technology

A fully integrated 2:1 multiplexer IC which operates at up to 50 Gbit/s data rate is presented. The MUX uses inductive shunt peaking and an output series inductor for higher bandwidth. The MUX directly drives the 50 /spl Omega/ load. The IC is fabricated in a 0.13 /spl mu/m bulk CMOS technology and draws 65 mA at 1.5 V supply voltage. The output voltage swing is 2/spl times/100 mV.     

Zeroth-order half-wave plates of LiNbO3 for integratedoptics applications at 1.55 μm

Reports on fabrication and characterization of the first zeroth-order half-wave plates of LiNbO₃ obtained by crystal ion slicing (CIS). Polarization rotation was demonstrated in 10-μm-thick freestanding LiNbO₃ films with 30-dB conversion ratios and negligible material loss. Polarization-independent performance was demonstrated in a hybrid-optic device comprising a CIS wave plate integrated with single-mode silica-based channel waveguides     

A kilohertz repetition rate 1.9 μm H2 Ramanoscillator

Raman conversion of a high-repetition-rate Q-switched Nd:YAG laser using a gaseous H₂ Raman medium is reported. With a H₂ cell placed in a focusing intracavity Raman oscillator, 3 W of average power at 1.9 μm was obtained from a 15-W 1.06-μm laser operating at 2 kHz. Although the pump beam was multimode, the Stokes output was diffraction limited. At kilohertz repetition rates, conversion efficiencies were improved with a flowing gas cell which substantially reduced the thermal lensing effect in the Raman medium. A rate equation approach was used to model the intracavity conversion process     

On the dynamics of population inversion for 3 μm Er3+lasers

A generalized model for 3-μm (⁴I_11/2 →⁴I_13/2)Er lasers is proposed. The essential energy transfer processes present in the single-doped Er ³⁺ systems (up-conversion from ⁴I_13/2, up-conversion from ⁴ I_11/2, cross-relaxation from ⁴S _3/2), as well as those present in Cr³⁺ codoped Er ³⁺ systems, are taken into account. In the frame of this model, the main features of 3 μm Er³⁺ lasers, such as long pulse or CW operation, the change of emission wavelength as a function of pumping conditions, and the effects of codoping with Ho³⁺ or Tm³⁺ ions, are explained     

Improving the RF performance of 0.18 μm CMOS with deep n-wellimplantation

The radio-frequency (RF) figures of merit of 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology are investigated by evaluating the unity-current-gain cutoff frequency (F _t) and maximum oscillation frequency (F_max). The device fabricated with an added deep n-well structure is shown to greatly enhance both the cutoff frequency and the maximum oscillation frequency, with negligible DC disturbance. Specifically, an 18% increase in F_t and 25% increase in F_max are achieved. Since the deep n-well implant can be easily adopted in a standard CMOS process, the approach appears to be very promising for future CMOS RF applications     

On-chip characterization of interconnect parameters and time delayin 0.18 μm CMOS technology for ULSI circuit applications

A real time, on-chip characterization technique is presented for extracting the interconnect parameters and for determining the associated time delays for ULSI circuit applications. To demonstrate the method, test chips were fabricated in both 0.25 and 0.18 μm CMOS technologies, using state of the art process technologies. Results obtained in these two cases are compared and the changing trends and issues for interconnect parameters in making the transition from the 0.25 μm to the 0.18 μm technologies are discussed. A completed look-up table in conjunction with a working analytic expression of the time delay enables accurate modeling and optimization of interconnect parameters and time delays for a given specification of chip performance     

Efficient silica-based Ho3+ fibre laser for 2 μmspectral region pumped at 1.15 μm

For the first time an Ho³⁺ silica fibre laser has been realised using a Bragg grating as the input coupler and a fibre pump source at 1.15 μm. The output power of 280 mW at 2 μm is to the authors' knowledge the highest value reported so far for Ho³⁺ silica fibre lasers     

An 8.29 mm2 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 μm CMOS Process

This paper presents a multi-mode decoder design for Quasi-Cyclic LDPC codes for Mobile WiMAX system. This chip can be operated in 19 kinds of modes specified in Mobile WiMAX system, including block sizes of 576,..., 2304. There are four proposed design techniques: reordering of the base matrix, overlapped operations of main computational units, early termination strategy and multi-mode design strategy. Based on overlapped decoding mechanism, the decoding latency can be reduced to 68.75% of non-overlapped method, and the hardware utilization ratio can be enhanced from 50% to 75%. Besides, the proposed early termination strategy can dynamically adjust the number of iterations when dealing with communication channels of different SNR values. The proposed multi-mode LDPC decoder design is implemented and fabricated in TSMC 0.13 mum 1.2 V 1P8M CMOS technology. The maximum operating frequency is measured 83.3 MHz and the corresponding power dissipation is 52 mW. The core size is 4.45 mm² and the die area only occupies 8.29 mm².