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为改善多传感器系统的状态估计性能,针对各传感器在测量数据联合处理时出现的测量周期不同,导致测量数据不同步的问题,采用数据压缩滤波的方法,使信息同步;由于各测向传感器仅测得目标的方位信息,采用将处理中心的状态估计和预测协方差阵反馈给各测向传感器的数据处理算法,减小各测向传感器局部估计的协方差阵,从而有效地提高系统的估计性能。仿真结果表明,利用提出的方法可使系统达到较好的估计效果。 相似文献
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《电子技术与软件工程》2016,(17)
随着高精度位移传感器以及加速度传感器的不断发展,油田低压测试仪器的发展也越来越朝着越来越轻量化、安全化的方向发展。本文针对基于光杆形变为原理的油田低压功图测试传感器的设计做了系统的阐述,该传感器采用了STM32系列单片机为主控芯片,前端载荷传感器采用了恒流源供电方式,降低了系统的功耗,而且提高了系统的载荷测试精度。位移传感器采用了通过高精度加速度传感器测试加速度来间接测量位移的原理,同时采用ISM-433MHz无线通讯频段进行数据传输,降低了传统有线测试仪器测试操作以及数据接收繁琐的问题。 相似文献
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基于多传感器数据融合的火灾预警系统 总被引:1,自引:0,他引:1
为避免火灾造成的严重损失,实现火灾早期报警,本系统通过对火灾发生过程和产物的研究比较,采用多种传感器对火灾发生初期火灾特征较明显的几个参数进行监测,并实时反馈回采集的数据。系统利用D-S证据理论对多传感器数据进行融合分析,实现对同一目标的判断;本系统通过利用D-S证据理论对多传感器数据融合的方法,不仅弥补了采用单一传感器的不足,而且很大程度上降低系统判断结果的不确定性,提高了系统预警的准确性和可靠性。 相似文献
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针对健康监测系统中不合理的传感器布置将影响传感器数据采集的有效性,降低监测系统的精度,以基于光纤Bragg光栅(FBG)传感器网络的结构健康监测系统为研究对象,采用逐步积累法,对系统中传感器网络的优化排布方法进行了研究。首先采用Ansys力学仿真软件建立了试验件的有限元模型并进行了加载试验,然后采用仿真获得的数据对传感器排布位置进行了优化,最后按照仿真研究获得的传感器优化位置在试验件上进行了试验研究。结果表明,试验同仿真结果具有很好的一致性,相对于原始传感器网络的排布方案,在相同的系统监测精度下,优化后的传感器排布方案可以采用更少的传感器;如果采用相同数量的传感器,优化后的传感器排布方案可以获得更高的监测精度。 相似文献
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为满足大视场、多个图像传感器同时使用、多光电图像传感器成像系统的响应一致性等技术需求,设计了一种大视场的成像系统.将先进先出缓存(FIFO)应用到数据传输技术当中,保证了系统多种图像数据同步实时输出;在基于低压差分信号(LVDS)技术上同时采用Camera link接口协议,设计了一种低成本、高速、稳定、简易的双目半导体金属氧化物有源传感器(CMOSAPS)成像系统,并深入探讨了系统的基本组成和工作原理;利用可编程门阵列完成自上而下的模块设计;并对系统部分工作时序进行了仿真,并进行板上调试;结果表明,本设计方案满足系统的大视场需求,为后续的图像采集工作打下了坚实的基础. 相似文献
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基亏DSP的多路音/视频采集处理系统设计 总被引:1,自引:0,他引:1
采用TI公司的TMS320DM642型数字媒体数字信号处理器(DSP)设计多路音/视频采集处理系统,实现实时处理4路模拟视频和音频输入、1路模拟/数字视频和1路模拟音频信号输出的功能,该系统可适应PAL/NTSC标准复合视频CVBS或分量视频Y/C格式的模拟信号和标准麦克风或立体声音频模拟输入,具有PAL/NTSC标准S端子或数字RGB模拟/数字信号输出和标准立体声音频模拟输出。并给出软/硬件设计原理和电路。 相似文献
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This paper covers a micro sensor analog signal processing circuit system(MASPS) chip with low power and a digital signal processing circuit board implementation including hardware connection and software design. Attention has been paid to incorporate the MASPS chip into the digital circuit board.The ultimate aim is to form a hybrid circuit used for mixed-signal processing,which can be applied to a micro sensor flow monitoring system. 相似文献
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Simoni A. Torelli G. Maloberti F. Sartori A. Plevridis S.E. Birbas A.N. 《Solid-State Circuits, IEEE Journal of》1995,30(7):800-806
A 64×64-pixel image sensor with full-frame analog memory and on-chip motion processor is presented. The processor consists of a charge amplifier and an analog subtractor. It uses the switched-capacitor technique and calculates the difference between the values of the signal on each pixel in successive frames. The rate can achieve up to 60 frames/s with limited area and power overhead. The analog memory required for the storage of the previous frame is implemented using implanted capacitors placed within the sensor array. Fabricated in a 1.2-μm standard CMOS process with an added metal 3 light-shielding layer, the circuit is fully functional and requires a total core area of 13 mm2 相似文献
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Kawahito S. Yoshida M. Sasaki M. Umehara K. Miyazaki D. Tadokoro Y. Murata K. Doushou S. Matsuzawa A. 《Solid-State Circuits, IEEE Journal of》1997,32(12):2030-2041
This paper presents a CMOS image sensor with on-chip compression using an analog two-dimensional discrete cosine transform (2-D DCT) processor and a variable quantization level analog-to-digital converter (ADC). The analog 2-D DCT processor is essentially suitable for the on-sensor image compression, since the analog image sensor signal can be directly processed. The small and low-power nature of the analog design allows us to achieve low-power, low-cost, one-chip digital video cameras. The 8×8-point analog 2-D DCT processor is designed with fully differential switched-capacitor circuits to obtain sufficient precision for video compression purposes. An imager array has a dedicated eight-channel parallel readout scheme for direct encoding with the analog 2-D DCT processor. The variable level quantization after the 2-D DCT can be performed by the ADC at the same time. A prototype CMOS image sensor integrating these core circuits for compression is implemented based on triple-metal double-polysilicon 0.35-μm CMOS technology. Image encoding using the implemented analog 2-D DCT processor to the image captured by the sensor is successfully performed. The maximum peak signal-to-noise ratio (PSNR) is 36.7 dB 相似文献
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《Solid-State Circuits, IEEE Journal of》1982,17(6):1039-1044
Presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCFs, an AGC circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 /spl mu/m line double polysilicon gate NMOS process. Chip size is 7.14/spl times/6.51 mm. The circuit operates on /spl plusmn/5 V power supplies. Typical power consumption is 270 mW. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size. 相似文献