Improved 94-GHz GaAs mixer diodes using gold-copper alloy whiskers

Reduced conversion loss and improved yield and reliability have been obtained in 94-GHz GaAs mixer diodes by substituting a gold-copper alloy wire for the conventional phosphor-bronze whisker.     

Fully integrated 60-GHz single-ended resistive mixer in 90-nm CMOS technology

This letter presents the design and characterization of a fully integrated 60-GHz single-ended resistive mixer in a 90-nm CMOS technology. A conversion loss of 11.6dB, 1-dB compression point of 6dBm and IIP3 of 16.5dBm were measured with a local oscillator (LO) power of 4dBm and zero drain bias. The possibility of improvement in IIP3 with selective drain bias has been verified. A 3-dB improvement in IIP3 was obtained with 150-mV dc voltage applied at the drain. Microstrip transmission lines are used to realize matching and filtering at LO and radio frequency ports.     

Design and fabrication of 94 GHz MMIC single balanced resistive mixer without IF balun

In this paper, a 94 GHz microwave monolithic integrated circuit (MMIC) single balanced resistive mixer affording high LO-to-RF isolation was designed without an IF balun. The single balanced resistive mixer, which does not require an external IF balun, was designed using a 0.1 μm InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (HEMT). The designed MMIC single balanced resistive mixer was fabricated using the 0.1 μm MHEMT MMIC process. From the measurement, conversion loss of the single balanced resistive mixer was 14.7 dB at an LO power of 10 dBm. The P_1 dB (1 dB compression point) values of the input and output were 10 dBm and −5.3 dBm, respectively. The LO-to-RF isolation of the single balanced resistive mixer was −35.2 dB at 94.03 GHz. The single balanced resistive mixer in this work provided high LO-to-RF isolation without an IF balun.     

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

Column-based dynamic power supply has been integrated into a high-frequency 70-Mb SRAM design that is fabricated on a high-performance 65-nm CMOS technology. The fully synchronized design achieves a 3-GHz operating frequency at 1.1-V power supply. The power supply at SRAM cell array is dynamically switched between two different voltage levels during READ and WRITE operations. Silicon measurement has proven this method to be effective in achieving both good cell READ and WRITE margins, while lowering the overall SRAM leakage power consumption.     

毫米波宽带高中频单平衡混频器设计与实现

针对毫米波宽带通信、雷达和测试仪器领域的应用需求,提出一种E波段宽带高中频(IF)单平衡混频器。射频(RF)及本振(LO)信号通过多分支宽带加宽波导正交耦合器输入,通过鳍线过渡结构将信号从波导传输模式过渡到微带模式,并提供宽带中频信号及直流接地回路;中频输出低通滤波器可有效抑制LO及RF信号,并为其提供等效接地回路。利用肖特基二极管的非线性实现混频,并通过微带匹配电路最终实现宽带低损耗混频效果。混频器采用57.6、62.4、67.2 GHz 3个点频本振,将67~85 GHz的射频信号分段下变频至9.4~17.8 GHz的中频范围内。测试结果表明,在67~85 GHz射频频率范围内,射频输入功率为-15 dBm,本振输入功率为12 dBm时,混频器变频损耗为7.1~10.1 dB,对组合杂散的抑制在36 dBc以上。     

High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology

The electrical characteristics of the parasitic vertical NPN (V-NPN) BJT available in deep n-well 0.18-/spl mu/m CMOS technology are presented. It has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of Early voltage, about 2 GHz of cutoff frequency, and about 4 GHz of maximum oscillation frequency at room temperature. The corner frequency of 1/f noise is lower than 4 kHz at 0.5 mA of collector current. The double-balanced RF mixer using V-NPN shows almost free 1/f noise as well as an order of magnitude smaller dc offset compared with CMOS circuit and 12 dB flat gain almost up to the cutoff frequency. The V-NPN operational amplifier for baseband analog circuits has higher voltage gain and better input noise and input offset performance than the CMOS ones at the identical current. These circuits using V-NPN provide the possibility of high-performance direct conversion receiver implementation in CMOS technology.     

A 0.3-25-GHz ultra-wideband mixer using commercial 0.18-/spl mu/m CMOS technology

An ultra-wideband mixer using standard complementary metal oxide semiconductor (CMOS) technology was first proposed in this paper. This broadband mixer achieves measured conversion gain of 11 /spl plusmn/ 1.5 dB with a bandwidth of 0.3 to 25 GHz. The mixer was fabricated in a commercial 0.18-/spl mu/m CMOS technology and demonstrated the highest frequency and bandwidth of operation. It also presented better gain-bandwidth-product performance compared with that of GaAs-based HBT technologies. The chip area is 0.8 /spl times/ 1 mm/sup 2/.     

High-performance millimetre-wave mixer diodes fabricated using a deep mesa etch approach

Schottky-barrier junction mixer diodes compatible with monolithic integration have been fabricated on semi-insulating GaAs substrates using buried VPE n+ layers and deep mesa etch processing. A 590 GHz cutoff frequency was determined using modified DeLoach analysis and fin-line chip mounting. A 5.3 dB (SSB) noise figure and a 4.8 dB conversion loss were obtained at 35 GHz for a pair of chips in a balanced microstrip mixer.     

Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology

In this paper, we present the design of a 32-b arithmetic and log unit (ALU) that allows low-power operation while supporting a design-for-test (DFT) scheme for delay-fault testability. The low-power techniques allow for 18% reduction in ALU total energy for 180-nm bulk CMOS technology with minimal performance degradation. In addition, there is a 22% reduction in standby mode leakage power and 23% lower peak current demand. In the test mode, we employ a built-in DFT scheme that can detect delay faults while reducing the test-mode automatic test equipment clock frequency.     

High-performance V-band cascode HEMT mixer and downconverter module

A high-performance V-band cascode HEMT mixer is presented together with a compact downconverter module integrating the mixer with other receiver MMICs. The cascode mixer was optimized for conversion gain and/or linearity by employing the low-pass interstage networks and by optimizing the bias voltages. The low-pass interstage network effectively filters out the unwanted harmonics and spurious signals, and therefore, enhances the gain and the linearity of the cascode mixer. On a two-tone test, the cascode mixer showed a high conversion gain of 6.3 dB with an LO power of 2.6 dBm at 60 GHz. When the gate bias to the upper common-gate HEMT was tuned for the intermodulation distortion "sweet spot" theoretically predicted by the authors , the mixer showed a high third-order intercept point of 11.2 dBm with a decent gain of 4.1 dB under a small DC power consumption of 8 mW. To benchmark the performance of the cascode mixer of this work, a waveguide-based compact V-band downconverter module was built by integrating the mixer with an MMIC LNA, a VCO, and a LO driving amplifier. The downconverter module showed a conversion gain higher than 20 dB from 57.5 to 61.7 GHz. This paper shows the potential of the cascode FET mixer for high-performance compact downconverter applications at millimeter-wave frequencies.     

High-performance low-power CMOS memories using silicon-on-sapphire technology

Complementary MOS silicon-on-sapphire inverters fabricated using silicon-gate technology and 5-/spl mu/m channel-length devices has achieved nanosecond propagation delays and picojoule dynamic power-x delay products. In addition to high switching speed and low dynamic power, inverters with low leakage currents and therefore low quiescent power have been obtained. Two complex CMOS/SOS memories that realize the performance attributes of the individual inverters have been fabricated. An aluminium-gate 256-bit fully decoded static random-access memory features a typical access time of 50 ns at 10 V with a power dissipation of 0.4 /spl mu/W/bit (quiescent) and 10 /spl mu/W/bit (dynamic). The access time at 5 V is typically 95 ns. A silicon-gate 256-bit dynamic shift register features operation at clock signals of 200 MHz at 10 V and 75 MHz at 5 V. The dynamic power dissipation at 50 MHz and 5 V is typically 90 /spl mu/W/bit.     

A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS

A 1.5-V 256-263 8-modulus prescaler and a 1.5-V integer-N phase-locked loop (PLL) with eight different output frequencies have been implemented in a 0.13-mum foundry CMOS process. The synchronous divide-by-4/5 circuit uses current mode logic (CML) D-flip-flops with resistive loads to achieve 21-GHz maximum operating frequency at input power of 0 dBm. The divider is used to implement an 8-modulus prescaler consuming 6-mA current and 9-mW power. This extremely low power consumption is achieved by radically decreasing the sizes of transistors in the divider. Utilizing the prescaler, a charge-pump integer-N PLL has been demonstrated with 20-GHz output frequency. The in-band phase noise of the PLL at 60-kHz offset and out-of-band phase noise at 10-MHz offset are ~-80 dBc/Hz and -116.1 dBc/Hz, respectively. The locking range is from 20.05 to 21 GHz. The PLL consumes 15-mA current and 22.5-mW power from a 1.5-V power supply.     

10-GHz Si bipolar amplifier and mixer ICs for coherent opticalsystems

Using a 30-GHz f_T silicon bipolar process, 10-GHz amplifier and mixer ICs for a multigigabit-per-second coherent optical-fiber communication system were fabricated. The dual-feedback amplifier with triple Darlington achieves a 10-GHz bandwidth and 20-dB gain. The Gilbert-cell mixer operates up to 10 GHz with a 10-dB conversion loss. The simulation technique, used for the design of these ICs includes an improved interconnect line model for the high-frequency region. The 10-GHz amplifier has a 1-mm² chip size and 210-mW power dissipation. The mixer has 2-mm² chip size and 550-mW power dissipation     

A K-band down-conversion mixer with 1.4-GHz bandwidth in 0.13-/spl mu/m CMOS technology

A low power and low voltage down conversion mixer working at K-band is designed and fabricated in a 0.13/spl mu/m CMOS logic process. The mixer down converts RF signals from 19GHz to 2.7GHz intermediate frequency. The mixer achieves a conversion gain of 1dB, a very low single side band noise figure of 9dB and third order intermodulation point of -2dBm, while consuming 6.9mW power from a 1.2V supply. The 3-dB conversion gain bandwidth is 1.4GHz, which is almost 50% of the IF. This mixer with small frequency re-tuning can be used for ultra-wide band radars operating in the 22-29GHz band.     

Metrology technology for the 70-nm node: process control throughamplification and averaging microscopic changes

Below the 70-nm node feature sizes and aspect ratios will require great advances in metrology and defect detection capability. Although the International Technology Roadmap for Semiconductors (ITRS) prediction becomes more aggressive with each revision, isolate gate lengths for the 70-nm node are predicted to be below 40 nm for microprocessors (see 2000 ITRS). 70 nm and below feature sizes and high aspect ratios will be characteristic of on-chip interconnect. Memory devices will achieve line densities that will drive all areas of metrology. The device performance required for increasing clock speed and reducing leakage current has been driving new gate stack materials development which is expected to be ready for manufacture at this node and below. On-chip interconnect will have integrated low κ dielectric, copper metal lines, and copper diffusion barrier layer materials predicted by the roadmap will require interconnect design advancements to meet increased clock speeds even if the present rate of advance in clock speed decreases. In this paper, the key metrology and defect detection trends for wafer manufacture are covered. The best available information on critical dimension, gate stack, and interconnect measurement and data management are described in light of the need to obtain statistically relevant information from microscopic features     

60 GHz MMIC double balanced Gilbert mixer in mHEMT technology with integrated RF, LO and IF baluns

A 60 GHz MMIC double balanced Gilbert mixer (DBGM) with integrated RF, LO and IF baluns has been designed, fabricated in an mHEMT MMIC technology and characterised with probed measurements. Although a standard mixer topology for integrated circuits in the low gigahertz region, the DBGM has had very little impact in the millimetre-wave range. To the authors' knowledge, the presented DBGM operates at the highest RF frequency ever published for any FET-based Gilbert type mixer, double or single balanced. A measured down conversion gain of 1.5 dB at 60 GHz is obtained with a DC power consumption of 300 mW. Further, IF bandwidth, isolation between the LO, RF and IF ports, 1 dB compression point for the RF input, and LO input power is presented     

Remote sensing of heart rate and patterns of respiration on a stationary subject using 94-GHz millimeter-wave interferometry

Using continuous wave, 94-GHz millimeter-wave interferometry, a signal representing chest wall motion can be obtained that contains both the heart rate and respiration patterns of a human subject. These components have to be separated from each other in the received signal. Our method was to use the quadrature and in-phase components of the signal, after removing the mean of each, to find the phase, unwrap it, and convert it to a displacement measurement. Using this, the power spectrum was examined for peaks, which corresponded to the heart rate and respiration rate. The displacement waveform of the chest was also analyzed for discrete heartbeats using a novel wavelet decomposition technique.     

A 243-GHz F/sub t/ and 208-GHz F/sub max/, 90-nm SOI CMOS SoC technology with low-power mm-wave digital and RF circuit capability

A 90-nm silicon-on-insulator (SOI) CMOS system on-chip integrates high-performance FETs with 243-GHz F/sub t/, 208-GHz F/sub max/, 1.45-mS//spl mu/m gm, and sub 1.1-dB NFmin up to 26 GHz. Inductor Q of 20, VNCAP of 1.8-fF//spl mu/m/sup 2/, varactor with a tuning range as high as 25:1, and a low-loss microstrip. Transmission lines were successfully integrated without extra masks and processing steps. SOI and its low parasitic junction capacitance enables this high level of performance and will expand the use of CMOS for millimeter-wave applications.     

High-performance wafer-bonded bottom-emitting 850-nm VCSEL's onundoped GaP and sapphire substrates

We have demonstrated high performance wafer-bonded bottom-emitting 850-nm vertical-cavity surface-emitting lasers (VCSEL's) on transparent substrates. The free-carrier absorption of the substrate was avoided by using undoped GaP or sapphire substrates. The maximum external quantum efficiency approaches 48% while the threshold current remains as low as 550 μA for the 6×6 μm² VCSEL's bonded on GaP substrates. VCSEL's with 8.6×8.6 μm² aperture bonded on sapphire substrates also exhibit threshold currents of 800 μA and external quantum efficiencies of 33.2%. The difference in efficiency between these two devices results from the change of the refractive index of the exit medium