Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.This research was supported by the National Science Foundation under Grant No. MIP-9200526. Parts of this paper were published in preliminary form in Proc. 23rd Symp. Fault-Tolerant Computing, Toulouse, June 1993, and in Proc. 31st Design Automation Conf, San Diego, June 1994.     

Vector sets for exhaustive testing of logic circuits

(L, d)-universal sets are useful for exhaustively testing logic circuits with a large number of functional components, designed so that every functional component depends on at most d inputs. Randomized and deterministic constructions of ( L, d)-universal test sets are presented, and lower and upper bounds on the optimal sizes of such sets are proven. It is also proven that the design of an optimal exhaustive test set for an arbitrary logic circuit is an NP-complete problem     

Fast test generation and partial testing for combinational logic circuits

A simple, yet effective fast test generation algorithm by using the real value boolean difference is given for combinational logic circuits along with a short review of several fast test generation algorithms. Because no recursive operation is involved, it can be carried out as a parallel algorithm. In the second part of this paper, the concept of the partial testing is discussed. A new partial testing method, weighted point testing, is presented in this paper. Every line or node in the combinational logic circuit has a weight assigned to it. The weight at a point is determined by several factors, such as the fault occurrence found by experience or prior-knowledges, the number of fan-in or fan-out at that point, and the depth of the point in the circuit. Only those points with relatively high weights are considered in the test generation and testing. Because testing is more effectively done and directed to the point, the test coverage is higher.     

BILCO: built in testing method for combinational logic circuits

The testing of digital logic circuits has become quite complex owing to miniaturisation and its associated increase in circuit function per unit area. Methods have been devised for testing ASIC products and, latterly, board level products. A new method (BILCO) is presented for probing asynchronous combinational logic circuits using a novel development of scan path principles     

High-speed testing of Josephson logic circuits by an on-chip signal-pattern generator

We have developed an on-chip signal-pattern generator (SPG) for high-speed testing of latching-type Josephson logic circuits. The basis of the SPG is using a feedback shift register, in which the complement output of the last-stage LATCH gate (a D flip-flop) is fed back to the first-stage LATCH gate. Since the SPG consists of only LATCH gates and requires no external input signal, the design and high-speed operation are greatly simplified. We performed a high-speed measurement of the 1-bit SPG and found that the SPG has the potential to operate at a speed of more than 4.6 GHz. We also demonstrated a high-speed testing of a 2-bit logic circuit with the 2-bit SPG up to a clock frequency of 1 GHz.     

Self-timed logic circuits

Self-timed and asynchronous design techniques are currently proposed as a vehicle for pushing digital integrated circuits to higher levels of density and performance. The arguments for and against the adoption of these techniques are presented with illustrations from practical development projects. Some of the key principles behind self-timed operation are reviewed. Design tools to enable complex practical applications to be engineered are considered. For engineers who wish to find out more a selection of key references is provided     

Digital logic circuits

Recent progress in Josephson digital logic circuits is described. It is noted that changing the junction material from a lead alloy to niobium has dramatically improved process reliability, and that high-speed, low-power operations have been demonstrated at large-scale integrated-circuit levels. The first Josephson microprocessor, operated at 770 MHz, verified the potential of Josephson devices for future digital elements. The possibilities of the ultrafast Josephson computer, previously shelved because of a number of problems, are being actively reconsidered. The performance anticipated for Josephson digital circuits using high-temperature superconducting materials is also discussed     

Dynamic logic CMOS circuits

A structure of dynamic CMOS logic based on the direct interconnection of p-channel logic and n-channel logic dynamic gates is reported. Prevention of glitches and other circuit problems are discussed. Application to a 16-bit parallel-adder design resulted in improved speed as well as important savings in layout area when compared to standard static design.     

Self-biasing Josephson logic circuits

A self-biasing network for Josephson logic circuits that permits wide variations in junction critical currents, resistors, and power supply voltage is presented. The self-biasing network automatically switches resistors in or out to make the gate currents track with the critical currents of the logic gates. Results of Monte Carlo statistical analyses of the tolerances of this scheme are presented as a function of amount of correlation between the critical currents of the logic device and the biasing network, amount of systematic variation on a chip, and number of junctions used in the biasing network. Results indicate that almost a factor of two larger variations in the critical currents of the Josephson junctions can be tolerated when the self-biasing network is used, without adverse impact on the gate delays and the power dissipation.     

Josephson nonlatching logic circuits

The authors describe nonlatching logic circuits that can be designed using Josephson junctions as the switching elements. The circuits require no current resetting and can be switched between their two logic states with a subnanosecond delay time. The switching behavior has been simulated numerically. The choice of parameters and junction types is analyzed. The distinctive features which make these circuits attractive are discussed.     

Fault characterization, testing considerations, and design fortestability of BiCMOS logic circuits

The results of a simulation-based fault characterization study of BiCMOS logic circuits are given. Based on the fault characterization results, the authors have studied different techniques for testing BiCMOS logic circuits. The effectiveness of stuck-at fault testing, stuck-open fault testing, delay fault testing, and current testing in achieving a high level of defect coverage is studied. A novel BiCMOS circuit structure that improves the testability of BiCMOS digital circuits is presented     

All-refractory Josephson logic circuits

A process for the fabrication of Josephson integrated circuits is described which uses only refractory materials. The Josephson devices are Nb-Si-Nb tunnel junctions which are formed in the initial phase of the process. After depositing a Nb-Si-Nb `trilayer' over the entire substrate, the individual devices are isolated by the selective niobium anodization process (SNAP). Other materials used are molybdenum for the normal resistors and bias-sputtered SiO/SUB 2/ for additional insulator layers. The process uses only five photolithographic steps to produce circuits of the direct-coupled isolation type. This simplicity is achieved by using some layers for multiple purposes and by fabricating components with different functional purposes in a single step. For example, the lower electrode of the Josephson devices also functions as the ground plane and the contacts to the ground plane are actually large-area Josephson junctions formed simultaneously with the active devices. Low capacitance junctions (~0.025 pF//spl mu/m/SUP 2/) are produced with good uniformity.     

Reliability evaluation of logic circuits

An important guide in the project of logic circuits is the ability to estimate rightly its reliability. In this paper a new type of analysis is presented, by following the references [1], [2], [3] and the method implemented by [4]. This is applicable to all logic circuits, combinational or sequential and by this new structure a reliability matrix is obtained.     

Characterization of integrated logic circuits

The characterization of integrated logic circuits must be accomplished in a manner which fully accounts for the circuit's nonlinear behavior and is amenable to experimental verification. The approach taken in this paper is to describe both the dc and the transient performance of the circuit by developing nonlinear equivalents of the 2-port "black box" parameters used in specifying linear networks. Such terminal parameter characterization has the obvious advantage of eliminating the need to probe the integrated circuit for testing purposes. In addition, knowledge of terminal performance is a necessity when the circuit is studied from a system point of view. In this paper an emitter-coupled logic circuit is used as an example to illustrate the analysis techniques. After accomplishing the terminal parameter characterization of this circuit, attention is directed towards using these results to establish a design procedure. To this end the relationship that exists between power consumption and the circuit safety margins is explored, and the minimum power-delay time product is derived. The analysis accounts for the parasitics which are present in a monolithic integrated circuit and illustrates the use of the nonlinear transistor model.     

Comparison of MOSFET logic circuits

Linear load, depletion-mode load, four-phase dynamic, and complementary MOSFET logic circuits are compared on the basis of power, delay, and density for two specific master slice layouts. The circuits were designed in a common technology base, and normalized power and delay characteristics were calculated by simulation. Chips of 1280 circuits were designed in images having one and two layers of metal, and power versus delay curves were calculated. The effect of an insulating substrate was also considered.     

Current-mode CMOS multiple-valued logic circuits

Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we review several of the current-mode CMOS multiple-valued logic (MVL) circuits that we have studied over the past decade. These circuits include a simple current threshold comparator, current-mode MVL encoders and decoders, current-mode quaternary threshold logic full adders (QFAs), current-mode MVL latches, current-mode latched QFA circuits, and current-mode analog-to-quaternary converter circuits. Each of these circuits is presented and its performance described     

Dynamic-type CMOS four-valued logic circuits

We first briefly introduce the various kinds of basic CMOS four-valued logic circuit that can be suitably employed for circuits with clock pulses. Using these, the design of multiple-valued MAX and MIN circuits with many inputs, each of which has two quaternary figures, are developed. It is shown that the number of MOS transistors required for these circuits can be reduced in comparison to binary circuits having equivalent functions. Successful simulation results using SPICE-2 for the circuit operations are given.     

Feedthrough in emitter-coupled logic circuits

Emitter coupled logic circuits transient noise behavior is examined. The mechanisms and causes of feedthrough are analyzed using, first, approximate expressions and, second, an accurate model. The experimental observations of feedthrough give ample evidence of good agreement between the theoretical and computational results. An accurate appraisal of the causes of feedthrough, such as C/SUB b//SUB e/, C/SUB b//SUB c/, c/SUB i//SUB d/, C/SUB i//SUB t/, C/SUB p/, and C/SUB c//SUB u//SUB s/ determine the main factors that offer scope for improvement.