基于片上系统的时钟复位设计

从方法优化和电路设计入手,提出了基于片上系统(SOC)的复位方法和时钟复位电路.设计了片外按键复位电路、片内上电电路、晶振控制电路、片内RC低频时钟电路、槽脉冲产生电路、分频延时电路、时钟切换电路及异步复位同步释放电路等电路模块.以上电路模块构成了片上系统的时钟复位电路,形成了特定的电路时钟复位系统.该时钟复位系统将片外按键复位与片内上电复位结合起来,形成多重复位设计,相比单纯按键复位更智能,相比单纯上电复位则更可靠.另外,该时钟复位系统还采用了片内RC振荡时钟电路等一系列电路,借助片内RC时钟实现对芯片的延时复位,进而在保证复位期间寄存器得到正确初始化的同时,还使得芯片能够始终处在稳定的晶振时钟下正常工作.相比传统的时钟复位电路,该时钟复位系统既便捷,又保证了系统初始化和系统工作的可靠性.     

4Gbps低功耗并串转换CMOS集成电路

为满足传输数据的高速低功耗的要求,文章设计了一种半速率时钟驱动的二级多路选择开关式的10：1并串转换器。第一级为两个5：1的并行串化器,共用一个多相发生器。多相发生器由五个动态D触发器构成。第二级为一个2：1的并行串化器。采用半速率时钟、多路选择开关结构降低了大部分电路的工作频率,降低了工艺要求,也降低了功耗。通过调整时钟与数据间的相位关系,提高相位裕度,降低了数据抖动。采用1．8V 0．18μm CMOS工艺进行设计。用Hspice仿真器在各种PVT情况下做了仿真,结果表明该转换器在输出4Gbps数据时平均功耗为395μW,抖动18s^-1．     

A synchronous approach for clocking VLSI systems

Presents a synchronous solution for clocking VLSI systems organized as distributed systems. This solution avoids the drawbacks of the self-timed approach. These VLSI systems are constituted of modules which represent synchronous areas driven by their own fast clock, interconnected by a synchronous communication mechanism driven by a slow clock. In order to avoid the risk of metastability in flip-flop between the modules and the communication mechanism, the author suggests to resynchronize the phase of each module clock on the transitions of the communication clock by a phase locked loop circuitry added to each module.     

High-speed CMOS adder and multiplier modules for digital signalprocessing in a semicustom environment

For the realization of digital filters in a semicustom environment, high-performance adder and multiplier modules have been developed. These modules define the performance limits for digital finite impulse response (FIR) filters. The Gate Forest semicustom environment is a sea-of-gates-type transistor array. It supports the implementation of dynamic (domino) CMOS logic circuits. The circuit-design technique is applicable to compact high-speed designs. The realized dynamic adder architecture consists of a 2-b group adder and a Manchester carry chain (MCC). For an N-b addition this results in a N/2-b carry lookahead path. This dynamic adder scheme can be expanded into 4-b group adder modules. The multiplier module is a combination of a modified Booth-coded static adder array with a final dynamic MCC adder. The multiplier is clocked with a single (symmetric) clock signal. The clock signal is divided into a precharge pulse, in which the static part of the multiplier added array is evaluated, and an evaluation phase for the generation of the multiplication result (least significant bits). A 16-b×16-b multiplier based on this architecture runs with a 40-MHz system clock. The first chips have been processed in a 2-μm CMOS double-metal technology     

A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains

A robust, scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which is useful for transferring data between modules operating in different clock domains is presented. The architecture supports correct operation in applications where multiple clock cycles of latency exist between the data producer, FIFO, and the data consumer; and with arbitrary clock frequency changes, halting, and restarting in either or both clock domains. The architecture is demonstrated in both a 0.18- mum CMOS full-custom design and a 0.18-mum CMOS standard cell design used in a globally asynchronous locally synchronous array processor. It achieves 580-MHz operation and 10.3-mW power dissipation while performing simultaneous FIFO read and write operations at 1.8 V.     

基于FPGA的数字电子钟设计

采用FPGA进行的数字电路设计具有更大的灵活性和通用性,已成为目前数字电路设计的主流方法之一.本文给出一种基于FPGA的数字钟设计方案.该方案采用VHDL设计底层模块,采用电路原理图设计顶层系统.整个系统在QuartusⅡ开发平台上完成设计、编译和仿真,并在FPGA硬件实验箱上进行测试.测试结果表明该设计方案切实可行.     

An all-digital phase-locked loop (ADPLL)-based clock recoverycircuit

A new algorithm for all-digital phase-locked loops (ADPLL) with fast acquisition and large pulling range is presented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell. These modules have been designed and verified on a 0.6-μm CMOS process. Test results are summarized as follows: 1) the proposed ADPLL can satisfy full locked bandwidth and fast acquisition within one data transition; 2) the on-chip clock generator can generate any target clock rate f_clock ; and 3) the function of nonreturn-to-zero clock recovery has a maximum f_clock/4 recovering capability with a locking range of (τ_input±τ_input/2)) where τ _input is the input period     

一种基于分频链的时钟校准方法

针对晶体振荡器的温漂特性,设计了一种基于分频链的时钟校准算法。在不改变晶体振荡器的情况下可调节时钟频率,校准精度达±0.25ppm,校准范围±32ppm,通过多次实验分析,用Verilog-HDL语言编写全部模块,在modelsim6.2b软件中实现模块仿真。全部功能正常实现,符合设计要求。     

A High-Speed Pseudorandom Test Pattern Generator

Real-time built-in self-testing (BIST) of digital devices that incorporate functional modules of various speed is considered. A method of designing a pattern generator is suggested. This generator is capable of forming pseudorandom test patterns both with the normal speed (one test vector per clock cycle) and with a speed several times higher (several test vectors per clock cycle). With these generators, at-speed testing of multichip module components can be performed to detect both stuck-at and ac faults.     

基于FPGA的梯度自适应格型滤波器设计

对于高灵敏度的数字信号的处理需要使用数值特性优良的格型滤波器。利用EDA技术设计了梯度自适应格型滤波器。实验表明更新反射系数的步长应随着模块数的增加逐步减小。对梯度自适应格型滤波器的单独模块采用驰豫超前技术设计,显著提高了FPGA的运行时钟速率。     

Pausible clocking-based heterogeneous systems

This paper describes a novel communication scheme, which is guaranteed to be free of synchronization failures, amongst multiple synchronous and asynchronous modules operating independently. In this scheme, communication between every pair of modules is done through an asynchronous first-in first-out (FIFO) channel; communication between a module and the FIFO is done using a request/acknowledge handshaking. Synchronization of handshake signals to the local module clock is done in an unconventional way-the local clock built out of a ring oscillator is paused or stretched, if necessary, to ensure that the handshake signal satisfies setup and hold time constraints with respect to the local clock. In order to validate this scheme, we implemented a test chip in 0.5-μm CMOS. This chip is designed as a ring, composed of two synchronous modules, an asynchronous module, and two asynchronous FIFOs. Each module functions as a receiver to one module and a sender to another module. Test results show that the chip functions reliably up to 456 MHz     

芯片级原子钟专用射频模块设计

为进一步实现原子钟的低功耗、微型化,设计了一种用于85Rb原子钟的专用射频模块芯片。该芯片采用了交叉耦合差分结构,利用串联的平面集成螺旋电感达到3 GHz的输出频率,同时采用了累积型MOS变容管,实现控制电压对于输出频率的单调调节。最终对设计芯片进行了仿真测试,并完成了流片与封装,基本达到了设计指标。     

QSERL: quasi-static energy recovery logic

A new quasi-static energy recovery logic family (QSERL) using the principle of adiabatic switching is proposed in this paper. Most of the previously proposed adiabatic logic styles are dynamic and require complex clocking schemes. The proposed QSERL uses two complementary sinusoidal supply clocks and resembles the behavior of static CMOS. Thus, switching activity is significantly lower than dynamic logic. In addition, QSERL circuits can be directly derived from static CMOS circuits. A high-efficiency clock generation circuitry, which generates two complementary sinusoidal clocks compatible to QSERL, is also presented in this paper. The adiabatic clock circuitry locks the frequency of clock signals, which makes it possible to integrate adiabatic modules into a VLSI system. We have designed an 8×8 carry-save multiplier using QSERL logic and two phase sinusoidal clocks. SPICE simulation shows that the QSERL multiplier can save 34% of energy over static CMOS multiplier at 100 MHz     

An Inexpensive Modular Pulse Generating System

A multiple channel pulse generator is described, consisting of a clock module and several identical output modules. Clock frequency can be varied continuously from 0.003 Hz to 100 Hz. Output pulses have continuously variable duration, can be positioned anywhere within the timing cycle, and their amplitude is variable from +5 to -5 V.     

Interfacing synchronous and asynchronous modules within ahigh-speed pipeline

This paper describes a new technique for integrating asynchronous modules within a high-speed synchronous pipeline. Our design eliminates potential metastability problems by using a clock generated by a stoppable ring oscillator, which is capable of driving the large clock load found in present day microprocessors. Using the ATACS design tool, we designed highly optimized transistor-level circuits to control the ring oscillator and generate the clock and handshake signals with minimal overhead. Our interface architecture requires no redesign of the synchronous circuitry. Incorporating asynchronous modules in a high-speed pipeline improves performance by exploiting data-dependent delay variations. Since the speed of the synchronous circuitry tracks the speed of the ring oscillator under different processes, temperatures, and voltages, the entire chip operates at the speed dictated by the current operating conditions, rather than being governed by the worst case conditions. These two factors together can lead to a significant improvement in average-case performance. The interface design is simulated using the 0.6-μm HP CMOS14B process in HSPICE     

Managing signal integrity [PCB design]

As system clock rates race to 100 MHz and beyond, designers of printed-circuit boards and multichip modules must watch out for such high-speed effects as ground bounce, ringing, reflections, and crosstalk. The author describes how today's high-speed printed-circuit boards and multichip modules require integrated design systems that include signal integrity analysis tools     

激光抽运铯原子钟的计算机模型

介绍了光抽运铯原子钟计算机模型系统的基本结构体系,该计算机模型系统包括铯原子炉、抽运和检测激光、Ramsey微波作用腔、C场、荧光检测系统等程序模块。利用这个计算机模型系统,对光抽运小型铯原子钟在一些极端条件下的情形进行了研究,如抽运激光功率偏低,有效原子的速度分布特别窄,微波功率远大于最佳微波功率等条件下,得到了一些有意义的结果。     

All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs

High-performance clocking of intellectual property (IP) modules, within a skew budget, is becoming difficult in deep sub-micron technologies. In this work, we propose a novel and all-digital synchronous design method for point-to-point communications, using two stages of interfacing registers and locally delayed clock with phase adjustments. This design is free from synchronizers and clock-data mismatch problems. Moreover, communicating modules run at frequencies which are virtually independent of the clock skew. We also provide a comprehensive case-wise mathematical analysis to facilitate design automation for synthesizing such designs as standard cells. An overall improvement in skew tolerance of up to n times (where n is the number of registers used), when compared to conventional designs, is achieved when the skew orientation is known and n/2 times if the skew orientation is unknown. Improvement in skew tolerance is validated using gate level simulations with the 0.18 μm TSMC CMOS technology. A prototype implementation of the proposed design using a Virtex-II Pro FPGA from Xilinx validates the claim that such designs allow a fast module to communicate with a slow module without constraining their frequencies.     

Kinetis 系列MCU时钟系统结构与配置研究

内嵌ARMCortex TM-M核的Kinetis系列微控制器具有复杂的时钟系统,时钟系统中多功能时钟发生器、锁相环、锁频环、晶振系统等功能模块协调工作时能为应用系统提供稳定的时钟源。通过对K60时钟系统的结构和配置方法的剖析,以及对多功能时钟发生器运行机制的梳理,提出了时钟源性能的测试方法以及芯片系统各功能模块时钟源的选择方法,为Kinetis相关芯片应用设计过程中的时钟系统配置以及时钟源选择提供了借鉴与参考。     

A multiple clocking scheme for low-power RTL design

This paper presents a resource allocation technique to design low-power register-transfer-level datapaths. The basis of this technique is to use a multiple clocking scheme of n nonoverlapping clocks, by dividing the frequency f of a single clock into n cycles, to partition the circuit into n disjoint modules and assign each module to a distinct clock, and to operate each module only during its corresponding duty cycle, thus clocking each module by a frequency f/n to reduce power. However, the overall effective frequency of the circuit remains f, i.e., the single clock frequency. Further power reduction is also obtained by tradeoffs between voltage, power, and delay across multiple clock partitions. Power savings up to 50% of the proposed multiple clocking scheme in comparison to single gated clock designs are also reported