基于跨导运算放大器的可重构模拟电路及应用设计

常规的粗粒度可重构模拟电路灵活性不高,而且可重构模拟单元(CAB)结构较为复杂。针对此类问题,该文改进并设计了一种新的基于OTA的可重构模拟电路。该电路设计方案降低了CAB的复杂度,提高了CAB的使用效率。该文方法的有效性通过3个模拟设计实例(二阶低通滤波器、高通滤波器和三阶巴特沃思低通滤波器)的设计加以验证。实验结果表明,所提出的方法正确有效,可以较好地兼顾CAB资源与所要求功能的平衡。     

An insect vision-based motion detection chip

The architectural and circuit design aspects of a mixed analog/digital very large scale integration (VLSI) motion detection chip based on models of the insect visual system are described. The chip comprises two one-dimensional 64-cell arrays as well as front-end analog circuitry for early visual processing and digital control circuits. Each analog processing cell comprises a photodetector, circuits for spatial averaging and multiplicative noise cancellation, differentiation, and thresholding. The operation and configuration of the analog cells is controlled by digital circuits, thus implementing a reconfigurable architecture which facilitates the evaluation of several newly designed analog circuits. The chip has been designed and fabricated in a 1.2-μm CMOS process and occupies an area of 2×2 mm²     

Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing

Modern advances in reconfigurable technologies are allowing analog circuit designers to benefit from the computational flexibility provided by large-scale field-programmable analog arrays. With the component density of these devices, small analog circuits, as well as larger analog systems, can be synthesized and tested in a shorter time and at a lower cost, compared with the full design cycle. However, automated development platforms and computer-aided design tools for these devices are far fewer than the physical synthesis tools for their digital counterparts. One of the major reasons for this is the considerably higher impact of interconnect parasitics on circuit functionality in the analog domain; therefore, performance optimization must be recognized as an indispensable step of the analog physical synthesis flow. Our goal in this brief is to present a physical synthesis framework with an optimization core and an integrated simulation environment for verification of the synthesis results. Although SPICE has been used as the simulation tool for our experiments, there is no dependency on a particular circuit simulator. Our synthesis tool currently accepts SPICE netlists as input and gives priority to user-specified metrics when optimizing the synthesized circuit performance. Experimental results demonstrate the effectiveness of our approach.     

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control(AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented.The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips.What’s more,a novel DC offset cancellation(DCOC) circuit with an HPCF(high pass cutoff frequency) less than 10 kHz is proposed.The AGC is fabricated by a 0.18μm CMOS process.Under analog control mode,the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz.Under digital control mode,through a 5-bit digital control word,the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB.The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV,while the offset voltage of 40 mV is introduced into the input.The overall power consumption is less than 3.5 mA,and the die area is 800×300μm~2.     

异步可重构结构设计

介绍一种异步可重构结构，研究了异步可重构单元的设计。通过提前产生求值完成信号，使用DSDCVS逻辑实现可重构单元的运算电路，改进了异步可重构单元的控制电路。用三输入的C元件实现异步可重构单元的控制电路。仿真结果表明，异步可重构结构具有低功耗、高性能的优点，适合作为IP集成到系统芯片上，组成低功耗、高性能的可重构计算平台。     

Quantized Spiking Neuron With A/D Conversion Functions

This brief presents a simple artificial spiking neuron and proposes its application to an A/D converter. Depending on the initial state, which is an analog input, the neuron can generate spike trains having various spike position patterns. Based on spike position modulation, the spike train can be symbolized by a digital output. As a result, the analog input can be encoded into the digital output. Adjusting a reconfigurable parameter, the neuron can realize various encodings such as binary and Gray encodings. This brief also proposes a simple reconfigurable implementation circuit and experimentally confirms typical A/D conversion functions     

基于可编程模拟器件的信号发生器

介绍了TRAC完全可重配置模拟器件和及其开发应用软件，并以此为基础设计了信号发生器，给出了设计图纸和仿真结果，该信号发生器性能稳定，不需要调试。     

Optimization Technique for Dynamic Reconfiguration of Programmable Analog/Digital Arrays

This paper presents an investigation of dynamically reconfigurable mixed-signal circuit constructed using a digital control system and the new technology of Field Programmable Analog Arrays (FPAA). A Motorola FPAA described in this paper can be used to build filters for analog signals as well as other kinds of analog applications implemented in switched capacitor technology (S/C-technology). The experimental studies described, take advantage of performance and programmability of the FPAA for filtering of an analog signal. The circuit structure is based on 2 parallel FPAA chips, analog multiplexer and multiplexer's control logic controlled by a digital system such as a PC or a Field Programmable Gate Array (FPGA). Dynamic reconfiguration is used in this system for adaptive filtering, or adaptive processing in general. Modeling and measurements of the transition behavior of the switching process between the 2 FPAA chips and analysis of limitations imposed by hardware imperfections will be presented. The experimental system assembled in this work is an excellent vehicle to learn about intricacies in performance of mixed-signal circuits and is used for verification of theoretical predictions and model validation/modification.     

A reconfigurable analog baseband circuit for WLAN,WCDMA,and Bluetooth

A reconfigurable analog baseband circuit for WLAN,WCDMA,and Bluetooth in 0.35 μm CMOS is presented.The circuit consists of two variable gain amplifiers (VGA) in cascade and a Gm-C elliptic low-pass filter (LPF).The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications.In order to achieve the optimum power consumption,the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application.Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN,8.9 mW for WCDMA and only 6.5 mW for Bluetooth,all with a 3 V power supply.The analog baseband circuit could provide-10 to +40 dB variable gain,third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth,fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA,and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN,respectively.     

Implementation of reconfigurable nth-order filter based on CCII

Topologies for realizing voltage and current mode reconfigurable nth-order filters based on the second-generation current conveyor (CCII) are assessed. The most compatible structure for field-programmable analog array is identified. A CCII adopting active current division networks are utilized for implementing the proposed filter leading to wide control of its coefficients. Programmability characteristics are demonstrated through experimental results obtained from integrated circuit chips fabricated in a 0.18 μm CMOS process.     

面向密码算法的异步可重构结构设计

针对FPGA和ASIC在实现密码算法时的不足之处，本文介绍了一种面向密码算法的异步可重构结构。该结构的运算功能由一个可重构单元阵列提供，数据通路由可重构单元之间的相互连接实现，异步通信采用握手信号完成。在分析握手信号传输延时对可重构结构的影响后，文章提出了一种适合该结构的单元信号传输握手控制电路。同时在单元结构中，使用改进的DSDCVS逻辑来设计其运算电路，减小了单元的面积，提高了单元的工作速度。应用实例表明，在实现密码算法时，面向密码算法的异步可重构结构表现出了比FPGA更好的性能。     

Programmable-weight building blocks for analog VLSI neural network processors

Although the neural network paradigms have the intrinsic potential for parallel operations, a traditional computer cannot fully exploit it because of the serial hardware configuration. By using the analog circuit design approach, a large amount of parallel functional units can be realized in a small silicon area. In addition, appropriate accuracy requirements for neural operation can be satisfied. Components for a general-purpose neural chip have been designed and fabricated. Dynamically adjusted weight value storage provides programmable capability. Possible reconfigurable schemes for a general-purpose neural chip are also presented. Test of the prototype neural chip has been successfully conducted and an expected result has been achieved.     

A reconfigurable VLSI neural network

Due to the variety of architectures that need be considered while attempting solutions to various problems using neural networks, the implementation of a neural network with programmable topology and programmable weights has been undertaken. A new circuit block, the distributed neuron-synapse, has been used to implement a 1024 synapse reconfigurable network on a VLSI chip. In order to evaluate the performance of the VLSI chip, a complete test setup consisting of hardware for configuring the chip, programming the synaptic weights, presenting analog input vectors to the chip, and recording the outputs of the chip, has been built. Following the performance verification of each circuit block on the chip, various sample problems were solved. In each of the problems the synaptic weights were determined by training the neural network using a gradient-based learning algorithm which is incorporated in the experimental test setup. The results of this work indicate that reconfigurable neural networks built using distributed neuron synapses can be used to solve various problems efficiently     

A highly integrated analog front-end for 3G

This paper describes a reconfigurable analog front-end (AFE) and audio codec IC supporting the wideband code division multiple access (WCDMA) standard. The chip is fabricated on Intel's 0.18-/spl mu/m (SOC) flash+logic+analog (FLA) process technology using a 0.35-/spl mu/m feature size analog transistor. The transmit path contains a 10-bit segmented rail-to-rail digital-to-analog converter, automatically tunable active RC filter, and programmable gain amplifier (PGA) with self-tuning gain and offset correction circuit. The receive path incorporates a PGA, active RC filter, and an 8-bit analog-to-digital converter with built-in offset correction. The AFE operates at 2.7 V with a current consumption of 55 mA and total active area of 15 mm/sup 2/.     

Aging signature properties and an efficient signature determination tool for online monitoring

Increased reliability problems in deep sub-micron CMOS technologies have led to a dramatic decrease of lifetime of analog integrated circuits. To palliate this problem, several reliability-aware design approaches have been developed. Reconfigurable circuit design is one of those approaches, which is based on reconfiguring the circuit considering degradation in circuit performances. Sense & React (S & R) approach is the well-known reconfigurable design approach, where degradation in circuit performances are sensed and a pre-established recovery operation is applied to heal the circuit. In practice, indirect measurements are preferred during sense operation, in which electrical quantities are measured in order to determine time to recovery. Determination of the time to recover is the most critical part of a S & R system. One or more circuit variables are selected out of all measurable circuit quantities. The selected signature should have some attributes to be used as the aging signature to reduce the measurement cost. However, efficient aging signature properties have not been defined in the literature yet. Moreover, the designer determines the aging signature manually by performing an iterative search and evaluation on aging simulation results, and there is no tool to ease this time consuming process. This paper clearly describes the aging signature properties and proposes an automatic signature selection tool that determines the most efficient signature for sense operation.     

A 4th-order reconfigurable analog baseband filter for software-defined radio applications

This paper presents a 4th-order reconfigurable analog baseband filter for software-defined radios.The design exploits an active-RC low pass filter（LPF） structure with digital assistant,which is flexible for tunability of filter characteristics,such as cut-off frequency,selectivity,type,noise,gain and power.A novel reconfigurable operational amplifier is proposed to realize the optimization of noise and scalability of power dissipation.The chip was fabricated in an SMIC 0.13μm CMOS process.The main filter and frequency calibration circuit occupy 1.8×0.8 mm² and 0.48×0.25 mm² areas,respectively.The measurement results indicate that the filter provides Butterworth and Chebyshev responses with a wide frequency tuning range from 280 kHz to 15 MHz and a gain range from 0 to 18 dB.An IIP3 of 29 dBm is achieved under a 1.2 V power supply.The input inferred noise density varies from 41 to 133 nV/（Hz）^1/2 according to a given standard,and the power consumptions are 5.46 mW for low band（from 280 kHz to 3 MHz） and 8.74 mW for high band（from 3 to 15 MHz） mode.     

A CMOS 5 nV$/surd $Hz 74-dB-Gain-Range 82-dB-DR Multistandard Baseband Chain for Bluetooth, UMTS, and WLAN

An analog baseband chain for a multistandard (Bluetooth, WCDMA/UMTS, and WLAN) reconfigurable receiver in a 0.13 mum CMOS occupying 1.65 mm² is presented. The circuit consists of an open-loop programmable-gain amplifier (PGA1), an active-G_m-RC low-pass filter (LPF), and a closed-loop programmable-gain amplifier (PGA2). The chain gain can be programmed in the range -6 divide 68 dB, while the input-referred noise (IRN) is 5 nV/radicHz. A dynamic range (DR) larger than 82 dB is achieved for a 1% total harmonic distortion (THD). The current consumption is minimized and adjusted for the different operation conditions, down to 11 mA for the full chain.     

一种基于动态存储和模拟运算的神经突触电路

提出了一种基于动态存储和模拟运算的神经突触电路。其中，动态存储单元的保持时间可以达到10^2ms量级。模拟运算单元的电路简单、精度高、速度快。由动态存储单元和模拟运算单元组成的突触电路能够满足实现大规模神经网络的需要。HSPICE仿真结果和理论分析相符。     

开放式可重构伺服系统研究与设计

伺服系统作为雷达的重要组成部分,目前已完成从模拟系统向数字控制的转换,但依然存在兼容性差、功能不易扩展等缺点,无法满足雷达对伺服系统多样性、移植性等需求。为了实现雷达伺服系统的开放性,文中提出一种开放式可重构雷达伺服系统的硬件构成及开放式系统接口设计,并对系统重构的软件设计方法进行了阐述。最后给出开放式系统在2种体制的雷达伺服系统中的应用实例。实践表明,基于嵌入式控制器的开放式可重构伺服系统应用灵活方便。     

Semi-Iterative Analog Turbo Decoding

Based on multiple-slice turbo codes, a novel semi-iterative analog turbo decoding algorithm and its corresponding decoder architecture are presented. This work paves the way for integrating flexible analog decoders dealing with frame lengths over thousands of bits. The algorithm benefits from a partially continuous exchange of extrinsic information to improve decoding speed and correction performance. The proposed algorithm and architecture are applied to design an analog decoder for double-binary codes. Taking full advantage of multiple slice codes, the on-chip area is shown to be reduced by ten when compared to a conventional fully parallelized analog slice turbo decoder. The reconfigurable analog core area for frames of 40 bits up to 2432 bits is 37 nm² in a 0.25-mum BiCMOS process.