Performance analysis of a low power low noise tunable band pass filter for multiband RF front end

This paper presents a low power tunable active inductor and RF band pass filter suitable for multiband RF front end circuits. The active inductor circuit uses the PMOS cascode structure as the negative transconductor of a gyrator to reduce the noise voltage. Also, this structure provides possible negative resistance to reduce the inductor loss with wide inductive bandwidth and high resonance frequency. The RF band pass filter is realized using the proposed active inductor with suitable input and output buffer stages. The tuning of the center frequency for multiband operation is achieved through the controllable current source. The designed active inductor and RF band pass filter are simulated in 180 nm and 45 nm CMOS process using the Synopsys HSPICE simulation tool and their performances are compared. The parameters, such as resonance frequency, tuning capability, noise and power dissipation, are analyzed for these CMOS technologies and discussed. The design of a third order band pass filter using an active inductor is also presented.     

A self-powered piezoelectric energy harvesting interface circuit with efficiency-enhanced P-SSHI rectifier

The key to self-powered technique is initiative to harvest energy from the surrounding environment.Harvesting energy from an ambient vibration source utilizing piezoelectrics emerged as a popular method.Efficient interface circuits become the main limitations of existing energy harvesting techniques.In this paper,an interface circuit for piezoelectric energy harvesting is presented.An active full bridge rectifier is adopted to improve the power efficiency by reducing the conduction loss on the rectifying path.A parallel synchronized switch harvesting on inductor (P-SSHI) technique is used to improve the power extraction capability from piezoelectric harvester,thereby trying to reach the theoretical maximum output power.An intermittent power management unit (IPMU) and an output capacitor-less low drop regulator (LDO) are also introduced.Active diodes (AD) instead of traditional passive ones are used to reduce the voltage loss over the rectifier,which results in a good power efficiency.The IPMU with hysteresis comparator ensures the interface circuit has a large transient output power by limiting the output voltage ranges from 2.2 to 2 V.The design is fabricated in a SMIC 0.18μm CMOS technology.Simulation results show that the flipping efficiency of the P-SSHI circuit is over 80％ with an off-chip inductor value of 820 μH.The output power the proposed rectifier can obtain is 44.4μW,which is 6.7× improvement compared to the maximum output power of a traditional rectifier.Both the active diodes and the P-SSHI help to improve the output power of the proposed rectifier.LDO outputs a voltage of 1.8 V with the maximum 90％ power efficiency.The proposed P-SSHI rectifier interface circuit can be self-powered without the need for additional power supply.     

VLSI局部电源网络的宏模型研究

针对大规模VLSI电源网络分析效率问题,提出一种局部电源网络宏模型求解方法,根据其结构特点,结合电路等效变换与电路合并,对电路模型进行简化,并建立其宏模型.在全局电源网络分析中,利用各局部电源网络宏模型替代其完整电路模型,以降低分析问题的规模与复杂度.实验结果表明,在电源网络分析中应用宏模型技术,可以将分析效率提高1.7倍,且性能随电源网络规模的增大而提高.     

低功耗自供电压电能量管理电路的研究

为了提高压电能量采集系统的采集效率,该文提出了一种用于压电能量采集的自供电能量管理电路.采用基于并联同步开关感应(P-SSHI)技术的有源全桥整流电路来提高压电采能器的功率,降低整流电路上的导通损耗;采用低功耗稳压降压集成芯片配合超级电容器,实现能量的高效采集存储.仿真结果表明,在模拟输出电压幅值为20 V时,该整流电...     

一种新颖的功率MOSFET SPICE宏模型

提出了一种新颖的功率MOSFET宏模型结构,详细介绍了宏模型建立的整个流程;并将此模型的仿真结果与实验数据进行比较,验证了模型的精度。此模型考虑了功率MOSFET必要的二阶效应,并采用行为级模型来处理JFET电阻。     

Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-μm CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.     

PCB integrated inductors for low power DC/DC converter

This paper discusses the use of printed circuit board (PCB) integrated inductors for low power DC/DC buck converters. Coreless, magnetic plates and closed core structures are compared in terms of achievable inductance, power handling and efficiency in a footprint of 10 /spl times/ 10 mm/sup 2/. The magnetic layers consist of electroplated NiFe, so that the process is fully compatible with standard PCB process. Analytic and finite element method (FEM) methods are applied to predict inductor performance for typical current waveforms encountered in a buck converter. Conventional magnetic design procedures are applied to define optimum winding and core structures for typical inductor specifications. A 4.7 /spl mu/H PCB integrated inductor with dc current handling of up to 500 mA is presented. This inductor is employed in a 1.5 W buck converter using a commercial control integrated circuit (IC). The footprint of the entire converter measures 10 /spl times/ 10 mm/sup 2/ and is built on top of the integrated inductor to demonstrate the concept of integrated passives in power electronic circuits to achieve ultra flat and compact converter solutions.     

A Multistage Interleaved Synchronous Buck Converter With Integrated Output Filter in 0.18 μm SiGe Process

The design and analysis of a fully integrated multistage interleaved synchronous buck dc-dc converter with on-chip filter inductor and capacitor is presented. The dc-dc converter is designed and fabricated in 0.18 mum SiGe RF BiCMOS process technology and generates 1.5 V-2.0 V programmable output voltage supporting a maximum output current of 200 mA. High switching frequency of 45 MHz, multiphase interleaved operation, and fast hysteretic controller reduce the filter inductor and capacitor sizes by two orders of magnitude compared to state-of-the-art converters and enable a fully integrated converter. The fully integrated interleaved converter does not require off-chip decoupling and filtering and enables direct battery connection for integrated applications. This design is the first reported fully integrated multistage interleaved, zero voltage switching synchronous buck converter with monolithic output filters. The fully integrated buck regulator achieves 64% efficiency while providing an output current of 200 mA.     

Internal Geometry Variation of LTCC Inductors to Improve Light-Load Efficiency of DC-DC Converters

A low-profile power inductor fabricated using low-temperature cofired ceramic (LTCC) technology has been demonstrated to improve the light-load efficiency of a converter, without the use of additional control circuitry. This is brought about by the material and the geometry, which causes a change in inductance with load current. Variation in inductor geometry is performed experimentally to study the effects on the light-load efficiency of a converter. By decreasing the conductor width of the inductor, the light-load efficiency can be further improved by 30% in comparison with using commercial inductors of similar inductance. Sufficient core thickness is necessary to have sufficient inductance, since an inductance value which is too low is detrimental from the system power loss point of view, as demonstrated experimentally. From the circuit point of view, there seems to be a critical inductance value, whereby increasing the inductance further, does not result in significant improvement in power stage efficiency. Changing conductor thickness in the range of 260 to 550 mum does not result in significant improvement in the overall efficiency of the converter. Variation in the number of parallel conductors in a multiconductor structure does not have significant effect on light-load efficiency improvement.     

Lossless average inductor current sensor for CMOS integrated DC–DC converters operating at high frequencies

A novel average inductor current sensing circuit integrable in CMOS technologies is presented. It is designed for DC–DC converters using buck, boost, or buck-boost topologies and operating in continuous conduction mode at high switching frequencies. The average inductor current value is used by the DC–DC controllers to increase the light load power conversion efficiency (e.g., selection of the modulation mode, selection of the dynamic width of the transistors). It can also be used to perform the constant current charging phase when charging lithium-ion batteries, or to simply detect overcurrent faults. The proposed average inductor current sensing method is based on the lossless sensing MOSFET principle widely used in monolithic CMOS integrated DC–DC converters for measuring the current flowing through the power switches. It consists of taking a sample of the current flowing through the power switches at a specific point in time during each energizing and de-energizing cycle of the inductor. By controlling precisely the point in time at which this sample is taken, the average inductor current value can be sensed directly. The circuit simulations were done with the Cadence Spectre simulator. The improvements compared to the basic sensing MOSFET principle are a lower power consumption because no high bandwidth amplifier is required, and less noise emission because the sensing MOSFET is no more switched. Additionally, the novel average inductor current sensing circuit overcomes the low bandwidth limitation previously associated with the sensing MOSFET principle, thus enabling it to be used in DC–DC converters operating at switching frequencies up to 10 MHz and above.     

DC/DC转换器中电流采样电路的设计

设计了一种用于DC/DC开关电源转换器的新型电流采样电路.常见的电流采样电路是通过检测采样管串联电阻上压降来得到采样电流,而该采样电路是通过检测开关管串联电感上压降来得到采样电流的.由于后者所需电阻更少,从而降低了采样电路的功耗,提高了效率;并且由于电感上压降对采样电流变化的灵敏度更高,有效地提高了采样的精度.     

一种用于RFID读写器的高集成CMOS功率放大器的设计与分析

To implement a fully-integrated on-chip CMOS power amplifier（PA） for RFID readers,the resonant frequency of each matching network is derived in detail.The highlight of the design is the adoption of a bonding wire as the output-stage inductor.Compared with the on-chip inductors in a CMOS process,the merit of the bondwire inductor is its high quality factor,leading to a higher output power and efficiency.The disadvantage of the bondwire inductor is that it is hard to control.A highly integrated class-E PA is implemented with 0.18-μm CMOS process.It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm.The maximum power-added efficiency（PAE） is 32.1%.Also,the spectral performance of the PA is analyzed for the specified RFID protocol.     

Efficient SSHI circuit for piezoelectric energy harvester uses one shot pulse boost converter

In this paper, a one shot pulse inductor boost converter is presented which provides 4 V output at 60 ms of delay using 0.15 V vibration source. Energy harvesting plays an important role in biomedical implants sensors where the extended life time is the most prominent factor. Synchronized switch harvesters on inductor (SSHI) comes into existence due to its highly efficient interface with energy harvesters. The main aim of this paper is to obtain high efficiency and maximum power extraction from piezoelectric energy harvester using SSHI and one shot pulse boost converter. This circuit does not require any external voltage and provides the controlled output with reduced power dissipation of approximately 10 nW and power consumption achieves between 1 and 10 mW. The start-up problem due to variable vibrational energy source is avoided by using one shot pulse inductor boost converter. This converter uses only one shot period for maximum charge transfer during first switching cycle. In 180 nm CMOS process, result shows that pulse boost converter can be directly powered from low voltage of 0.15 V with efficiency of?≈?90% across the load of 6 µA current having switching frequency of 206 kHz. It also eliminates the problem of switching losses and reduces leakage current by saving board space and external components cost.     

Analysis of the power delivery path from the 12-V VR to the microprocessor

This paper offers a thorough analysis of the power delivery path. Based on the power delivery path model, the current slew rate of each loop is derived. The relationship between the inductor current slew rate of the voltage regulator (VR) and the bandwidth is also derived. Then, the level of the voltage spike across the capacitors of each loop is determined, after which the relationship between the bandwidth and the capacitance can be plotted. We find that for today's power delivery structure, the bulk capacitors can be eliminated as long as the bandwidth is pushed beyond 350 kHz. The experimental results of a 2-MHz two-stage 12-V VR verify this analysis.     

High efficiency,high switching speed,AlGaAs/GaAs P-HEMT DC–DC converter for integrated power amplifier modules

This paper presents a high efficiency, high switching frequency DC–DC buck converter in AlGaAs/GaAs technology, targeting integrated power amplifier modules for wireless communications. The switch mode, inductor load DC–DC converter adopts an interleaved structure with negatively coupled inductors. Analysis of the effect of negative coupling on the steady state and transient response of the converter is given. The coupling factor is selected to achieve a maximum power efficiency under a given duty cycle with a minimum penalty on the current ripple performance. The DC–DC converter is implemented in 0.5 μm GaAs p-HEMT process and occupies 2 × 2.1 mm² without the output network. An 8.7 nH filter inductor is implemented in 65 μm thick top copper metal layer, and flip chip bonded to the DC–DC converter board. The integrated inductor achieves a quality factor of 26 at 150 MHz. The proposed converter converts 4.5 V input to 3.3 V output for 1 A load current under 150 MHz switching frequency with a measured power efficiency of 84%, which is one of the highest efficiencies reported to date for similar current/voltage ratings.     

Cycle-accurate macro-models for RT-level power analysis

In this paper, we present a methodology and techniques for generating cycle-accurate macro-models for register transfer (RT)-level power analysis. The proposed macro-model predicts not only the cycle-by-cycle power consumption of a module, but also the moving average of power consumption and the power profile of the module over time. We propose an exact power function and approximation steps to generate our power macro-model. First-order temporal correlations and spatial correlations of up to order three are considered in order to improve the estimation accuracy. A variable reduction algorithm is designed to eliminate the “insignificant” variables using a statistical sensitivity test. Population stratification is employed to increase the model fidelity. Experimental results show our macro-models with 15 or fewer variables, exhibit <5% error for average power and <20% errors for cycle-by-cycle power estimation compared to circuit simulation results using Powermill     

单片集成直流-直流转换器的效率提高方法

采用SMIC 0.13μm CMOS工艺,设计实现了开关频率达到250 MHz,单片集成的降压型电源转换器。为了提高电源转换效率,该转换器中的片上电感采用非对称性设计方法,提高了电感的品质因数。采用了高密度片上滤波电容来稳定输出电压,同时对单位电容尺寸的优化设计减小了电容的等效串联电阻以及输出电压纹波。测试结果表明,芯片输入电压为3.3 V,当输出2.5 V电压时,峰值效率达到了80%,最大输出电流达到270 mA;当输出1.8 V电压时,峰值效率达到了70%,最大输出电流达到400 mA。     

A highly efficient inductorless voltage regulator

This versatile and highly efficient voltage regulator, for applications where the conventional series regulator and the inductor type of switching regulator are impractical, uses solid-state switching techniques. Efficiencies greater than 90 percent have been achieved, independent of input voltage amplitudes. Good load regulation is provided, with a ripple increase as the main effect of a load-current increase. High-peak-current capability is another major advantage of the regulator. The circuit described successfully delivers power peaks of 600 watts. Output voltage restoration from the power line is accomplished as quickly as possible. Some applications of the regulator are prereugulation, class-B audio amplifiers, and solenoid driving.     

A TEG Efficiency Booster with Buck–Boost Conversion

A thermoelectric generator (TEG) efficiency booster with buck–boost conversion and power management is proposed as a TEG battery power conditioner suitable for a wide TEG output voltage range. An inverse-coupled inductor is employed in the buck–boost converter, which is used to achieve smooth current with low ripple on both the TEG and battery sides. Furthermore, benefiting from the magnetic flux counteraction of the two windings on the coupled inductor, the core size and power losses of the filter inductor are reduced, which can achieve both high efficiency and high power density. A power management strategy is proposed for this power conditioning system, which involves maximum power point tracking (MPPT), battery voltage control, and battery current control. A control method is employed to ensure smooth switching among different working modes. A modified MPPT control algorithm with improved dynamic and steady-state characteristics is presented and applied to the TEG battery power conditioning system to maximize energy harvesting. A 500-W prototype has been built, and experimental tests carried out on it. The power efficiency of the prototype at full load is higher than 96%, and peak efficiency of 99% is attained.     

A design methodology for integrated inductor-based DC–DC converters

A design methodology for monolithic integration of inductor based DC–DC converters is proposed in this paper. A power loss model of the power stage, including the drive circuits, is defined in order to optimize efficiency. Based on this model and taking as reference a 0.35 μm CMOS process, a buck converter was designed and fabricated. For a given set of operating conditions the defined power loss model allows to optimize the design parameters for the power stage, including the gate-driver tapering factor and the width of the power MOSFETs. Experimental results obtained from a buck converter at 100 MHz switching frequency are presented to validate the proposed methodology.