W-plug via electromigration in CMOS process

We analyze the failure mechanism of W-plug via electromigration made in a 0.5-μm CMOS SPTM process. Failure occurs at the top or bottom of a W-plug via. We design a series of via chains, whose size ranges from 0.35 to 0.55 μm. The structure for the via electromigration test is a long via chain, and the layer in the via is Ti/TiN/W/TiN. Using a self-heated resistor to raise the temperature of the via chain allows the structure to be stressed at lower current densities, which does not cause significant joule heating in the plugs. This reduces the interaction between the plug and the plug contact resistance and the time-to-failure for the via chain. The lifetime of a W-plug via electromigration is on the order of 3 × 107 s, i.e., far below the lifetime of metal electromigration. The study on W-plug via electromigraion in this paper is beneficial for wafer level reliability monitoring of the ultra-deep submicron CMOS multilayer metal interconnect process.     

A novel sub-half micron Al-Cu via plug interconnect using lowdielectric constant material as inter-level dielectric

A novel Al-Cu via plug interconnect using low dielectric constant (low-ϵ) material as inter-level dielectric (ILD) has been demonstrated. The interconnect structure was fabricated by spin-on deposition of the low-ϵ ILD and physical vapor deposition (PVD) of the Al-Cu. Excellent local ILD planarization was achieved by a two-step spin-on coating process. The dielectric constant of the low-ϵ no is about 2.7, which leads to significant interconnect wiring capacitance reduction. For the first time, completely filled Al-Cu:0.5% plugs with nearly vertical sidewalls were fabricated in organic low-ϵ ILD. Excellent via fill was observed with via size down to 0.30 μm. Low via resistance and excellent via reliability have been observed     

Abnormal metal oxide formation induced by residual charging in plasma etch process

Electron cyclotron resonance plasma with SF₆ and Cl₂ gas mixture were used for tungsten plug etch-back processes. The properties of electric contacts between tungsten plugs and Al/Ti/TiN interconnect lines, fabricated by this etching process, have been studied. Particles and abnormal oxide layers at the plug/line interfaces have been found to be the main factor to cause deterioration of the electric contacts. Mechanisms for particle transportation and metal oxide formation have been proposed. The phenomenon was attributed to the residual charging effect, which occurred immediately after the plasma power being turned off. A technique to prevent the residual charging induced tungsten oxide growth has been developed and applied in industrial fabrication lines.     

Alkaline barrier slurry applied in TSV chemical mechanical planarization

We have proposed a TSV （through-silicon-via） alkaline barrier slurry without any inhibitors for barrier CMP （chemical mechanical planarization） and investigated its CMP performance. The characteristics of removal rate and selectivity of Ti/SiO2/Cu were investigated under the same process conditions. The results obtained from 6.2 mm copper, titanium and silica show that copper has a low removal rate during barrier CMP by using this slurry, and Ti and SiO2 have high removal rate selectivity to Cu. Thus it may be helpful to modify the dishing. The TSV wafer results reveal that the alkaline barrier slurry has an obvious effect on surface topography correction, and can be applied in TSV barrier CME     

微电子器件制备中CMP抛光技术与抛光液的研究

介绍了河北工业大学微电子研究所发明成果:15～20nm铜的CMP碱性抛光液、阻挡层CMP碱性抛光液,用于介质CMP的120nm水溶胶磨料抛光液、互连插塞钨和铝的CMP纳米SiO2磨料碱性抛光液及ULSI硅衬底CMP抛光液及切削液、磨削液、倒角液和应力控制技术等研究成果。     

Watermark-Induced High-Density Via Failures in Submicron CMOS Fabrication (May 2006)

High via resistance was detected in the high-density via structure in our 0.15-mum back-end-of-line (BEOL) yield monitoring test vehicle. A localized insulating layer was found on top of the plug in test vehicle causing high via resistance. The failure was attributed to watermark-induced contaminants on top of the W plug. It was shown that the failure could be avoided by eliminating watermark formation on the wafer in the post-chemical-mechanical polishing scrub process.     

Implementation of tungsten metallization in multilevelinterconnection technologies

The techniques of experimental design and response-surface methodology have been used to produce empirical models of the deposition and etchback of tungsten in commercially available reactors for a tungsten plug technology. Deposition was carried out in a Genus 8402 LPCVD (low-pressure chemical vapor deposition) batch reactor by the H ₂ reduction of WF₆. Response-surfaces for deposition rate, sheet resistance uniformity, resistivity, and film stress were developed as a function of reactor pressure, reactor temperature, and flow rate of WF₆ at a fixed H₂ flow rate using linear-interactive models. A thin layer of TiN was used to ensure adhesion of tungsten to SiO₂. Etchback of the composite layer of W/TiN to form via plugs was performed in a Tegal 804 single-wafer system with a two-step process using mixtures of SF₆ with C₂F₆ and He with Cl₂ in step 1 and step 2, respectively. Process parameters for both steps were obtained from quadratic models of etch rate and etch uniformity     

Cu互连及其关键工艺技术研究现状

低介电常数材料和低电阻率金属的使用可以有效地降低互连线引起的延时.Cu因其具有比Al及Al合金更低的电阻率和更高的抗电迁移能力而成为新一代互连材料.论述了Cu互连技术的工艺过程及其研究发展现状.对Cu互连技术中的阻挡层材料、电化学镀Cu技术以及化学机械抛光技术等一系列关键工艺技术进行系统的分析和讨论.     

The stability of a novel weakly alkaline slurry of copper interconnection CMP for GLSI

Chemical mechanical polishing (CMP) is one of the important machining procedures of multilayered copper interconnection for GLSI,meanwhile polishing slurry is a critical factor for realizing the high polishing performance such as high planarization efficiency,low surface roughness.The effect of slurry components such as abrasive (colloidal silica),complexing agent (glycine),inhibitor (BTA) and oxidizing agent (H2O2) on the stability of the novel weakly alkaline slurry of copper interconnection CMP for GLSI was investigated in this paper.First,the synergistic and competitive relationship of them in a peroxide-based weakly alkaline slurry during the copper CMP process was studied and the stability mechanism was put forward.Then 1 wt％ colloidal silica,2.5 wt％ glycine,200 ppm BTA,20 mL/L H2O2 had been selected as the appropriate concentration to prepare copper slurry,and using such slurry the copper blanket wafer was polished.From the variations of copper removal rate,root-mean square roughness (Sq) value with the setting time,it indicates that the working-life of the novel weakly alkaline slurry can reach more than 7 days,which satisfies the requirement of microelectronics further development.     

Bumpless Interconnect of 6- $mu$m-Pitch Cu Electrodes at Room Temperature

Bumpless interconnect of 6-$mu{rm m}$-pitch Cu electrodes was realized at room temperature with the surface activated bonding (SAB) method. In this study, we propose a novel bumpless structure, where the electrodes and a surrounding Cu frame are fabricated with the same height to increase bond strength and demonstrate the feasibility of a sealing interconnection between Cu surfaces. The damascene process, assisted by the reactive ion beam etching (RIE), was used to fabricate the Cu structures. 923$thinspace$521 electrodes placed inside the frame were arranged into a spiral chain to enable the detection of the positions with insufficient interconnection by electrical resistance measurements. Using the SAB conditions optimized with simple chemo-mechanical polishing (CMP)-Cu film samples, we found that 744$thinspace$769 electrodes were successfully interconnected, except some specific lines near the frame, which might be due to sample preparation error rather than a bond defect. The mean contact resistance was below 0.08 $Omega$; a sealing effect was achieved at the frame structure because there was little increase in the contact resistance in high temperature storage testing performed at 150 $^{circ}{rm C}$ for 1000 h, in ambient air.      

Design of experiment (DOE) method considering interaction effect of process parameters for optimization of copper chemical mechanical polishing (CMP) process

Chemical mechanical polishing (CMP) has been widely accepted for the metallization of copper interconnection in ultra-large scale integrated circuits (ULSIs) manufacturing. It is important to understand the effect of the process variables such as turntable speed, head speed, down force and back pressure on copper CMP. They are very important parameters that must be carefully formulated to achieve desired the removal rates and non-uniformity. Using a design of experiment (DOE) approach, this study was performed investigating the interaction effect between the various parameters as well as the main effect of the each parameter during copper CMP. A better understanding of the interaction behavior between the various parameters and the effect on removal rate, non-uniformity and ETC (edge to center) is achieved by using the statistical analysis techniques. In the experimental tests, the optimized parameters combination for copper CMP which were derived from the statistical analysis could be found for higher removal rate and lower non-uniformity through the above DOE results.     

Process development in metal/BCB multilayer interconnections of MMCM with embedded chip in Si substrate

A vertical interlayer connection via (VILCV) fabrication process is presented. This process is used for the interconnection of multilayer benzocyclobutene (BCB) based microwave multichip modules (MMCM). The excellent planarity of BCB allows VILCV to be formed using gold electroplating or stud bumps prior to BCB application. And mechanical polishing (MP) planarization is adopted to expose the VILCV, enabling interconnection between different layers. Subsequently upper interconnection is patterned. Metal/BCB multilayer structure can be made by repeating above steps. This approach eliminates the need for laser drilling and plasma etching. Both four terminal Kelvin structures and via chains are fabricated as test vehicles. Finally, a transition of transmission lines in different layers and a packaged MMIC embedded in Si substrate are presented and measured in high frequency range up to 20 GHz. The results show there is only minimal performance degradation.     

Aluminum-germanium-copper multilevel damascene process usinglow-temperature reflow sputtering and chemical mechanical polishing

A low-temperature multilevel aluminum-germanium-copper (Al-Ge-Cu) damascene technology was developed using reflow sputtering and chemical mechanical polishing (CMP). The maximum processing temperature for the fabrication of multilevel interconnections could be reduced to 420°C using Al-1%Ge-0.5%Cu, whereas the conventional reflow temperature was not less than 500°C. No degradation due to reflow heat cycles was observed in terms of Al-Ge-Cu wiring resistance. Electromigration test results indicated that the mean time to failure (MTTF) of Al-1%Ge-0.5%Cu was longer than 10 years at the operating condition, which was equivalent to that of Al-1%Si-0.5%Cu. The Al-1%Ge-0.5%Cu triple-level interconnection was fabricated using reflow sputtering to fill vias and wiring trenches and subsequent CMP for Al-Ge-Cu films     

The formation of Ti-polycide gate structure with high thermalstability using chemical-mechanical polishing (CMP) planarizationtechnology

A planarized Ti-polycide gate structure with high thermal stability has been developed using a chemical-mechanical polishing (CMP) process for the application of high-speed DRAM devices. For a given gate length and without any thermal annealing, the planarized Ti-polycide structure developed via a novel gate line formation technology manifested a substantially lower gate line resistance than that produced by a conventional processing method. In addition, the agglomeration of the TiSi₂ gate in a deep submicron regime was suppressed even after high-temperature cycling at 850°C for 300 min, owing to a negligible local stress at the corner of the active and field region     

Selectively deposited nickel film for via filling

A selective deposition process is used to fill vias in VLSI multilevel interconnection. Ni film is chosen as the via-filling material because of its compatibility with the underlying Al film. The vias are filled with a thin Pd film first and a thick Ni film. The deposited Ni film is uniform and smooth in the via regions. This film is not attacked by the plasma etch used in subsequent Al patterning; therefore, the design rule of overlapping the second metal on vias can be relaxed. The specific via resistance of this process is 4×10 ^-9Ω-cm². The via resistance increases about 30% after an exposure to 450°C for 8 h     

Effect of oxide and W-CMP on the material properties and electromigration behaviour of layered aluminum metallisations

It has been found that chemical mechanical polishing increases the electromigration resistance of a Ti/AlCu/Ti/TiN metal stack. (111) X-ray diffraction polefigures indicate an increased (111) texture of AlCu deposited on a substrate that received at least one CMP step. This improved (111) texture can be attributed to a decreased roughness of the underlying oxide when chemical mechanical polishing is used.     

IC制备中钨插塞CMP技术的研究

对目前超大规模集成电路钨插塞化学机械全局平面化(CMP)的原理及工艺进行了分析,对钨抛光浆料的组成成分进行了研究,开发了一种能够适合工业生产的钨的碱性抛光浆料,并对钨抛光浆料今后的发展进行了展望.     

Ti/TiN/Ti(N) PVD liners for W-plug applications

A novel scheme for implementing a same chamber Ti/TiN/Ti(N) W-plug liner is introduced. The Ti(N) cap is the result of a TiN-coated target clean in an argon only plasma. It is found that a process window exists within which a thin flash layer renders the contribution of TiF₃ formation during the CVD W deposition process to via resistance insignificant. At the same time the flash process time is long enough to sufficiently de-nitride the target. The subsequent Ti deposition is pure enough to getter any surface contamination at the bottom of the vias. The W-liner interfaces for flash layers of varying thicknesses are investigated using Auger emission spectroscopy. The electrical results presented demonstrate that the Ti/TiN/Ti(N) liner is comparable to standard liner processes.     

GLSI多层布线钨插塞CMP表面质量的影响因素分析

随着超大规模集成电路向高集成、高可靠性及低成本的方向发展,对IC工艺中的全局平坦化提出了更高的要求。在特大规模集成电路(GLSI)多层布线化学机械抛光(CMP)过程中,抛光质量对器件的性能有明显影响。研究了多层互连钨插塞材料CMP过程中表面质量的影响因素及控制技术,分析了抛光过程中影响抛光质量的主要因素,确定了获得较高去除速率和较低表面粗糙度的抛光液配比及抛光工艺参数。     

铜互连及其相关工艺

介绍了铜互连、金属间低K绝缘层和CMP工艺。ITRS2001/1999对铜互连、金属间低K绝缘层和CMP工艺提出了具体的要求和进程。ITRS2001比ITRS1999整整提前了一年。铜互连和金属间低K绝缘层可解决布线RC延迟问题,CMP可解决晶圆表面不平整问题。IC特征尺寸、铜互连层厚度、金属间低K绝缘层厚度和Cu/低K鄄CMP所用研磨膏粒子尺寸都已步入纳米级,从而进一步提高了高端IC的密度和速度。