集成电路的互连线延迟分析

IC制造技术先后进入亚微米、VDSM和LIDSM工艺,互连线延迟关注随之逐渐增强.事实上,互连线延迟早已超过了器件延迟,使IC设计重点转移到以互连线设计为核心.在对互连延迟模型、延迟影响因素、互连线延迟优化以及互连线延迟对IC设计的影响作简要分析基础上,给出了有价值的总结.     

连环图：一种新的多计算机系统通信体系结构

本文根据Ｃａｙｌｅｙ图模型，提出了一种新的互连网络，它具有预点对称性。固定的顶点度、易于路由、通信延迟小以及容错等特点。本文给出了这种互连网络的路由算法和容错路由算法，证明了其连通度为３。     

基于MMS协议的异构网络互连

ＭＭＳ（制造报文规范）是一种能够满足ＣＩＭＳ环境中各种可编程自动化设备间通信需求的应用层协议。本文首先简单介绍了ＭＭＳ的客户／服务器通信模型，接着给出异构网络互连的物理模型及信息模型，并详细论述了异构网络上ＭＭＳ通信系统的实现，最后对实际制造设备入网方法及ＰＬＣ系统入网实现进行了探讨。     

CIMS中单元控制器互连的研究和实现

单元控制器是ＣＩＭＳ的重要组成部分，ＣＩＭＳ的多变的需求环境要求单元控制器具有开放的体系结构，本文介绍了支持单元控制器互连的计算机网络技术和协议，以及在ＴＣＰ／ＩＰ网络上单元控制器互连和ＭＭＳ子集的实现。     

基于对角互连网格拓扑结构的片上网络

对二维网格拓扑结构进行改进,给出对角互连的DMesh结构和对角互连且边界节点互连的DTorus结构,针对2种拓扑结构分别提出DXY路由算法和TDXY路由算法。仿真实验结果表明,DMesh和DTorus结构可以节省网络节点间的路由通道数,减少平均传输延迟,增加吞吐量,使路由路径更加多样化。     

Internet的高速新信道——CATV数字网络

文中讨论了我们在基于ＣＡＴＶ网络上实现Ｉｎｔｅｒｎｅｔ互连课题中的部分研究成果。简要地描述了ＣＡＴＶ与电信网在实现Ｉｎｔｅｒｎｅｔ上的优劣比较；详细地分析了在ＣＡＴＶ介质上运行ＴＣＰ／ＩＰ协议的必要条件；给出了ＣＡＴＶ介质的低层协议；在此基础上较详细地讨论实现Ｃａｂｌｅ ＭＯＤＥＭ的关键技术，最后给出了一个实现实例和结论。     

基于网络包延迟偏差的硬件动态拥塞控制机制

互连网络已经成为提升高性能计算系统性能的技术瓶颈。对高性能互连网络中的拥塞控制进行研究,针对通信热点的形成过程,给出了一种基于网络包延迟偏差的硬件动态拥塞控制机制CMDPD,利用网络包传输延迟偏差预判网络拥塞状态,控制端到端网络注入,避免拥塞形成。构建了模拟环境,在Fat-tree和Dragonfly两种网络结构下,对CMDPD进行了模拟实验。结果表明,在Fat-tree网络中CMDPD的吞吐率可提高5%~12%。     

网络互连多线程处理器

结合可扩展的片上互连网络和隐藏延迟的同时多线程结构,论文提出网络互连多线程(NMT,NetworkedMulti-threaded)处理器结构;在SMTSIM仿真器的基础上进行仿真,结果表明NMT结构具有较好的可扩展性和并行性,并提出了对其片上互连网络的性能要求。     

一个可变拓扑的多单片机系统的设计

用可变拓扑互连结构来实现多机间的互连，是计算机多机通讯研究的一个重要方向。本文给出了一个采用现场可编程技术实现的多单片系统的体系结构的设计和实现。它将四片ＭＣＳ－５１系列单片机通过全互连的拓扑结构连接起来，以ＰＣ３８６／４８６为主机，构成一个主从分布式控制的多机系统。该系统还在Ｘｉｌｉｎｘ ＸＡＣＴ的Ｃ
ＣＡＤ工具上进行了模拟验证，并得到ＦＰＧＡ（现场可编程门阵列）实现。     

LON网络组网技术的研究与实现

本文详细阐述了ＬＯＮ网络的组网技术。对于ＬＯＮ网络的关键部件神经元芯片ＭＣ１４３１２０和ＭＣ１４３１５０作了深入的研究与说明，并给出了由该类神经元芯片构成的典型网络节点的组成方式和结构特点     

基于分段时延凸函数的最小斯坦纳树方法

针对超大规模集成电路的互连时延问题,提出一种利用互连时延为搜索距离分段凸函数性质建立的最小时延斯坦纳Elmore(Steiner Elmore)布线树的方法,采用扩大搜索空间的方法寻找最佳连接点,同时建立一种有效的查找方法对布线树进行反复修改以减小树的总长度。实验结果表明,该方法可以缩小布线树的搜索空间,加快搜索速度,在阻抗占优的情况下,具有较好的性能。     

High-performance MCM routing

The authors describe the multilayer MCM (multichip module) routing problem, and propose an approach for routing high-performance MCMs with the objective of minimizing interconnect delays and crosstalk. They first introduce an approach for rapidly estimating the time-domain response of lossy transmission line trees, and propose a realistic second-order delay model for MCM interconnects. The delay model is used to guide a performance-driven global routing algorithm. Given the 2-D global paths, the next stage is layer assignment. An effective algorithm for constrained layer assignment is developed. Based on the best-known maxcut approximation algorithm (which performs well in practice), a maximal k-color ordering is formulated for minimizing both interlayer and intralayer crosstalk as well as crossings in 3-D MCM substrates. The authors also propose a strategy that exhibits a good tradeoff between circuit performance and design cost, instead of concentrating exclusively on a single objective such as area minimization     

基于优先性的延迟噪声故障分析方法*

为了减少互连串扰噪声对电路性能的影响,提出一种top-k延迟噪声故障分析方法。通过逻辑分析方法有效地修剪受扰线和干扰线组合的分析空间,利用时序窗口计算受扰线和干扰线之间的虚假延迟噪声故障的发生概率,找到实际电路中最有可能引起虚假延迟噪声故障的top-k条干扰线。本方法能够在规定时间内消除尽可能多的虚假噪声,从而提高了串扰噪声影响下时序分析的精确度。     

用动态规划法求解延时/面积最小化工艺映射

本文提出了一个求解延时／面积最小化工艺映射动态规划法．它首先基干线性延时模型，给出了用动态规划法求解延时最小化工艺映射的步骤；然后从树型网络的面积计算公式入手，用动态规划法近似计算面积最小化工艺映射；最后用“线性加权和法”把延时／面积最小化工艺映射转变为单目标最优化问题求解．     

调节缓存器宽度和布线宽度相结合的优化算法

介绍了将调节缓存器宽度和布线宽度相结合的一种减小连线延迟的优化算法—B＆W算法。算法是以Elmore迟延模型为基础的。该算法在GWSA1的算法基础上考虑调节缓存器宽度的作用,因而比单独的调节布线宽度的算法在运算速度上要快的多。例如它在有8000个缓存器和连线段的情况下,CPU时间仅为0．215秒。B＆W算法同时是一种叠代搜索算法,它能够达到最优解。而且算法可以扩展应用到互连树的情况下,这使它的应用更加广泛。     

Overlay high-density interconnect: a chips-first multichip moduletechnology

A high-density interconnection (HDI) technology that involves placing bare chips into cavities on a base substrate and fabricating the thin-film interconnect structure on top of the components is described. The interconnects to the chip I/O pads are formed as part of the thin-film fabrication process, thus eliminating the need for wire bonds, tape-automated bonds (TABs), or solder bumps. The need for advanced packaging and interconnection and the standard chips-last multichip module (MCM) technologies are reviewed. The HDI chips-first MCM technology's IC pretest requirements and approaches, substrate and packaged parts test, and substrate packaging are discussed     

Prediction of communication delay in torus networks under multiple time-scale correlated traffic

The efficiency of a large-scale multicomputer is critically dependent on the performance of its interconnection network. Current multicomputers have widely employed the torus as their underlying network topology for efficient interprocessor communication. In order to ensure a successful exploitation of the computational power offered by multicomputers it is essential to obtain a clear understanding of the performance capabilities of their interconnection networks under various system configurations. Analytical modelling plays an important role in achieving this goal. This study proposes a concise performance model for computing communication delay in the torus network with circuit switching in the presence of multiple time-scale correlated traffic which is found in many real-world parallel computation environments and has strong impact on network performance. The tractability and reasonable accuracy of the analytical model demonstrated by extensive simulation experiments make it a practical and cost-effective evaluation tool to investigate network performance with various alternative design solutions and under different operating conditions.     

金属连线光刻技术

介绍了一种细线条金属连线光刻技术。在溅射铝后,生长一薄层氮化硅薄膜作为减反层,利用氮化硅薄膜的光刻条件,涂覆薄胶可以保证刻出细线条,腐蚀薄层氮化硅保证线宽,同时在腐蚀铝过程中用氮化硅作掩蔽解决了薄胶问题。并在亚微米的抗辐射加固电路中成功应用。     

面向输电线故障信息传输的多播路由

针对无线传感器网络应用于输电线路故障传输时存在通信代价高、实时性差的问题,提出一种输电线路故障传输多播路由算法(MRFT)。抽象出输电线路故障信息传输网络模型;根据时延最短路径树(SPT)的最大端到端时延确定多播树时延上限,将时延上限边接入多播树;设计最小代价启发函数将剩余叶子节点接入多播树。仿真结果表明,与KPP算法相比,MRFT算法构造的多播树在多播树时延、端到端时延方差和多播树代价3个方面均有良好表现。该算法能够有效保证输电线路故障信息传输的实时性,降低通信代价。     

Trends in low-cost, high-performance substrate technology

The trends in high density interconnection (HDI) multichip module (MCM) techniques that have the potential to reduce interconnection cost and production time are described. The implementation in laminated dielectric (MCM-L) technology of a workstation processor core illustrates current substrate technology capabilities. The design, routing, layout and thermal management of the processor core are described. Thin-film deposited dielectric (MCM-D) technology is discussed as a cost-effective method for future interconnection applications