A class of digitally programmable nth‐order filters

A family of new high‐order filters capable of providing all filter functions without changing the circuit topology is proposed for integrated circuit applications. The proposed filters are based on simple active elements, namely, digitally controlled current amplifiers (DCCAs) and unity gain voltage buffers (VBs). Gains of DCCAs are digitally programmed to adjust the coefficients of transfer functions. R2R ladders are also utilized to increase the tuning flexibility of the proposed filters. A filter replicating the famous KHN biquad is extended to realize general nth‐order filters. Comparison with the recent works shows that the proposed approach results in more efficient realizations compared with its counterparts based on other current‐mode active elements. Experimental results obtained from a fourth‐order filter implemented using devices fabricated in a 0.35‐µm CMOS process are provided. Copyright © 2011 John Wiley & Sons, Ltd.     

A complementary metal–oxide semiconductor digitally programmable current conveyor

A second‐generation current conveyor with digitally programmable current gains is presented. A current division network with zero standby power consumption is utilized in two different ways to provide both gain and attenuation of the second‐generation current conveyor's current transfer characteristics. The proposed topology overcomes several drawbacks of the previous solutions through affording a more power and area efficient solution while exhibiting relatively wider tuning range and bandwidth. A variable‐gain amplifier and a two‐integrator‐loop filter biquad providing low‐pass and band‐pass responses are given as application examples. A modified two‐integrator‐loop topology is developed to offer independent control of the pole frequency and quality factor without disturbing the passband gain. Simulation results obtained from a standard 0.18 µm complementary metal–oxide semiconductor process are given. Copyright © 2011 John Wiley & Sons, Ltd.     

CMOS digitally programmable quadrature oscillators

CMOS digitally programmable quadrature oscillators based on digitally controlled current followers and voltage followers are proposed. The proposed designs provide the advantage of programmability similar to the operational transconductance amplifier‐based oscillators while offering improved linearity. In mixed analog/digital systems, the digital tuning feature allows direct interfacing with the digital signal processing part. Novel realizations that provide both voltage‐mode and current‐mode quadrature sinusoidal signals are presented. Employing only grounded capacitors the designs achieve independent control of the frequency and condition of oscillation that can be tuned digitally. Experimental results obtained from a 0.35 µm CMOS chip fabricated using standard CMOS process are given. Copyright © 2008 John Wiley & Sons, Ltd.     

基于MAX262的程控滤波器的实现

介绍了自动测试系统中基于ＭＡＸ２６２的程控滤波器的设计原理及流程，给出了具体电路及程序，最后举一个应用实例进行了说明。     

Improved 3 × 3 sequential Euclidean distance transform

We propose an improved 3 × 3 sequential Euclidean distance transform (DT) using quad‐scan propagation. Our method has a separable scan structure that can be processed with a multicore processor to reduce computation time with a better accuracy. The computer simulation shows that the proposed DT algorithm approximates the Euclidean map more precisely than conventional 3 × 3 DTs while reducing dramatically computation time comparable to 8‐point sequential Euclidean distance algorithm. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A low-power 75 dB digitally programmable variable-gain amplifier in 0.18μm CMOS

Variable-gain amplifiers (VGAs) are essential building blocks of many communication systems. In this paper, a monolithic low-power digitally programmable VGA with 75 dB of gain range is presented. The core of the design is based on a low-distortion source-degenerated differential amplifier structure. The gain is varied by changing the source-degeneration resistor and tuning the resistors in the common-mode feedback circuitry. The complete VGA consists of three gain stages. As a proof of concept, a 24 dB single-gain stage with 2 dB gain steps is fabricated in a 0.18 ?m CMOS technology. The prototype chip is tested, and measurement results are obtained. Based on these results, the gain stage is redesigned to optimize its performance, and a three-stage 75 dB VGA is designed and simulated. Each stage has a digitally tunable gain range of 25 dB. The overall gain can be varied from ?15 dB to 60 dB in 2.5 dB gain steps. The bandwidth of the multi-stage VGA is higher than 140 MHz, and the gain error is less than 0.3 dB. The overall VGA draws 6.5mA from a 1.8V power supply. The noise figure of the system at maximum gain is 12.5 dB, and the third-order intermodulation intercept point (IIP3) at minimum gain is 14.4 dBm.     

A programmable VLSI architecture based on multilayer CNN paradigms for real-time visual processing

A new digital VLSI architecture has been presented for the implementation of discrete-time multilayer CNNs. At functional level, the architecture is organized as 12 layers of 64 × 64 cells which interact as specified by a set of 3D generalized templates. At structural level the application of cloning templates occurs in a set of processing units programmed by instruction masks, generated on the basis of the algorithm to be emulated. It is demonstrated that this architecture is applicable to multilayer algorithms for visual processing and also to standard CNNs, including those that use sequences of templates or that work in parallel. Simulations evidence the high efficiency of this implementation.     

A dynamic‐biasing 4× charge pump based on exponential topology

A 4× charge pump using exponential topology is proposed and implemented. Comparing to the conventional implementations, the proposed circuit suppresses the reverse current effectively without using different threshold‐voltage transistors and additional capacitors. Also, the body effect found in the charge transfer switches is eliminated. The proposed charge pump is analyzed with the state‐space method and fabricated using 0.35 µm complementary metal–oxide–semiconductor process. Results show that the output voltages close to the ideal one, and a maximum power efficiency of 95% was recorded. Copyright © 2013 John Wiley & Sons, Ltd.     

A VLSI-oriented continuous-time CNN model

This paper presents an analysis of the stability and convergence properties of the full signal range (FSR) CNN model. These properties are demonstrated to be similar to those of the Chua-Yang model and the I/O mapping of known applications is shown to be unaffected by the modification introduced in this new model. In this modified CNN model the dynamic range of the cell state variables equals the dynamic range of the cell output variables and is invariant with the application. This feature results in simpler circuit implementations, thus allowing higher cell densities and improving the robustness of CNN integrated circuits. The FSR CNN model is particularly well suited for programmable CNN integrated circuits.     

Theory on resistance of m × n cobweb network and its application

A basic theorem of equivalent resistance between two arbitrary nodes in an m × n cobweb network in both finite and infinite conditions is discovered, and two conjectures on the equivalent resistance are proved in terms of the basic theorem. We built a tridiagonal matrix equation by means of network analysis and made a diagonalization method of matrix transformation and work out its explicit expressions. The new formulae obtained here can be effectively applied in complex impedance network, especially the formulation leads to the occurrence of resonances and a series of novel results in RLC (denote resistor, inductance and capacitance) network. These curious results suggest the possibility of practical applications to resonant circuits. Copyright © 2014 John Wiley & Sons, Ltd.     

A CNN handwritten character recognizer

CNNs are used for feature detection in handwritten character recognition. Detected features are fed to a simple classifier network. Performance was tested by using two well-known ETL data base series: (i) ETL3 consisting of numerals, alphabets and several symbols and (ii) ETL8B2 consisting of Japanese Hirakana characters. the average recognition rate for ETL3 is 94.8%, while that for ETL8B2 is 85.7%. Both series include ‘hard’ characters so distorted that even humans cannot recognize them.     

Resistance and capacitance of 4 × n cobweb network and two conjectures

A classic problem in electric circuit theory studied by numerous authors over 160 years is the computation of the resistance between two nodes in a resistor network, yet some basic problem in m × n cobweb network is still not solved ideally. The equivalent resistance and capacitance of 4 × n cobweb network are investigated in this paper. We built a quaternion matrix equation and proposed the method of matrix transformations in terms of the network analysis. We proposed a brief equivalent resistance formula and find that the equivalent resistance is expressed by cos(kπ/9) in a series of strict calculation. Meanwhile, an equivalent resistance of infinite networks is gained. Using the inverse mapping relation between capacitance parameters and resistance parameters, the equivalent capacitance formula is also given for the 4 × n capacitance cobweb network. By analyzing and comparing the equivalent resistances of the 1 × n, 2 × n, 3 × n and 4 × n cobweb networks, two conjectures on the equivalent resistance and capacitance of the m × n cobweb network are proposed. Copyright © 2013 John Wiley & Sons, Ltd.     

A DOUBLE TIME—SCALE CNN FOR SOLVING TWO-DIMENSIONAL NAVIER—STOKES EQUATIONS

A practical cellular neural network (CNN) approximation to the Navier–Stokes equation describing the viscous flow of incompressible fluids is presented. The implementation of the CNN templates based on a finite-difference discretization scheme, including the double-timescale CNN dynamics and the treatment of various types of boundary conditions are explained. The operation of the continuous-time model is demonstrated through several examples.     

Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology

This paper uses a CAD methodology proposed by the authors to design a low-power second-order ΣΔM. This modulator has been fabricated in a 0·7 μm CMOS technology to be used as the front-end of an energy-metering mixed-signal ASIC and features 16·4 bit at a digital output rate of 9·6 kHz with a power consumption of 1·71 mW. It yields a value of the power(W)/(2^{Resolution(bit)}×output rate (Hz)) figure which is the smallest reported to now, thus demonstrating the possibility to design high-performance embeddable ΣΔMs using CAD methodologies. © 1997 by John Wiley & Sons, Ltd.     

A CNN UNIVERSAL CHIP IN CMOS TECHNOLOGY

This paper describes the design of a programmable cellular neural network (CNN) chip with added functionalities similar to those of the CNN universal machine. The prototype contains 1024 cells and has been designed in a 1·0 μm, n-well CMOS technology. Careful selection of the topology and design parameters has resulted in a cell density of 31 cells mm⁻² and around 7–8 bits accuracy in the weight values. Adaptive techniques have been employed to ensure accurate external control and system robustness against process parameter variations.     

一种可编程扭矩柔性起动电路

介绍一种可编程硬件电路的工作原理和软件编程 ,实现柔性起动。     

DYNAMIC ANALOGIC CNN ALGORITHMS FOR A COMPLEX RECOGNITION TASK—A FIRST STEP TOWARDS A BIONIC EYEGLASS

Complex, dynamic, analogic CNN algorithms are presented for detecting some objects and features in a natural scene. Though the problem is well defined, the variations in the arrangements of features and objects and the illumination cause significant problems. The task is to find doors, door-handles, signs, etc. in a given floor of a house. The solution is a first step towards making a bionic CNN eyeglass.     

Current‐mode programmable piecewise‐linear neural synapses

Cellular Neural Networks with piecewise linear connection have been proposed by several authors as a generalization of the basic paradigm, which allows for more complex functionality. None of the prototypes realized to date, however, provides for such kind of synapses. As a feasibility study, a current‐mode subthreshold CMOS piecewise‐linear synapse circuit is developed in this paper. Copyright © 2003 John Wiley & Sons, Ltd.