MECHATRONICS 2000. Seventh Mechatronics Forum InternationalConference and Mechatronics Education Workshop

The following topics are dealt with: flip chip solder joint quality inspection; direct chip attach packaging for microsystems; reliability analysis of no-underfill flip chip package; ASIC/memory integration by system-on-package; wafer-level and flip chip designs through solder prediction models and validation; reliability evaluation of under bump metallurgy in two solder systems; a method to improve the efficiency of the CMP process; thermal and reliability analysis of packaging systems     

3-D packaging methodologies for microsystems

Issues associated with the packaging of microsystems in plastic and three-dimensional (3-D) body styles are discussed. The integration of a microsystem incorporating a micromachined silicon membrane pump, into a 3-D plastic encapsulated vertical multichip module package (MCM-V) is described. Finite element techniques are used to analyze the encapsulation stress in the structure of the package. Cracks develop in the chip carrier due to thermomechanical stress. Based on the results of a finite element design study, the structures of the chip carriers are modified to reduce their risk of cracking. Alternative low stress 3-D packaging methodologies based on chip on board and plastic leadless chip carriers are discussed.     

微系统三维(3D)封装技术

文章论述塑料三维(3D)结构微系统封装技术相关问题,描述了把微电机硅膜泵与3D塑料密封垂直多芯片模块封装(MCM-V)相结合的微系统集成化。采用有限元技术分析封装结构中的封装应力,根据有限元设计研究结果,改变芯片载体结构,降低其发生裂纹的危险。计划采用板上芯片和塑料无引线芯片载体的替代低应力和低成本的3D封装技术方案。     

Investigation of the fluid/structure interaction phenomenon in IC packaging

In the present study, experiment and simulation studies were conducted on the fluid/structure interaction (FSI) analysis of integrated circuit (IC) packaging. The visualisation of FSI phenomenon in the actual package is difficult due to limitations of package size, available equipment, and the high cost of the experimental setup. However, the experimental data are necessary to validate the simulation results in the FSI analysis of IC packaging. Scaled-up package size was fabricated to emulate the encapsulation of IC packaging and to study the effects of FSI phenomenon in the moulded package. The interaction between the fluid and the structure was observed. The deformation of the imitated chip was studied experimentally. The air-trap mechanism that occurred during the experiment is also presented in this paper. Simulation technique was utilised to validate the experimental result and to describe the physics of FSI. The predicted flow front was validated well by the experiment. Hence, the virtual modelling technique was proven to be excellent in handling this problem. The study also extends FSI modelling in actual-size packaging.     

Cover Picture: Fabrication of Multicomponent Microsystems by Directed Three‐Dimensional Self‐Assembly (Adv. Funct. Mater. 5/2005)

Directed three‐dimensional self‐assembly to assemble and package integrated semiconductor devices is demonstrated by Jacobs and Zheng on p. 732. The self‐assembly process uses geometrical shape recognition to identify different components and surface‐tension between liquid solder and metal‐coated areas to form mechanical and electrical connections.The components (top left) self‐assemble in a turbulent flow (center) and form functional multi‐component microsystems (bottom right) by sequentially adding parts to the assembly solution. The technique provides, for the first time, a route to enable the realization of three‐dimensional heterogeneous microsystems that contain non‐identical parts, and connecting them electrically. We have developed a directed self‐assembly process for the fabrication of three‐dimensional (3D) microsystems that contain non‐identical parts and a statistical model that relates the process yield to the process parameters. The self‐assembly process uses geometric‐shape recognition to identify different components, and surface tension between liquid solder and metal‐coated areas to form mechanical and electrical connections. The concept is used to realize self‐packaging microsystems that contain non‐identical subunits. To enable the realization of microsystems that contain more than two non‐identical subunits, sequential self‐assembly is introduced, a process that is similar to the formation of heterodimers, heterotrimers, and higher aggregates found in nature, chemistry, and chemical biology. The self‐assembly of three‐component assemblies is demonstrated by sequentially adding device segments to the assembly solution including two hundred micrometer‐sized light‐emitting diodes (LEDs) and complementary metal oxide semiconductor (CMOS) integrated circuits. Six hundred AlGaInP/GaAs LED segments self‐assembled onto device carriers in two minutes, without defects, and encapsulation units self‐assembled onto the LED‐carrier assemblies to form a 3D circuit path to operate the final device. The self‐assembly process is a well‐defined statistical process. The process follows a first‐order, non‐linear differential equation. The presented model relates the progression of the self‐assembly and yield with the process parameters—component population and capture probability—that are defined by the agitation and the component design.     

An approach of numerical multi-objective optimization in stacked packaging

The main aim for the development of small electronic packages is supported by an ongoing development of portable communication devices. Thin silicon dies are believed to improve the device performance as well as its reliability. Additionally, novel packaging techniques such as stacked packaging reduce packaging cost and size, and improve the functionality and reliability. In the case of the stacked packages, wafers are stacked to form a 3D multi-chip package. On the other hand, the electronic market requires novel and efficient numerical designing tools to deal properly with the optimization. The goal of the current work was to design a reliable numerical model of the stacked package and afterwards perform numerical multi-objective optimization in reference to a number of variables, which influence the stacked package reliability.     

Review on materials, microsensors, systems and devices forhigh-temperature and harsh-environment applications

The considerable investment in silicon technology has rarely addressed device use in harsh environments such as high temperatures, aggressive media, and radiation exposure. A clear future requirement is to save weight, volume, and reduce costs in “unfriendly” environments like high temperatures. This can be achieved either by cooling systems or by electronic microsystem components suited to withstand high temperatures. The current status of cooling systems, harsh-environment sensors, and microsystems in view of markets, realized devices, material, properties, process maturity, and packaging technologies are reviewed. Possible semiconductor candidates for high-temperature applications are discussed. The main obstacles for the future of high-temperature and harsh-environment microsystems is highlighted     

化学镀镍镀钯浸金表面处理工艺概述及发展前景分析

随着电子封装系统集成度逐渐升高及组装工艺多样化的发展趋势,适应无铅焊料的化学镀镍镀钯浸金（ENEPIG）表面处理工艺恰好能够满足封装基板上不同类型的元件和不同组装工艺的要求,因此ENEPIG正成为一种适用于IC封装基板和精细线路PCB的表面处理工艺。ENEPIG工艺具有增加布线密度、减小元件尺寸、装配及封装的可靠性高、成本较低等优点,近年来受到广泛关注。文章基于对化学镍钯金反应机理的简介,结合对镀层基本性能及可靠性方面的分析,综述了ENEPIG表面处理工艺的优势并探讨了其发展前景。     

基于SOP生产工艺的系统级封装

提出了一种基于SOP24基板及生产工艺,利用空余的管脚焊盘放置被动元件实现内部互连,制作SiP封装集成电路的封装工艺。选择红外发射电路,使用HT6221红外编码器芯片、电阻、三极管等无源元件,制造出集成了驱动电路的红外发射芯片。建立开发平台对内部器件的布置进行优化,最终制作出工艺简单、性能可靠的SiP封装器件。用一个标准的SOP24封装组件实现了完整的系统功能,面积比系统级封装前减少50％,可靠性大幅度提高,用户使用该芯片开发产品的难度大大降低。     

Development of packaging technologies for microsystems

It is well known that packaging plays a very important role in developing microsystems. Packaging accounts for about 60%～80% of cost and function of a microsystem. Package is required to provide mechanical protection, media separation or coupling, signal conditioning, etc.     

New dimensions in memory

A new 16Mb 3DM module has been developed that satisfies the requirements of high packaging density, high memory capacity, and low fabrication cost. The package density is four times that of TSOP. The module is fabricated by using four 4Mb-DRAM chips at low cost, and it is almost the same size as the single 4Mb-DRAM package (TSOP) currently in use. We also developed a new fabrication process for the module. A 3DM module has advantages in its size, high package density, and electrical performance. Applications that can utilize these advantages include supercomputers, workstations, memory cards, and space equipment     

汽车电子封装趋势,考量及生产的特殊性

汽车电子是半导体行业成长较快的领域。安全、舒适、互联,和个性化是未来十年成长的主要动力。可靠性和性价比优势使支架封装仍占主导,而其它封装,如PBGA、堆叠式芯片尺寸封装(SCSP),和晶圆级封装(WLP)等,也正得到启用。MLF誖(QFN)应用广泛,具有很好的热电性能和设计灵活性。类似凹槽侧面可湿性焊点技术的创新,让MLF誖这种传统封装更具吸引力。更多传感器和MEMS用于汽车应用,封装形式主要为MLF誖,LGA和"凹槽MEMS"。资讯娱乐系统需要采用更多类型的封装形式。汽车电子封装生产所涉及的供应商管理、可靠性测试等因素必须与严格的汽车标准保持一致。     

Flip chip die attach development for multichip mechatronics powerpackages

New package innovations are needed to address the next generation system requirements of the automotive market. Enhanced system functionality from semiconductor components and overall cost reduction demands drive multichip package solutions. The use of semiconductor devices to switch, control and monitor high current loads will integrate logic and power devices on a common substrate with requirements for effective power dissipation, current carrying capability and fine width conductor features for the control device and interconnections. To achieve these goals Motorola's Advanced Interconnection Systems Laboratory, Munich, has developed a new package concept, a multichip mechatronics power package, utilizing flip chip die attach technology and electroplated eutectic SnPb solder bumps. With the goal to deliver an advanced package platform to cover different power levels in the system architecture,the several substrate technologies were evaluated     

Packaging of microsystems for harsh environments

Micromachined devices have great potential but using these fragile structures in aggressive environments can pose a challenge. Mechanical shock, chemical exposure, and temperature extremes can damage delicate microsystems. Also, substantial effort is often put forth to develop a device concept only to find later that the device is difficult or expensive to package suitably in a consumer or automotive environment. The cost of materials, processing, and manufacturing make the sensor or actuator device impractical for some applications. A successful MEMS device manages the proper balance for its application between the high device performance and low unit cost. The packaging of MEMS begins with a consideration of the microsystem's environment. An aerospace, automotive, or industrial component could be subjected to temperatures ranging from -40°C to over 150°C. Mechanical shocks in the 10 g to +500 g range can be experienced which can fracture poorly designed silicon beams. Chemical exposure, which can corrode silicon, or the metal interconnection lines on silicon, and shift electrical parameters, are challenges that must be overcome in these applications     

自主知识产权产品LIP封装

为解决QFN成本较高的问题和进一步提高产品可靠性,华天科技突破了传统思想的束缚,在产品结构的设计上进行了创新。引脚在封装本体内式封装(LIP:Lead In Package)是一种新型的封装形式,它是针对目前QFN(Quad Flat No-lead)在封装高成本问题而重新选择的设计方案。     

Wafer-level chip size package (WL-CSP)

Size reduction is one of the main driving forces for packaging in nearly all electronic applications. The interaction of size reduction with highest functionality and high reliability is also predominant for all microelectronic systems. Therefore a synergism of optimal product design, smallest single chip package and board technology will give the best solution. Wafer level CSP will be the best solution for single chip packaging matching all requirements for electronic systems and reducing total cost     

Active fiber-solder-ferrule alignment method for high-performance opto-electronic device packaging

In optical communication systems, the transceivers, including both transmitters and receivers, are the key components of system quality and bandwidth. Fiber-solder-ferrule (FSF) assembly has been widely adopted in packaging high performance transceivers such as dual-in-line package and butterfly package. The flexibility and size of the fiber and ferrule, traditional FSF packaging process is done manually and the average accuracy of the fiber position is around 80 /spl mu/m. In this case, approximately 1 out of 5 FSF assemblies will have an accuracy of less than 20 /spl mu/m, which past research shows is sufficient to maintain 90% coupling efficiency of the optoelectronic devices. This study proposes a novel method for automating the fiber-solder-ferrule packaging process based on thorough system analysis. Finally, a packaging system is developed to improve the accuracy of the fiber position to up to 20 /spl mu/m.     

High reliability, high density, low cost packaging systems formatrix systems for matrix BGA and CSP by vacuum printing encapsulationsystems (VPES)

Ball grid array (BGA) and chip scale package (CSP) packaging markets are increasing. In general, transfer molding systems are used for these packaging processes. However, transfer molding systems are difficult to change the model for high expensive metal die. This paper describes a unique vacuum printing encapsulation system (VPES) we developed to solve such problems with lower cost than transfer molding. We used matrix type BGA and CSP for this test. Matrix type BGA and CSP make it easy to use printing technology for die-bonding, packaging, marking, and flux coating process. The total cost of this packaging is cheaper than the transfer molding process. We developed very low warpage and high reliability epoxy resin for matrix BGA and CSP. We succeeded in achieving high reliability and low cost packaging systems with this technology     

晶圆级芯片尺寸封装技术

尺寸缩减几乎是电子封装技术应用的主要驱动力之一。高功能性和高可靠性与尺寸缩减的相互作用,也是所有微电子系统的决定因素。因此,最佳产品设计、最小单芯片封装和板技术的最佳结合,将提供最佳解决方案。晶圆级CSP将是匹配所有电子系统要求、降低总成本的单芯片封装技术的最佳方案。