A survey of efficient MDCT implementations in MP3 audio coding standard: Retrospective and state-of-the-art

This tutorial paper describes various efficient implementations (published and new unpublished) of the forward and backward modified discrete cosine transform (MDCT) in the MPEG layer III (MP3) audio coding standard developed in the time period 1990-2010, including the efficient implementation of polyphase filter banks for completeness. The efficient MDCT implementations are discussed in the context of (fast) complete analysis/synthesis MDCT filter banks in the MP3 encoder and decoder. In general, for each efficient forward/backward MDCT block transforms implementation are presented: complete formulas or sparse matrix factorizations of the algorithm, the corresponding signal flow graph for the short audio block and the total arithmetic complexity as well as the useful comments related to improving the arithmetic complexity and a possible structural simplification of the algorithm. Finally, all efficient forward/backward MDCT implementations are compared both in terms of the arithmetic complexity and structural simplicity. It is important to note that almost all presented algorithms can be also used for the 2ⁿ-length data blocks in others MPEG audio coding standards and proprietary audio compression algorithms.     

Common Architecture Design of Novel Recursive MDCT and IMDCT Algorithms for Application to AAC, AAC in DRM, and MP3 Codecs

This paper presents a novel recursive algorithm to compute the modified discrete cosine transform (MDCT) and the inverse MDCT (IMDCT) based on type IV of the discrete cosine transform (DCT-IV) algorithm. The proposed algorithm has the following advantages: In contrast with parallel designs, the input sequence fed by serial in/serial out (SISO) can dynamically be switched with the variable window length. The data throughput per transformation for the MDCT and IMDCT algorithms is four times higher than that of the previous algorithms, and the ROM size can be reduced by 50%-79%. Less memory is required for accessing; thus, it can reduce the chip area in hardware implementation. The chip efficiency is also increased, and the proposed architecture makes a feasible design to integrate several audio standards [i.e., advanced audio coding (AAC)/AAC in digital radio mondiale (DRM/MPEG-1 Audio Layer 3 (MP3)] into one portable media player. The proposed algorithm is designed and fabricated by using 0.18-mum 1P6M complimentary metal-oxide-semiconductor (CMOS) process. The core area is 441 times 437 mum², including the MDCT, IMDCT, and DCT-IV modules. For modern audio applications, i.e., AAC/AAC in DRM/MP3, this processor only consumes 14.077/3.482/0.3138 mW at 50/12.5/1 MHz. Furthermore, the proposed algorithm can calculate the 2048/1920/256/240/36/12-point MDCT and the 1024/960/128/120/18/6-point IMDCT.     

运用递归算法实现共用的MDCT和IMDCT结构

在MPEG音频编码标准中，前向MDCT和后向MDCT是2个计算最复杂的部分。提出了一种有效的递归算法来同时实现任意长度的前向MDCT和后向MDCT。由于递归算法本身的特性，所提出的结构非常适合并行VLSI的实现。     

A Hardware/Software Co-Design of MP3 Audio Decoder

The Moving Picture Experts Group (MPEG) audio coding standard offers three levels of compression algorithms where the MPEG Layer III (MP3) has the best quality but with the most complexity. There are several complex coding techniques involved in MP3 audio decoding algorithm, therefore, it is difficult to make an efficient architecture design. This paper presents a hardware/software co-design method for the implementation of MP3 audio decoder, which meets the real-time requirement of MP3 standard. The software and hardware part of this decoder is partitioned into a pre-processing and a post-processing unit respectively. The pre-processing unit with a programmable parser processor is developed for the implementation of intensive decision making operations needed for audio bitstreams. The post-processing unit with a dedicated hardware of modified fast algorithm is designed for the regular and computation-intensive operations in MP3 audio decoding flow. The architecture achieves a high throughput with a reduced memory requirement and hardware complexity. With a two-level pipeline approach, it allows a high hardware utilization and is suitable to low power implementation. The proposed decoder system has been designed and implemented using VLSI cell-based approach. The die size is 3.5 × 4.45 mm² with the maximum operation frequency of 20 MHz.Tsung-Han Tsai was born in Chunghua, Taiwan, R.O.C. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1990, 1994, and 1998 respectively. Dr. Tsai was an Instructor (1994–1998) and an Associate Professor (1998–1999) of the department of electrical engineering at Hwa Hsia College of Technology and Commerce. From 1999 to 2000, he was an Associate Professor of electronic engineering at Fu Jen University. Currently, he is an Assistant Professor in the department of electrical engineering at National Central University. He is also a member of IEEE and Audio Engineering Society (AES). Dr. Tsai has been awarded 8 patents and more than 70 refereed papers published in international journals and conferences. His research interests include VLSI signal processing, video/audio coding algorithms, DSP architecture design, wireless communication and System-On-Chip design.Ya-Chau Yang was born in Tainan, ROC in 1976. He received the B.S. and M.S. degrees both in electrical engineering from Fu-Jen University in 1999 and 2001, respectively. In 2002, he was as software engineer of Foundry Access in Cadence Design Systems. Currently he is a design engineer at ActVision Technology Inc, where he works on MPEG audio decoder IP design. His interests include MPEG audio coding algorithms, VLSI signal processing/architecture and computer architecture.Chun-Nan Liu was born in Taichung, Taiwan, R.O.C., in 1978. He received the B.S. degrees in electrical engineering from National Central University, Taiwan, in 2000. He is currently pursuing the Ph.D. degree from the Department of Electrical Engineering, National Central University, Taiwan. His area of interests are audio signal processing and VLSI signal processing.     

Generalized fast mixed-radix algorithm for the computation of forward and inverse MDCTs

This paper presents a generalized mixed-radix decimation-in-time (DIT) fast algorithm for computing the modified discrete cosine transform (MDCT) of the composite lengths N=2×q^m, m≥2, where q is an odd positive integer. The proposed algorithm not only has the merits of parallelism and numerical stability, but also needs less multiplications than that of type-IV discrete cosine transform (DCT-IV) and type-II discrete cosine transform (DCT-II) based MDCT algorithms due to the optimized efficient length-(N/q) modules. The computation of MDCT for composite lengths N=q^m×2ⁿ, m≥2, n≥2, can then be realized by combining the proposed algorithm with fast radix-2 MDCT algorithm developed for N=2ⁿ. The combined algorithm can be used for the computation of length-12/36 MDCT used in MPEG-1/-2 layer III audio coding as well as the recently established wideband speech and audio coding standards such as G.729.1, where length-640 MDCT is used. The realization of the inverse MDCT (IMDCT) can be obtained by transposing the signal flow graph of the MDCT.     

数字音频压缩自适应变换编码算法的研究

本文介绍了一种建立在心理声学基础上的适用于宽频带数字音频信号的数据压缩技术。我们利用计算机对整个编解码算法的全部过程进行了模拟，并采用Motorola公司的数字信号处理芯片DSP56009作为硬件平台，实现了高质量的音频信号压缩编码。试验效果压缩比达到1／10以下，没有明显的音质衰减。     

Mixed-Radix Algorithm for the Computation of Forward and Inverse MDCTs

The modified discrete cosine transform (MDCT) and inverse MDCT (IMDCT) are two of the most computationally intensive operations in MPEG audio coding standards. A new mixed-radix algorithm for efficiently computing the MDCT/IMDCT is presented. The proposed mixed-radix MDCT algorithm is composed of two recursive algorithms. The first algorithm, called the radix-2 decimation-in-frequency algorithm, is obtained by decomposing an N-point MDCT into two MDCTs with the length N/2. The second algorithm, called the radix-3 decimation-in-time algorithm, is obtained by decomposing an N -point MDCT into three MDCTs with the length N/3. Since the proposed MDCT algorithm is also expressed in the form of a simple sparse matrix factorization, the corresponding IMDCT algorithm can be easily derived by simply transposing the matrix factorization. Comparison of the proposed algorithm with some existing ones shows that our proposed algorithm is more suitable for parallel implementation and particularly suitable for the layer III of MPEG-1 and MPEG-2 audio encoding and decoding. Moreover, the proposed algorithm can be easily extended to the multidimensional case by using the vector-radix method.     

数字音频压缩中的变换编码算法

变换编码是音频压缩中的一个重要部分,文中叙述ＭＰＥＧ音频编码标准中的变换编码技术,包括改进余弦变换和反变换（ＭＤＣＴ和ＩＭＤＣＴ）时域混叠抵消与自适应窗选择,详细推导了ＭＤＣＴ和ＩＭＤＣＴ的快速算法。     

MP3编解码器中MDCT与IMDCT的硬件实现

在MP3编解码器的设计中,前向MDCT与反向IMDCT是两个计算最为复杂的部分.提出了一种新的算法,对MDCT与IMDCT的实现进行优化,极大地降低了运算量.该算法将MDCT与IMDCT的计算分成三步实现:前处理,核心处理,后处理.其中,核心处理部分由MDCT与IMDCT共用,大大减少了对硬件电路的需求,降低了芯片成本.     

MPEG中子带滤波的快速算法及定点实现

高保真的数字音频编码一般都采用子带分析滤波器,作为整个编码过程的主要模块之一,MPEG(活动图象专家组)音频就是典型情况。鉴于标准中给出的子带分析滤波器算法的运算量相当可观,作者提出了一种基于ID-CT(反离散余弦变换)的快速算法,在保证运算精度的前提下,减少运算量和数据量,最终目的是在一片廉价定点DSP上实现MP3(MPEG-Ⅰ层3)编码算法。     

A 128 Kb/s Hi-Fi audio codec based on adaptive transform codingwith adaptive block size MDCT

A Hi-Fi audio codec with an improved adaptive transform coding (ATC) algorithm is presented using digital signal processors (DSPs). An audio signal with a 20 kHz bandwidth sampled at 48 kHz is coded at a rate of 128 kb/s. The algorithm utilizes adaptive block size selection, which is effective for preecho suppression. A modified discrete cosine transform (MDCT) with a simple window set is employed to reduce block boundary noise without decreasing the performance of transform coding. In addition, a fast MDCT calculation algorithm, based on a fast Fourier transform, is adopted. Weighted bit allocation is employed to quantize the transformed coefficients. The codec was realized by a multiprocessor system composed of newly developed DSP boards. Subjective tests with the codec show that the coding quality is comparable to that of compact disc signals     

Fast IMDCT and MDCT algorithms - a matrix approach

This paper presents a systematic investigation of the modified discrete cosine transform/inverse modified discrete cosine transform (MDCT/IMDCT) algorithm using a matrix representation. This approach results in new understanding of the MDCT/IMDCT, enables the development of new algorithms, and makes clear the connection between the algorithms. We represent in a matrix form the IMDCT as the product of the type-IV DCT with simple scaling, sign-changing, and permutation operations such that fast algorithms for the type-IV DCT can be simply modified for the IMDCT, and vice versa. Then, the simple symmetry and inversion properties of the type-IV DCT are used to develop new algorithms and establish the connection between existing fast IMDCT algorithms. This approach also enables us to show that MDCT and IMDCT share common core operation and present an efficient architecture for implementing both the MDCT and the IMDCT in one hardware.     

A superfast algorithm for single-error correction in rrns and hardware implementation

The modular algebraic structure of the residue number systems (RNS) leads to modularity and parallelism in the hardware implementation for the RNS-based arithmetic processor [1], [2]. Both modularity and parallelism are essential to fully utilize the very-large-scale integrated (VLSI) technology [3]. In this work, a superfast algorithm for correcting single residue errors in the RNS is developed with a slight increase in redundancy. Based on this algorithm and another recently proposed fast algorithm, two architectures are designed for their hardware implementation. The hardware complexity for this superfast algorithm isO(k) while the hardware complexity for previously known algorithms isO(k ²). The performance of this new technique is compared to the previously known techniques in terms of computational speed and other criteria.     

基于MPEG-AAC编码器的压缩域音频增强方法

本文基于MPEG-AAC音频编解码器,提出了一种压缩域的音频增强方法.首先,对含噪音频信号的比特流进行解码,得到含噪音频信号的MDCT系数;然后,利用修正的加权递归平均（Modified Weighted Recursive Averaging,MWRA）方法估计噪声功率;再者,利用基于听觉掩蔽原理的自适应β-阶双曲余弦（COSH）统计模型,对含噪音频的MDCT系数进行增强处理;最后,将增强后的MDCT系数重新量化编码,得到用于解码的增强比特流实验结果表明,本文提出的方法能有效去除AAC解码音频信号中的多种背景噪声,其性能明显优于参考方法.     

MP3／AAC解码器中Huffman硬件加速器设计与实现

Huffman解码是感知音频解码过程的重要部分。软件实现Huffman解码运算,计算速度慢、功耗高,采用硬件实现的方法,设计并实现了一个兼容MP3与AAC标准的Huffman解码硬件加速器。采用十六叉树搜索算法．在存储空间增加不大的情况下,有效减少了Huffman码字的搜索深度,简化寻址操作,加快了搜索速度。通过直接外设访问的接口设计,该硬件加速器还可快速进行音频码流的数据读取。在XilinixFPGA上的功能和性能验证表明。该Huffman硬件加速器可成功应用于MP3和AAC解码器。     

AAC编码算法的快速实现

Advanced Audio Coding(AAC)是一种高质量的音频编码标准,其编码算法的运算复杂度很高。本文针对AAC的心理声学模型谱估计采用SDFT'谱代替标准建议的DFI'谱,对其比特分配模块则提出了一种自适应的最佳全局量化阶搜索方法,此外,还采用基于FFT的MDC'I'快速算法,大大降低了AAC编码算法的运算复杂度。     

基于DSP处理器的MP3解码器的优化

音频格式MP3（第三层）是现在非常流行的一种数字音频压缩技术，适应于微小的移动设备，如MP3播放器和手机等。它们内置的解码器大多或者是基于DSP，或者是RISC处理器，虽然基于汇编语言的解码程序已经很成熟高效，但是不方便移植。文中提出的优化解码程序是基于标准C语言的，只要添加不同类型的DSP头文件，就可以移植应用。已经成功解出MP3（44．1kHz，128kbps），并且满足国际音频组要求的限制精度。     

1300 V, 2 ms pulse inductive load switching test circuit with 20 ns selectable crowbar intervention

A non destructive inductive load switching (ILS) test apparatus with the capability of delivering high current pulses with a maximum 2 ms duration under a 1300 V supply is presented in this work. The system is also provided with a fast crowbar whose intervention is programmable with a 20 ns resolution and is intended to perform tests on power devices driving generic inductive loads. This kind of test is commonly used for quality control and prototype verification in power devices industry [Busatto G, Cascone B, Fratelli L, Balsamo M, Iannuzzo F, Velardi F. Non-destructive high temperature characterization of high-voltage IGBTs. Microelectron Reliab 2002;42(9–11):1635–40]. The high resolution crowbar intervention allows an immediate steering of the current away from the Device Under Test (DUT) after the failure event. In this way device damage is minimized so as to have a better understanding of the exact position of the failure, an essential parameter to infer the reasons that caused it [Trivedi M, Shenai K. Failure mechanisms of IGBTs under short-circuit and clamped inductive switching stress. IEEE Trans Power Electron 1999;14(1):108–16; Breglio G, Irace A, Riccio M, Spirito P, Hamada K, Nishijima T, et al. Detection of localized UIS failure on IGBTs with the aid of lock-in thermography. Microelectron Reliab 2008;48(8–9):1432–4].     

New block filtered-X LMS algorithms for active noise control systems

New block formulations for an active noise control (ANC) system using only convolution machines are presented. The proposed approaches are different from conventional block least-mean-square (LMS) algorithms that use both convolution and cross-correlation machines. The block implementation is also applied to the filtering of the reference signal by the secondary-path estimate. In addition to the use of the fast Fourier transform (FFT), the fast Hartley transform (FHT) is used to develop transform-domain ANC structures for reducing computational complexity. In the proposed approach, some FFT and FHT blocks are removed to obtain an additional reduction of the computational burden resulting in the reduced-structure of FFT-based block filtered-X LMS (FBFXLMS) and FHT-based block filtered-X LMS (HBFXLMS) algorithms. The computational complexities of these new ANC structures are evaluated.     

Fast Solution of Scattering From Conducting Structures by Local MLFMA Based on Improved Electric Field Integral Equation

In this paper, a local multilevel fast multipole algorithm (LMLFMA) based on an improved electric field integral equation (IEFIE) is developed to achieve fast and efficient solution of electromagnetic scattering from 3-D conducting structures. The IEFIE is used to reduce iteration number, and LMLFMA is applied to further accelerate the computation of matrix-vector multiplications in iteration, in which only the local interactions between subscatterers are taken into account. Numerical results show that the present method attains faster iterative convergence than traditional EFIE and less computational cost than MLFMA. The speedup can achieve at least 4–5 times while keeping an rms error of less than 2 dB.