Model identification in rapid thermal processing systems

Of the various techniques for controlling the temperature in rapid thermal processing (RTP), model-based control has the greatest potential for attaining the best performance, when the model is accurate. Some system identification methods are introduced to help obtain more accurate models from measured input-output data. For the first identification method, techniques for estimating the parameters (time constant and gain) of a particular physics-based model are presented. For the other, it is shown how to use the input-output measurements to obtain a black-box (autoregressive exogenous) model of the RTP system, which turns out to have better predictive capability. For each problem, the theoretical derivation of the identification technique and assumptions on which it is based are summarized, and experimental results based on data collected from an RTP system are described. Studying the DC response using the identified model led to a reconfiguration of the chamber geometry of the existing RTP system to more effectively distribute the light energy from the lamps     

Design and modeling of rapid thermal processing systems

The concept of rapid thermal processing (RTP) has many potential applications in microelectronics manufacturing, but the details of chamber design, temperature dynamics, process control, and temperature measurement remain active areas of research. This paper discusses the design rules used in an RTP test bed installed at SEMATECH with respect to the placement of lamps and the geometry and reflectivity of the enclosure. The distribution of light across the wafer was modeled, and a theory fur the wafer's dynamic temperature response was derived analytically with a few simplifying assumptions, parameters for this model were estimated from experimental data to yield a set of linear ordinary differential equations with temperature dependent coefficients. This particular model form is convenient for control system design and analysis     

A contribution to optimal lamp design in rapid thermal processing

Recent studies of wafer temperature control in rapid thermal processing systems have indicated that a multiring circularly symmetric lamp configuration with independent (multivariable) control of the power applied to each ring is likely to be more successful than the earlier lamp design approaches. An important issue in such multiring lamp systems is the optimal shaping of the output heat flux profile (HFP) of each ring to provide maximum controllability of the wafer temperature. In this paper we seek to optimize the ring HFP's via the lamp design parameters: ring positions and widths. We start by determining the heat loss profiles over the wafer surface for a variety of temperature setpoints and processing conditions. In order to maintain temperature uniformity across the wafer at a given setpoint, the lamp system should provide a compensating HFP. The total lamp HFP is the sum of the individual ring HFPs weighted by their respective applied powers. The HFP's are, in turn, functionally dependent on the lamp design parameters and this dependence can be measured through a calibration process. Therefore, the resulting optimization problem reduces to determining the lamp design parameters that result in lamp HFP's which best approximates the collection of the wafer heat loss profiles. Our method provides a practical technique for determining the optimal lamp design parameters     

Model-based emissivity correction in pyrometer temperature controlof rapid thermal processing systems

Single-wavelength pyrometers are most often used to infer wafer temperature in rapid-thermal-processing (RTP) systems. A constant wafer emissivity is assumed with a pyrometer, but a variation in the wafer's surface emissivity can result in an error in the inferred temperature which affects the temperature control of the RTP system. A time-dependent variation is evident in rapid thermal chemical vapor deposition where the emissivity is a function of the film type and thickness. An approach which uses a physically based model of the emissivity variation as part of the feedback control loop is described. The technique employs a first-order model of the emissivity as a function of film thickness from which a projected actual wafer temperature is inferred. The film thickness is approximated using a valid growth-rate expression and temperature as a function of time. These models are then incorporated into the feedback loop of the RTP control system     

Modelling of rapid thermal processing

An overview is given of modelling issues in rapid thermal processing. Firstly, the influence of surface and bulk properties on wafer emissivity is discussed. Secondly, the influence of back-side layers, wafer transparency and back-side roughness on temperature measurement is discussed. Thirdly, several causes of temperature non-uniformity are mentioned.     

Rule-based adaptive configuration selection for analog design systems

A configuration selection tool for rule-based analog IC design is presented. A fast determination of proper analog circuit configuration plays an eminent role in the initial design phase. This appears to be quite demanding due to the large number of parameters and side issues involved. In order to ease concept engineering in analog design an adaptive algorithm has been developed for configuration selection. It can be used in design systems that rely on use of expert knowledge stored as a set of rules in a knowledge base, e.g., expert systems, design assistants, etc. The developed learning algorithm also helps eliminate inconsistent, incorrect, and redundant rules in rule bases used in analog design systems. The rule base is continuously adapted, depending on the correctness of the decisions the rules have invoked.     

Recent developments in rapid thermal processing

Rapid thermal annealing (RTA) with a short dwell time at maximum temperature is used with ion implantation to form shallow junctions and polycrystalline-Si gate electrodes in complementary, metal-oxide semiconductor (CMOS) Si processing. Wafers are heated by electric lamps or steady heat sources with rapid wafer transfer. Advanced methods use “spike anneals,” wherein high-temperature ramp rates are used for both heating and cooling while also minimizing the dwell time at peak temperature to nominally zero. The fast thermal cycles are required to reduce the undesirable effects of transient-enhanced diffusion (TED) and thermal deactivation of the dopants. Because junction profiles are sensitive to annealing temperature, the challenge in spike annealing is to maintain temperature uniformity across the wafer and repeatability from wafer to wafer. Multiple lamp systems use arrayed temperature sensors for individual control zones. Other methods rely on process chambers that are designed for uniform wafer heating. Generally, sophisticated techniques for accurate temperature measurement and control by emissivity-compensated infrared pyrometry are required because processed Si wafers exhibit appreciable variation in emissivity.     

Transient effects in rapid thermal processing

Using a realistic model of a rapid thermal processing chamber including Navier-Stokes calculations of the gas losses, the stresses and yield strengths of silicon wafers were determined for several linear ramp rates. It was found that the stress to yield strength ratio is a sensitive function of the ramp rate and the radiant uniformity. Radiation patterns that produce good steady-state thermal nonuniformity overheat the wafer edges during heating transients, leading to high stress levels     

Adaptive control approach of rapid thermal processing

This paper presents an adaptive control approach for achieving the control of the wafer temperature in a rapid thermal processing system (RTP). Numerous studies have addressed the temperature control problem in RTP and most researches on this problem require exact knowledge of the systems dynamics. However, it is difficult to acquire this exact knowledge. Thus, various approaches cannot guarantee the desired performance in practical application when there exist some modeling errors between the model and the actual system. In this paper, an adaptive control scheme is applied to RTP without exact information on the dynamics. The system dynamics are assumed to be an affine nonlinear form, and the unknown portion of the dynamics are estimated by a neural network referred to a piecewise linear approximation network (PLAN). The controller architecture is based on an adaptive feedback linearization scheme and augmented by sliding mode control. The performance of the proposed method is demonstrated by experimental results on an RTP system of Kornic Systems Corporation, Korea.     

Polysilicon capacitor failure during rapid thermal processing

Rapid thermal-processing-induced polysilicon capacitor failure is investigated. Polysilicon-SiO2-Si capacitors fail at the perimeter upon heating to temperatures in excess of 1050°C for a few seconds in vacuum or argon. Shorting occurs when the silicon grains deform due to surface energy-driven diffusion and extend over etch-damaged oxide surrounding the capacitor. The presence of oxygen or nitrogen during, or regrowth of the damaged oxide prior to, rapid thermal processing substantially reduces the failure rate.     

Defect generation and gettering during rapid thermal processing

The authors present results showing that deep-level transient spectroscopy (DLTS) is particularly efficient in identifying the origin of rapid thermal processing (RTP) related defects. It was found that defects are mostly related to residual impurities present in the as-grown silicon wafers or unintentionally introduced during high-temperature processing steps. It was shown, in particular, that these impurities can be thermally annealed out or neutralized by a hydrogenation process. In addition, the authors demonstrated that these impurities can be swept out of the active region of the device by a gettering effect during the RTP which is similar to that occurring in a classical thermal treatment     

In-situ processing using rapid thermal chemical vapor deposition

Metal-Oxide-Semiconductor Capacitors (MOSCAP’s) were fabricated using Rapid Thermal Processing (RTP) techniques. MOSCAP’s that received in-situ polysilicon gate deposition after oxide growth evinced significantly tighter oxide breakdown voltage distribution as compared to devices that received ex-situ polysilicon deposition. Capacitance-Voltage (C-V) measurements of electrically unstressed and stressed devices indicate that the oxide charge, interface state density, electron trapping, and interface state generation characteristics are identical, irrespective of the mode of polysilicon gate deposition. It is concluded that, while in-situ processing may be capable of reducing particle related defects, no improvement is seen in the intrinsic properties of the oxide itself.     

Thin polyoxide films grown by rapid thermal processing

The growth of thin (80-200 Å) oxide films by rapid thermal processing (RTP) on LPCVD poly and amorphous silicon is reported. Oxide growth kinetics are affected by dopant concentration, implant species, and preoxidation anneal conditions. Breakdown fields > 11 MV/ cm have been measured. Constant current stress measurements indicate a higher rate of negative charge trapping in oxides grown on top of polysilicon as compared to amorphous silicon.     

A model for rapid thermal processing: achieving uniformity throughlamp control

A first-principles approach to the modeling of a rapid thermal processing (RTP) system to obtain temperature uniformity is described. RTP systems are single wafer and typically have a bank of heating lamps which can be individually controlled. Temperature uniformity across a wafer is difficult to obtain in RTP systems. A temperature gradient exists outward from the center of the wafer due to cooling for a uniform heat flux density on the surface of the wafer from the lamps. Experiments have shown that the nonuniform temperature of a wafer in an RTP system can be counteracted by adjusting the relative power of the individual lamps, which alters the heat flux density at the wafer. The model is composed of two components. The first predicts a wafer's temperature profile given the individual lamp powers. The second determines the relative lamp power necessary to achieve uniform temperature everywhere but at the outermost edge of the wafer (cooling at the edge is always present). The model has been verified experimentally by rapid thermal chemical vapor deposition of polycrystalline silicon with a prototype LEISK RTP system. The wafer temperature profile is inferred from the poly-Si thickness. Results showed a temperature uniformity of ±1%, an average absolute temperature variation of 5.5°C, and a worst-case absolute temperature variation of 6.5°C for several wafers processed at different temperatures     

Signal processing principles for systems analysis and design

The author indicates, for the benefit of system designers, how and to what extent independently available information-or generic characteristics derived from the signal itself-can be used to enhance the extraction of wanted signals in the presence of noise or interference. To bring out the commonalities in apparently different problems or methods, he uses the `state-space' concept, common to the dimensions of time, frequency, antenna aperture and image space, and treats signal processing as a sequence of transformations subject to a set of limiting constraints     

Model reduction for optimization of rapid thermal chemical vapordeposition systems

A model of a three-zone rapid thermal chemical vapor deposition (RTCVD) system is developed to study the effects of spatial wafer temperature patterns on polysilicon deposition uniformity. A sequence of simulated runs is performed, varying the lamp power profiles so that different wafer temperature modes are excited. The dominant spatial wafer thermal modes are extracted via proper orthogonal decomposition and subsequently used as a set of trial functions to represent both the wafer temperature and deposition thickness. A collocation formulation of Galerkin's method is used to discretize the original modeling equations, giving a low-order model which loses little of the original, high order model's fidelity. We make use of the excellent predictive capabilities of the reduced model to optimize power inputs to the lamp banks to achieve a desired polysilicon deposition thickness at the end of a run with minimal deposition spatial nonuniformity. Since the results illustrate that the optimization procedure benefits from the use of the reduced-order model, our future goal is to integrate the model reduction methodology into real-time and run-to-run control algorithms. While developed in the context of optimizing a specific RTP process, the model reduction techniques presented in this paper are applicable to other materials processing systems     

Formation of titanium silicide films by rapid thermal processing

Titanium silicide thin films, sputter deposited from a composite silicide target, have been rapidly sintered in ∼10 s to produce extremely uniform highly conductive layers (≲ Ω/sq plusmn; 1 percent over a 4-in wafer) with film stress comparable to furnace-annealed films. Such films are suitable for VLSI applications. In addition, silicide formation and activation of ion-implanted species in adjacent Si regions can be accomplished in the same rapid processing step without significant dopant redistribution.     

Towards high-eficiency silicon solar cells by rapid thermal processing

Rapid thermal processing can offer many advantages, such as small overall thermal budget and low power and time consumption, in a strategy focused on cost-effective techniques for the preparation of solar cells in a continuous way. We show here that this very short duration (a few tens of seconds) of isothermal heating performed in a lamp furnace can be used for many thermal steps of silicon solar cell processing. Rapid thermal processing was applied to form the p-n junction from a phosphorus-doped spin-on silica film deposted on (100) silicon substrates at typical processing temperatures between 800 and 1100°C. the solar cells showed conversion efficiencies as good as those processed in a conventional way.     

Ion implantation and rapid thermal processing of Ill-V nitrides

Ion implantation doping and isolation coupled with rapid thermal annealing has played a critical role in the realization of high performance photonic and electronic devices in all mature semiconductor material systems. This is also expected to be the case for the binary III-V nitrides (InN, GaN, and A1N) and their alloys as the epitaxial material quality improves and more advanced device structures are fabricated. In this article, we review the recent developments in implant doping and isolation along with rapid thermal annealing of GaN and the In-containing ternary alloys InGaN and InAlN. In particular, the successful n- and p-type doping of GaN by ion implantation of Si and Mg+P, respectively, and subsequent high temperature rapid thermal anneals in excess of 1000°C is reviewed. In the area of implant isolation, N-implantation has been shown to compensate both n- and p-type GaN, N-, and O-implantation effectively compensates InAlN, and InGaN shows limited compensation with either N- or F-implantation. The effects of rapid thermal annealing on unimplanted material are also presented.     

Challenges and current status in 300 mm rapid thermal processing

Rapid Thermal Processing (RTP) will be indispensable to meet the process requirements of future device and integrated circuit (IC) generations. The paper reviews several approaches to manage the challenges of single-wafer 300 mm heat treatment, including the most important issues in RTP system technology: temperature measurement and accuracy, fast ramp capability, process repeatability, ultra-shallow junction formation and process uniformity for various applications in concurrent IC manufacturing. The paper also focuses on the substantial improvement of key system features. The implementation of a new lamp intensity modulation-based and emissivity independent temperature measurement technique yields a measurement uncertainty of ±1.5°C within an emissivity range from 0.2 to 0.8 for key process applications.