Test Challenges for 3D Integrated Circuits

One of the challenges for 3D technology adoption is the insufficient understanding of 3D testing issues and the lack of DFT solutions. This article describes testing challenges for 3D ICs, including problems that are unique to 3D integration, and summarizes early research results in this area. Researchers are investigating various 3D IC manufacturing processes that are particularly relevant to testing and DFT. In terms of the process and the level of assembly that 3D ICs require, we can broadly classify the techniques as monolithic or as die stacking.     

The DoD Initiative in Integrated Circuits

The Department of Defense's Very High-Speed IC Program includes research in areas such as submicron fabrication technology and advanced signal processing. DoD foresees results beneficial to both commercial and military applications.     

辐照加固集成电路

本文叙述了辐照加固集成电路在军事武器及航天设备中的意义，重点介绍了已有的辐照加固集成电路，如微处理器系列电路、数字电路、接口电路，最后通过对这些电路所用的加工技术的分析，提出了我国发展辐照加固集成电路的建议。     

Reliability of CMOS Integrated Circuits

CMOS ICsare being produced using a variety of processes, and considerable data is now available on their reliability and failure mechanisms.     

Implementing Qubits with Superconducting Integrated Circuits

Superconducting qubits are solid state electrical circuits fabricated using techniques borrowed from conventional integrated circuits. They are based on the Josephson tunnel junction, the only non-dissipative, strongly non-linear circuit element available at low temperature. In contrast to microscopic entities such as spins or atoms, they tend to be well coupled to other circuits, which make them appealling from the point of view of readout and gate implementation. Very recently, new designs of superconducting qubits based on multi-junction circuits have solved the problem of isolation from unwanted extrinsic electromagnetic perturbations. We discuss in this review how qubit decoherence is affected by the intrinsic noise of the junction and what can be done to improve it. PACS: 03.67.-a, 03.65.Yz, 85.25.-j, 85.35.Gv     

Phototransistors for CMOS Optoelectronic Integrated Circuits

Integrated pnp phototransistors (PT) built in 0.6 μm OPTO ASIC CMOS are presented. The production starts with a low doped epitaxial wafer as bulk material. This work presents several different types of phototransistors due to the realization of base and emitter areas. The different types are optimized for different goals, e.g. responsivity or bandwidth. Responsivities up to 76 A/W, 35 A/W for DC light at 675 nm and 850 nm, respectively, as well as 37.2 A/W for modulated light at 300 kHz and 850 nm wavelength were achieved. On the other hand bandwidths up to 14 MHz with lower responsivity were achieved with different design of base and emitter area. Due to the fact that the used process is a production silicon CMOS technology, cheap integration of an integrated optoelectronic circuit is possible. Possible applications are low cost, highly sensitive optical receivers, optical sensors, systems-on-a-chip for optical distance measurement or combined to an array even a 3D camera.     

基于度量认证的协同集成可信部署技术

协同开发技术是进行控制系统软件开发的重要方法,其中的软件集成部署是协同开发技术的重要一环.随着软件规模越来越大,复杂性越来越高,现有的软件集成部署方法由于缺乏标准统一的部署规范和安全机制,所以会存在集成部署效率低下和安全性较差的问题.针对上述问题,提出了一种基于度量认证的协同集成部署方法,解决在分布式协同开发环境下集成部署工作带来的安全和效率问题.本文的主要思想是利用一种安全关联协议,在软件部署双方之间建立可信的安全传输通道,继而根据统一的打包部署规范,完成软件的集成和部署工作.理论分析和实验结果表明,该方案统一了软件打包部署规范,优化了完整性度量算法,减少了认证和软件部署的时间,并且由于部署双方在准备阶段已建立了安全关联,所以提高了整个软件部署过程的安全性.本文的研究内容能够在分布式开发环境下完成安全且高效的软件集成部署工作.     

电力机房一体化可信监控装置设计

提出了一种新型机房一体化可信监控装置设计方案.该方案所选核心芯片LS1043A具备超强边缘计算能力,利用PCIe总线扩展构建7个数据通道,桥接远端业务终端与功能扩展板,支持四遥、串口、4G/5G模块业务应用,亦可根据具体需求适配不同类型扩展板,另外通过6路千兆以太网网络衔接智能化远程监控终端.本方案高效实用,充分利用P...     

Computer Aided Design for Large-Scale Integrated Circuits

The complexity of integrated circuits has increased steadily over the past several years from circuits consisting of simple gates through Medium Scale Integration (MSI) and Large Scale Integration (LSI). Fabrication techniques for LSI have evolved from well-established integrated circuit technology. Because of the large physical size and the large number of components on the individual silicon die, production techniques have been substantially improved in order to maintain reasonable yields. However, the most significant effects of LSI on the semiconductor manufacturer are in the areas of design and testing; techniques used in the past for simpler integrated circuits are inadequate for LSI.     

网络化边缘扫描集成电路测试系统研制

简单论述了边缘扫描测试技术,详述了研制的网络化边缘扫描测试系统的构建方法.针对测试系统的实际应用进行了说明.     

Inductive Fault Analysis of MOS Integrated Circuits

Inductive Fault Analysis (IFA) is a systematic Procedure to predict all the faults that are likely to occur in MOS integrated circuit or subcircuit The three major steps of the IFA procedure are: (1) generation of Physical defects using statistical data from the fabrication process; (2) extraction of circuit-level faults caused by these defects; and (3) classification of faults types and ranking of faults based on their likelihood of occurrence Hence, given the layout of an IC, a fault model and a ranked fault list can be automatically generated which take into account the technology, layout, and process characteristics. The IFA procedure is illustrated by its applications to an example circuit. The results from this sample led to some very interesting observations regarding nonclassical faults.     

新型集成电路的综述

本文按通用集成芯片和专用集成芯片的分类对典型的集成芯片的最新进展作了简述，针对目前的主流芯片如：单片机和DSP(数字信号处理器)的发展作了综述。并指出了有关的信息收集网址，它为使用集成芯片开发智能产品的工作者提供了有价值的参考。     

关于集成电路设计中噪声问题的探讨

集成电路的发展在给我们生活带来便利的同时,自身也在不断的完善。在集成电路设计中,噪声已经成为一个需要迫切解决的问题。本文主要分析集成电路设计中几种常见的噪声问题的形成和处理方式,供相关人士查阅参考。     

集成电路中的规则性提取算法

通过对现有文献中的规则性提取算法的全面分析,提出了一个新的基于图论方法的规则性提取算法.此算法可以生成任意给定电路系统的模块,并且在同构的前提下自动将模块分类.在生成模块的过程中保证相同顶点的模块只出现一次,降低了模块分类时的复杂性.算法对电路以及模块的结构没有任何限制,弥补了现有算法的不足.     

VirMIC—一个基于Internet的IC虚拟制造环境

该文展示了一个Internet环境下的集成电路虚拟制造环境VirMIC,着重于系统的三个核心模块,即电路性能仿真与成品率优化模块、工艺线仿真与调度模块和产品决策模块,电路性能仿真与成品率优化模块,建立了一个基于OO-DCE的技术CAD环境,以这个环境为依托,通过协调效益和成品率进行了工艺流程的可制造性优化设计;工艺线仿真与调度模块,以一定的工艺流程和制造系统配置为基础,建立制造系统Petri网模型,从而进行系统性能仿真和生产调度,对制造系统的整体性能进行优化;产品决策模块以前两个模块为基础,对如何选择合作伙伴,如何在合作伙伴之间分配用户提交的制造负荷,为构成“虚拟企业”提供指导性信息,以上三个模块构成了Vir-MIC系统的功能核心。     

自承认技术债的研究:问题、进展与挑战

技术债是一个指以牺牲长期代码质量为代价来实现短期项目目标的隐喻.其中,那些由开发者有意引入项目中的技术债被称为自承认技术债(self-admitted technical debt,SATD),通常以代码注释的形式存在于软件项目中.SATD的存在给软件质量和鲁棒性带来了巨大挑战.为了识别并且及时地偿还SATD来保障代码...     

用Tabu Search解决基于结群的电路划分问题

电路划分是VLSI物理设计中最重要的步骤之一。本文提出了一种自底向上的结群策略，首先将具有高互连关系的电路模块进行结群，然后再将结群后的宏模块进行划分，用Tabu Search启发式算法进行求解，测试电路选择标准MCNC benchmarks，实验结果表明在解的质量相当情况下，运算时间较少。     

Concurrent Placement and Routing in the Design of Integrated Circuits

For the problem arising in the design of integrated chips, an efficient heuristic approach was proposed. It unites the stages of placing the logical elements (devices) on the chip and performing their detailed routing. At that, it minimizes both the critical (maximum) delay and the chip area required for routing.