一种新型宽带接收机I/Q通道失配的数字校正方法

由于各种因素的影响,I/Q通道之间通常会发生失配现象,这会降低接收机的动态范围,进而影响接收机的性能。本文提出了一种宽带接收机中L/Q幅相误差校正的数字方法：首先通过一种时域方法以获得误差信息,籍此计算校正所需参数,再由Newton插值多项式构造滤波器组对I/Q信号进行滤波校正。仿真表明,这种数字校正方法能有效地提高宽带接收机I/Q通道的正交一致性。     

一种超宽带零中频接收机的设计与实现

针对雷达、电子战和通信等多功能一体化探测要求,设计了一种基于零中频架构的0.3～18 GHz超宽带接收机。硬件系统由宽带数字接收机、超宽带模拟解调器和超宽带频率源组成,实现了0.3～2 GHz频段信号的直接数字化接收和2～18 GHz频段信号的模拟正交解调。给出了FPGA软件处理流程,采用了基于镜像功率检测方法对I/Q支路进行时延误差校正,采用了基于矩阵求逆最小方差法对I/Q支路进行幅相误差校正。样机测试结果表明,接收机的最大瞬时带宽为4 GHz,校正后的镜像抑制度超过50 dB。     

一种宽带接收机幅相不平衡的校正方法

由模拟器件构成的宽带正交解调接收机会由于正交通道的幅相不一致性造成整个系统的失真，进而影响整个接收系统的性能。本文仔细分析了幅相误差对接收机性能的影响，提出了基于FIR滤波的一种数字域校正的方法。通过计算机彷真，证实了该方法的可行性。     

宽带信号I/Q采样不平衡校正方法研究

针对宽带信号模拟正交下变频时产生的I/Q信号不平衡问题,本文提出了一种在数字域对I/Q信号不平衡的校正方法,建立了 I/Q信号不平衡的数字模型,分析了 I/Q信号不平衡给系统带来的影响,推导了 I/Q信号不平衡的校正方法,并对校正结果进行了仿真验证,该方法已在某设备中成功应用.     

基于改进NLMS算法的通道校正技术研究

在电子侦察中,由于数字接收机通道中的放大器、混频器中的本振以及低通滤波器等器件的非理想性,造 成了接收机通道之间的幅相不平衡现象,极大地影响了无源测向的精度。本文在自适应滤波理论的基础上,提出了一种基 于改进NLMS算法的自适应通道校正方法。改进的算法在无法得到信号先验信息的情况下,也能获得较快的收敛速度和较 小的失调量,完成通道校正过程。基于该算法的通道校正方法不需要参考信号,直接利用天线接收到的雷达信号完成自校 正过程。仿真结果表明,该方法能有效提高通道的幅相一致性,是一种较好的通道校正方法。     

DDC在雷达正交接收机中的应用

研制了一种基于DDC芯片的直接中频数字化雷达正交接收机 ,分析了I/Q通道的增益误差和正交误差对解调输出信号的影响。结果表明 ,设计的接收机通道间误差对解调输出的影响完全可以忽略。最后对接收机性能进行了测试 ,得到了理想的解调结果。     

数字校正在角误差测量中的应用

分析单脉冲跟踪雷达和差通道幅相不平衡及I、Q不正交性对角误差测量的影响.并提供一种I、Q正交校正与和差支路幅相不平衡校正的方法.     

基于脉冲分裂的宽带雷达系统通道误差校正方法

在不改动宽带雷达系统校准通道硬件的前提下,该文提出一种校正宽带雷达系统传递函数误差及正交解调误差的新方法。该方法通过对通道误差特征的分析,结合宽带线性调频信号的时频关系,根据分裂脉冲方法以分离通道误差造成的镜频干扰和传递函数非理想,得到宽带雷达系统传递函数的完全表征,由此构建相应的雷达回波校正函数,实现接收回波的误差校正。针对有效带宽的实际雷达系统的通道误差校正实验,验证了该文方法的有效性,且与传统的方法相比,该文方法显现出适用性强的特点。     

一种改进的数字乘积检波方法

数字乘积检波(DPD:Digital Product Detector)是一种工程实现数字正交解调的简便方法[1][2],该方法克服了模拟正交解调I、Q通道不平衡的缺点[1],在雷达中频或射频信号采样中得到了广泛应用.然而该方法获得的I、Q数据在时间上不同步,需要进行分数阶多相插值滤波修正[1]～[8],由于分数阶多相插值滤波器无法做到I、Q通道幅度和相位的同时匹配[2],其不匹配引入的镜像干扰对工作在极低信噪比下的车载前视步进频率雷达来说非常不利.本文从信号与系统基本原理[9]出发,对DPD方法进行改进,提出了一种不需要对I、Q数据进行分数阶多相插值滤波,就可以得到时间同步I、Q数据的正交解调方法,该方法简便灵活,容错性强,用低通滤波器代替分数阶多相插值滤波器,可以做到两个通道幅度和相位的同时匹配,可以很好地控制I、Q分量幅度和相位的一致性.     

高分辨率SAR宽带I/Q正交解调器的实验研究

宽带I／Q正交解调器是高分辨率SAR系统的关键部件之一。本文讨论了宽带I／Q正交解调器对高分辨SAR系统性能的影响，分析了其主要误差来源，给出了设计原则，介绍了具体电路的设计过程，并给出实验结果。实验表明，该解调器用于高分辨SAR系统是有效的。     

Channel estimation in the presence of transmitter and receiver I/Q mismatches for OFDM systems

In this paper, we study the problem of channel estimation in the presence of the transmitter and receiver inphase and quadrature-phase (I/Q) mismatches for orthogonality frequency division multiplexing (OFDM) systems. A new concept called channel residual energy (CRE) is introduced. We show that by minimizing CRE, we can jointly estimate the transmitter and receiver I/Q mismatches without knowing the channel information. The optimal solution is given in closed form. Once we have the I/Q parameters, an estimate of the channel response can be obtained by simple substitution. The proposed method needs only one OFDM block for training and the training data can be arbitrary. Simulation results show that the proposed method can achieve a good performance.     

I/Q mismatch compensation using adaptive decorrelation in a low-IF receiver in 90-nm CMOS process

We present a single multiplier based adaptive I/Q mismatch compensation circuit for narrowband quadrature receivers. Adaptive decorrelation between I and Q channel data is used for correcting gain and phase mismatches. Adaptation step size is computed from L/sub 1/-norm inverse power measurement and a gear-shifting mechanism is used that allows fast initial convergence and slow adaptation on actual burst data. Image rejection ratio in excess of 50 dB is reported for GSM receiver after compensation allowing the receiver to use IF frequencies higher than half of the channel bandwidth. The presented mismatch compensation circuit is implemented as part of a single-chip GSM wireless transceiver fabricated in a 90-nm digital CMOS process. The presented techniques are, however, equally applicable to other narrowband packet-based applications.     

Cascaded Complex ADCs With Adaptive Digital Calibration for $I/Q$ Mismatch

A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch.     

DBF体制雷达中多通道数字中频接收机设计

介绍了DBF体制雷达中多通道数字中频接收机的研制思路、方案，其基本思想是用中频直接采样和数字I／Q解调技术代替模拟I／Q解调；并应用LNDS技术解决DBF体制雷达系统中多信道、高速大容量数据的传输问题。详细分析了研制中的关键技术；给出了试验测试结果。     

Circularity-Based I/Q Imbalance Compensation in Wideband Direct-Conversion Receivers

Communication receivers that utilize I/Q downconversion are troubled by amplitude and phase mismatches between the analog I and Q branches. These mismatches are unavoidable in practice and reduce the obtainable image frequency attenuation to the 20-40-dB range in practical receivers. In wideband multichannel receivers, where the overall bandwidths are in the range of several megahertz and the incoming carriers located at each other's mirror frequencies have a high dynamic range, the image attenuation of the analog front-end (FE) alone is clearly insufficient. In this paper, two novel blind low-complexity I/Q imbalance compensation techniques are proposed and analyzed to digitally enhance the analog FE image attenuation in wideband direct-conversion receivers. The proposed algorithms are grounded on the concept of circular or proper complex random signals, and they are, by design, able to handle the often overlooked yet increasingly important case of frequency-dependent I/Q mismatches. The first technique is an iterative one, stemming from adaptive filtering principles, whereas the second one is a moment-estimation-based block method. The performance of the algorithms is evaluated through computer simulations, as well as real-world laboratory signal measurement examples in practical multicarrier receiver cases. Based on the obtained results, the proposed compensation techniques can provide very good compensation performance with low computational resources and are robust in the face of different imbalance levels and dynamics of the received signals, as well as many other crucial practical aspects such as the effects of the communications channel and carrier synchronization.     

An 81-MHz IF receiver in CMOS

An 81-MHz CMOS IF receiver for digital wireless applications is presented. The receiver consists of a continuous-time IF amplifier, a subsampling switched-capacitor gain stage, and a sixth-order bandpass ΣΔ A/D converter. Incorporating 24 dB of programmable gain, the receiver achieves 92 dB of dynamic range in a 200 kHz bandwidth. Due to its IF sampling nature, the reciever is immune to de offset, flicker noise, and errors due to mismatches between I and Q signal paths. By utilizing a pseudo two-path resonator architecture in the bandpass ΣΔ A/D converter, a stable passband center frequency which is immune to capacitor mismatch is achieved. Implemented in 0.8-μm CMOS, this chip uses a single 3 V supply and consumes 14.4 mW of power     

数字合成孔径雷达接收机设计

为了解决模拟合成孔径雷达接收机带来的幅相不平衡等诸多问题,设计了一种基于高速A/D转换和FPGA高速信号处理的数字合成孔径雷达中频接收机.该设计结构简单、信号带宽大、镜频抑制比高.对多相滤波正交解调算法进行了改进,给出了数字中频接收机的工作原理和系统结构框图,设计了基于Virtex-4 FPGA的信号处理模块.仿真验证结果表明该设计完全符合系统设计参数的要求,可以应用于高分辨率合成孔径雷达.     

A 400-Ms/s frequency translating bandpass sigma-delta modulator

A bandpass Σ-Δ modulator is described in this paper that uses frequency translation inside the Σ-Δ modulator loop to take advantage of the attributes of both continuous-time and discrete-time circuits. A CMOS direct-conversion modulator digitizes a 200 kHz intermediate-frequency signal centered at 100 MHz and produces baseband I/Q outputs with a peak signal-to-noise ratio of 54 dB. Images due to I/Q mismatches are suppressed by 50 dB. This 0.35-μm digital CMOS chip operates from a 2.7/3.3-V supply, dissipates 330 mW, and occupies 3.2 mm²