Responsivity and lifetime of resonant-cavity-enhanced HgCdTe detectors

Resonant-cavity-enhanced HgCdTe structures have been grown by molecular beam epitaxy, and photoconductors have been modelled and fabricated based on these structures. Responsivity has been measured and shows a peak responsivity of 8 × 10⁴ V/W for a 50 × 50 μm² photoconductor at a temperature of 200 K. The measured responsivity shows some agreement with the modelled responsivity across the mid-wave infrared window (3–5 μm). The measured responsivity is limited by surface recombination, which limits the effective lifetime to ≈15 ns. The optical cut-off of the detector varies with temperature as modelled from 5.1 μm at 80 K to 4.4 μm at 250 K. There is strong agreement between modelled peak responsivity and measured peak responsivity with varying temperature from 80 to 300 K.     

Fabrication of NbN/AlN/NbN junctions with Al embedding circuits on Si membrane for 1.5 THz SIS mixers

A process has been developed to fabricate NbN tunnel junctions and 1.5 THz SIS mixers with Al electrodes and Al/SiO₂/Al microstrip tuning circuits on thin Si membranes patterned on silicon on insulator wafers (SIMOX). High Josephson current density (J_c up to 2×10⁴ A/cm²) NbN/AlN/NbN and NbN/MgO/NbN SIS junctions have been fabricated with a reasonably good V_m quality factor and energy gap values close to 5 meV at 4.2 K on (100) oriented 3 inches SIMOX wafers covered by a thin (∼8 nm) MgO buffer layer. The sputtering conditions critically influence the dielectric quality of both AlN and MgO tunnel barriers as well as the surface losses of NbN electrodes. 0.6-μm Si/SiO₂ membranes are obtained after processing of a whole wafer and etching the individual chips in EDP. Such a technology is applied to the development of a waveguide/membrane SIS mixer for use around 1.5 THz.     

Multilevel characteristics and operating mechanisms of nonvolatile memory devices based on a floating gate of graphene oxide sheets sandwiched between two polystyrene layers

Nonvolatile organic memory devices were fabricated utilizing a graphene oxide (GO) layer embedded between two polystyrene (PS) layers. Scanning electron microscope images of GO sheets sandwiched between two PS layers showed that the GO sheets were clearly embedded in the PS layers. Capacitance–voltage (C–V) curves of the Al/PS/GO/PS/n-type Si devices clearly showed hysteresis behaviors with multilevel characteristics. The window margin of the nonvolatile memory devices increased from 1 to 7 V with increasing applied sweep voltages from 6 to 32 V. The cycling retention of the ON/OFF switching for the devices was measured by applying voltages between +15 and −15 V. While the capacitance of the memory devices at an ON state have retained as 230 pF up to 10⁴ cycles, that at an OFF state maintained as 16 pF during three times of repeated measurements. The extrapolation of the retention data for the devices maintained up to 10⁶ cycles. The operating mechanisms of the nonvolatile organic memory devices with a floating gate were described by the C–V results and the energy band diagrams.     

Fabrication of single crystal field-effect transistors with phenacene-type molecules and their excellent transistor characteristics

Single crystal field-effect transistors (FETs) using [6]phenacene and [7]phenacene show p-channel FET characteristics. Field-effect mobilities, μs, as high as 5.6 × 10^?1 cm² V^?1 s^?1 in a [6]phenacene single crystal FET with an SiO₂ gate dielectric and 2.3 cm² V^?1 s^?1 in a [7]phenacene single crystal FET were recorded. In these FETs, 7,7,8,8-tetracyanoquinodimethane (TCNQ) was inserted between the Au source/drain electrodes and the single crystal to reduce hole-injection barrier heights. The μ reached 3.2 cm² V^?1 s^?1 in the [7]phenacene single crystal FET with a Ta₂O₅ gate dielectric, and a low absolute threshold voltage |V_TH| (6.3 V) was observed. Insertion of 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F₄TCNQ) in the interface produced very a high μ value (4.7–6.7 cm² V^?1 s^?1) in the [7]phenacene single crystal FET, indicating that F₄TCNQ was better for interface modification than TCNQ. A single crystal electric double-layer FET provided μ as high as 3.8 × 10^?1 cm² V^?1 s^?1 and |V_TH| as low as 2.3 V. These results indicate that [6]phenacene and [7]phenacene are promising materials for future practical FET devices, and in addition we suggest that such devices might also provide a research tool to investigate a material’s potential as a superconductor and a possible new way to produce the superconducting state.     

Direct imprint of Al foil for metallization of high-aspect ratio Al lines in nano/micro patterned SiO2/Si

Patterning techniques of Al micro/nano-structures become more and more critical as optical components and microelectronic devices continue to be scaled down. In this work, we fabricated gap-filled Al lines in SiO₂/Si masters by using the direct thermal imprint of molten Al. As a result, gap-filled Al lines with width ranging from 0.25 to 20 μm and depth ranging from 6 to 127 μm could be achieved without any further processing step such as CVD and PVD. The process studied here has shown the possibility to extend trench filling capability to 0.25 μm structures with 24:1 aspect ratio, which are difficult to be obtained by other conventional Al metallization methods.     

Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors

We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (I_D–V_G) curve due to the formation of a conducting channel layer. The specific contact resistance (ρ_C) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm²/V·s), ON/OFF current ratio (3.27×10⁶), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm² at V_G=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.     

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

Growth enhancement and field emission characteristics of one-dimensional 3,4,9,10-perylenetetracarboxylic dianhydride nanostructures on pillared titanium substrate

We have utilized the π–π interactions between 3,4,9,10-perylenetetracarboxylic dianhydride (PTCDA) molecules and temperature-induced morphology changes to synthesize one-dimensional (1D) nanostructures of PTCDA on a heated (ca. 100 °C) titanium substrate through vacuum sublimation. Because of the pillared Ti structures and the presence of reactive Ti–Cl sites, the titanium substrate played a crucial role in assisting the PTCDA molecules to form 1D nanostructures. The average diameter of the nanofibers deposited on the Ti-CVD substrate, a Ti substrate formed by chemical vapor deposition (CVD), at 100 °C was ca. 84 nm, with lengths ranging from 100 nm to 3 μm. When the PTCDA nanofibers were biased under vacuum, the emission current remained stable. The turn-on electric field for producing a current density of 10 μA/cm² was 8 V/μm. The maximum emission current density was 1.3 mA/cm², measured at 1100 V (E = 11 V/μm). From the slope of the straight line obtained after plotting ln(J/E²) versus 1/E, we calculated the field enhancement factor β to be ca. 989. These results demonstrate the PTCDA nanofibers have great potential for applicability in organic electron-emitting devices.     

Reduced contact resistance and highly stable operation in polymer thin-film transistor with aqueous MoOx solution contact treatment

We report on a newly developed solution process using MoO₃ for reducing source and drain (S/D) electrodes in organic thin-film transistor (TFT). By taking advantage of the difference in surface wettability between the gate dielectric layer and the S/D electrodes, the electrode treatment using the MoO_x solution was applied to polymer TFT with short channel lengths less than 10 μm. The contact resistance was noticeably reduced at the interface of the S/D electrodes in a polymer TFT using a pBTTT-C16. Furthermore, the field effect mobility for this TFT was enhanced from 0.03 to 0.1 cm²/V s. Most notably, the threshold voltage (V_th) shift under gated bias stress was less than 0.2 V after 10⁵ s, which is comparable to that of conventional poly crystalline Si TFT.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

Realizing high breakdown voltage for a novel interface charges islands structure based on partial-SOI substrate

A novel interface charge islands partial-SOI (ICI PSOI) high voltage device with a silicon window under the source and its mechanism are studied in this paper. ICI PSOI is characterized by a series of equidistant high concentration n⁺-regions on the bottom interface of top silicon layer. On the condition of high-voltage blocking state, inversion holes located in the spacing of two n⁺-regions effectively enhance the electric field of the buried oxide layer (E_I) and reduce the electric field of the silicon layer (E_S), resulting in a high breakdown voltage (V_B). It is shown by the simulations that the enhanced field ΔE_I and reduced field ΔE_S by the accumulated holes reach to 449 V/μm and 24 V/μm, respectively, which makes V_B of ICI PSOI increase to 663 V from 266 V of the conventional PSOI on 5 μm silicon layer and 1 μm buried oxide layer with the same silicon window length. On-resistance of ICI PSOI is lower than that of the conventional PSOI. Moreover, self-heating-effect is alleviated by the silicon window in comparison with the conventional SOI at the same power of 1 mW/μm.     

Fabrication and analysis of high-efficiency String Ribbon Si solar cells

This paper reports on the solar cell efficiencies of 18.3% and 16.8% (both 4 cm²) achieved on String Ribbon Si material using photolithography-defined and screen-printed front grid contacts, respectively, reinforcing the potential of String Ribbon Si for high-performance industrial cells. Rapid co-firing of screen-printed Al on the rear and low-frequency plasma-enhanced chemical vapor deposited single-layer SiN_x antireflection coating on the front in a rapid thermal processing unit was combined to enhance the as-grown minority carrier lifetime of 2–3 μs to 91 μs in processed String Ribbon Si cells. The performance of the best screen- printed String Ribbon Si cell (16.8%) was comparable to the 17.0% efficient planar float-zone (FZ) Si cell, which was processed simultaneously in the same run. However, the average performance of String Ribbon Si cells was 0.9%–1.4% lower in absolute efficiency relative to the FZ Si cells. Detailed characterization and analysis revealed that this is due to the presence of distributed electrically active defects, which could not be fully passivated, in spite of very effective defect hydrogenation during the cell processing.     

Sol–gel synthesized Titania nanoparticles deposited on porous polycrystalline silicon: Improved carbon dioxide sensor properties

Titania nanoparticles (TNPs) were synthesized by a sol–gel method in our laboratory using titanium tetrachloride as the precursor and isopropanol as the solvent. The particles׳ size distribution histogram was determined using ImageJ software and the size of TNPs was obtained in the range of 7.5–10.5 nm. The nanoparticle with the average size of 8.5 nm was calculated using Scherrer׳s formula. Homogeneous and spherical nanoparticles were characterized by X-ray diffraction (XRD), atomic force microscopy (AFM), field emission scanning electron microscopy (FESEM) and UV–visible spectroscopy (UV–vis). The X-ray powder diffraction analysis showed that the prepared sample (TNPs) has pure anatase phase. TNPs were deposited on porous polycrystalline silicon (PPS) substrate by electron beam evaporation. The TNPs thickness was 23±2 nm at 10⁻⁵ mbar pressure at room temperature. Porosity was performed by an anodization method. Since polycrystalline silicon wafers consist of different grains with different orientations, the pore size distribution in porous layer is non-uniform [1]. Therefore, the average diameter of pores can be reported in PPS layer analysis. Average diameter of pores was estimated in the range of 5 μm which was characterized by FESEM. The nanostructured thin films devices (Al/Si/PPS/TNPs/Al and Al/Si/PPS/Al) were fabricated in the sandwich form by aluminum (Al) electrodes which were also deposited by electron beam evaporation. Electrical measurements (I–V curves) demonstrated the semiconducting behavior of thin film devices. The gas sensitivity was studied on exposure to 10% CO₂ gas. As a result, conductivity of devices increased on exposure to CO₂ gas. The device with TNPs thin film (Al/Si/PPS/TNPs/Al) was more sensitive and, had better response and reversibility in comparison with the device without TNPs thin film (Al/Si/PPS/Al).     

Using metal/organic junction engineering to prepare an efficient organic base-modulation triode and its inverter

In this study, we investigated the influence of a buffer layer of molybdic oxide (MoO₃) at the metal/organic junction on the behavior of organic base-modulation triodes. The performance of devices featuring MoO₃/Al as the emitter electrode was enhanced relative to that of corresponding devices with Au and Ag, presumably because of the reduced in the contact barrier and the prevention of metal diffusion into the organic layer. The device exhibited an output current of ?16.1 μA at V_B = ?5 V and a current ON/OFF ratio of 10³. Using this architecture, we constructed resistance–load inverters that exhibited a calculated gain of 6.     

Self-aligned flexible organic thin-film transistors with gates patterned by nano-imprint lithography

Many applications that rely on organic electronic circuits still suffer from the limited switching speed of their basic elements – the organic thin film transistor (OTFT). For a given set of materials the OTFT speed scales inversely with the square of the channel length, the parasitic gate overlap capacitance, and the contact resistance. For maximising speed we pattern transistor channels with lengths from 10 μm down to the sub-micrometre regime by industrially scalable UV-nanoimprint lithography. The reduction of the overlap capacitance is achieved by minimising the source–drain to gate overlap lengths to values as low as 0.2 μm by self-aligned electrode definition using substrate reverse side exposure. Pentacene based organic thin film transistors with an exceptionally low line edge roughness <20 nm of the channels, a mobility of 0.1 cm²/Vs, and an on–off ratio of 10⁴, are fabricated on 4″ × 4″ flexible substrates in a carrier-free process scheme. The stability and spatial distribution of the transistor channel lengths are assessed in detail with standard deviations of L ranging from 185 to 28 nm. Such high-performing self-aligned organic thin film transistors enabled a ring-oscillator circuit with an average stage delay below 4 μs at an operation voltage of 7.5 V.     

Fluorene-based cathode interlayer polymers for high performance solution processed organic optoelectronic devices

A hydrophilic polyfluorene-based conjugated polyelectrolyte (CPE) Poly[9,9-bis(4′-(6″-(diethanolamino)hexyloxy) phenyl)fluorene], PPFN-OH (Scheme 1) has been synthesized and utilized as cathode interlayer for both polymer light emitting diodes (PLEDs) and solar cells (PSCs). For comparison, another CPE namely Poly[9,9-bis(6′-(diethanolamino)hexyl)fluorene] (PFN-OH) has also been investigated. They comprise the same polyfluorene backbone structures with, respectively, diethanolaminohexyl (PFN-OH) and diethanolaminohexoxyphenyl (PPFN-OH) substituents attached to the C9 carbon of the fluorene repeat unit. In comparison to reference devices with more reactive Ca/Al cathodes, utilizing these CPEs as interlayers allowed an Al cathode to be used for blue light emission PLEDs, yielding 51% and 92% enhancement of maximum luminous efficiency (LE) for PFN-OH and PPFN-OH, respectively. The PLEDs with PPFN-OH showed both higher maximum LE and maximum luminance (L) (LE = 2.53 cd/A at 6.2 V, L = 9917 cd/m² at 8.3 V) than devices with PFN-OH (2.00 cd/A at 4.1 V, 3237 cd/m² at 7.2 V). The PPFN-OH PLEDs also showed no significant roll-off in efficiency with increasing current density up to 400 mA/cm², indicating excellent electron injection ability and stability for this interlayer. The insertion of alkoxy-phenyl groups at the C9-position in PPFN-OH is clearly advantageous. This simple modification significantly improves the CPE cathode interlayer performance. Parallel investigations of the electron extraction properties of PPFN-OH in inverted architecture PSCs with PCDTBT:PC₇₀BM bulk heterojunction active layers demonstrated a power conversion efficiency enhancement of ∼19% (from 4.99% to 5.95%) for indium tin oxide cathode devices compared with reference devices using Ca/Al cathodes. These results confirm PPFN-OH to be a promising interlayer material for high performance solution processed organic optoelectronic devices.     

Scaling down of organic complementary logic gates for compact logic on foil

In this work, we realize complementary circuits with organic p-type and n-type transistor integrated on polyethylene naphthalate (PEN) foil. We employ evaporated p-type and n-type organic semiconductors spaced side by side in bottom-contact bottom-gate coplanar structures with channel lengths of 5 μm. The area density is 0.08 mm² per complementary logic gate. Both p-type and n-type transistors show mobilities >0.1 cm²/V s with V_on close to zero volt. Small circuits like inverters and 19-stage ring oscillators (RO) are fabricated to study the static and the dynamic performance of the logic inverter gate. The circuits operate at V_dd as low as 2.5 V and the inverter stage delay at V_dd = 10 V is as low as 2 μs. Finally, an 8 bit organic complementary transponder chip with data rate up to 2.7 k bits/s is fabricated on foil by successfully integrating 358 transistors.     

Megahertz operation of flexible low-voltage organic thin-film transistors

Bottom-gate, top-contact (inverted staggered) organic thin-film transistors with a channel length of 1 μm have been fabricated on flexible plastic substrates using the vacuum-deposited small-molecule semiconductor 2,9-didecyl-dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (C₁₀-DNTT). The transistors have an effective field-effect mobility of 1.2 cm²/V s, an on/off ratio of 10⁷, a width-normalized transconductance of 1.2 S/m (with a standard deviation of 6%), and a signal propagation delay (measured in 11-stage ring oscillators) of 420 ns per stage at a supply voltage of 3 V. To our knowledge, this is the first time that megahertz operation has been achieved in flexible organic transistors at supply voltages of less than 10 V.     

Measurement of stresses in Cu and Si around through-silicon via by synchrotron X-ray microdiffraction for 3-dimensional integrated circuits

Through-silicon via (TSV) has been used for 3-dimentional integrated circuits. Mechanical stresses in Cu and Si around the TSV were measured using synchrotron X-ray microdiffraction. The hydrostatic stress in Cu TSV went from high tensile of 234 MPa in the as-fabricated state, to ?196 MPa (compressive) during thermal annealing (in situ measurement), to 167 MPa in the post-annealed state. Due to this stress, the keep-away distance in Si was determined to be about 17 μm. Our results suggest that Cu stress may lead to reliability as well as integration issues, while Si stress may lead to device performance concerns.     

Comparative study of low-frequency noise in 0.18 μm and 0.35 μm gate-length nMOSFETs with gate area of 1.1 μm2

We analyzed the noise characteristics of 0.18 μm and 0.35 μm nMOSFETs with a gate area of 1.1 μm² in the frequency range of 1 Hz to 100 kHz. Both two- and four-finger devices were investigated and analyzed. The experimental results show that the noise of 0.35 μm gate-length nMOSFET possesses lower 1/f component than the 0.18 μm one, whereas the four-finger devices reveal less 1/f noise than those of with two-finger ones. Furthermore, we used time domain measurement of drain current and also the statistical analysis of wafer level on the random telegraph signals (RTS) tests, and the results showed that RTS noise is higher in devices with a 0.35 μm gate-length, and devices with a smaller gate finger width produce more RTS noise than devices with a larger gate finger width.