The study of hot-carrier stress on poly-Si TFT employing C-V measurement

The degradation of n-type and p-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) due to hot-carrier stress was investigated by capacitance-voltage (C-V) measurement. In C-V measurements, the fixed charges in the gate oxide of TFTs are not affected by a small-applied signal, whereas the trap states in the bandgap respond to the applied frequency, so that the dominant degradation mechanism of poly-Si TFTs can be evaluated. The capacitance (C/sub GS/) between the source and the gate, as well as the capacitance (C/sub GD/) between the drain and the gate, were measured. The difference between the C/sub GD/ and the C/sub GS/ indicates the location of degradation in the TFT. Our experimental results showed that the degradation of n-type TFTs was caused by additional trap states in the grain boundary, whereas the degradation of p-type TFTs was caused by electron trapping into the gate oxide.     

Radio-Frequency Operation of Transparent Nanowire Thin-Film Transistors

In this letter, radio-frequency characterization of fully transparent thin-film transistors (TFTs) based on chemically synthesized nanowires (NWs) has been carried out. The NW TFTs show current-gain cutoff frequency $f_{T}$ of 109 MHz and power-gain cutoff frequency $f_{max}$ of 286 MHz. The TFTs were fabricated on glass substrates using aligned $hbox{SnO}_{2}$ NWs as the transistor channel and sputtered indium–tin–oxide films as the source–drain and gate electrodes. Besides exhibiting $≫$ 100-MHz operation frequencies, the transparent NW TFTs show a narrow distribution of performance metrics among different devices. These results suggest the NW-TFT approach may be promising for high-speed transparent and flexible integrated circuits fabricated on diverse substrates.      

Metal-induced lateral crystallization of a-Si thin films by Ni-Co alloys and the electrical properties of poly-Si TFTs

We have introduced a new process in metal-induced lateral crystallization (MILC). By adding Co to the Ni-MILC process, the electrical characteristics of MILC poly-Si TFTs were considerably improved. In particular, a considerable decrease of TFT leakage current were achieved in both n-type and p-type devices.     

A new pixel circuit for driving organic light-emitting diode with low temperature polycrystalline silicon thin-film transistors

A new pixel circuit design for active matrix organic light-emitting diode (AMOLED), based on the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) is proposed and verified by SPICE simulation. Threshold voltage compensation pixel circuit consisting of four n-type TFTs, one p-type TFT, one additional control signal, and one storage capacitor is used to enhance display image quality. The simulation results show that this pixel circuit has high immunity to the variation of poly-Si TFT characteristics.     

Interfacial Crystallization‐Driven Assembly of Conjugated Polymers/Quantum Dots into Coaxial Hybrid Nanowires: Elucidation of Conjugated Polymer Arrangements by Electron Tomography

A simple and practical “solution‐biphase method” allows the preparation of efficient charge‐transporting 1D nanocrystals with coaxial p–n junctions. It involves gradual diffusion of a top layer of poor solvent (acetonitrile) into a bottom layer of poly(3‐hexyl thiophene)‐b‐poly(2‐vinyl pyridine) (P3HT‐b‐P2VP) conjugated polymers (CPs) and CdSe quantum dots (QDs) dissolved in chloroform. Initial interfacial crystallization‐driven assembly of CPs results in the formation of seeds consisting of dimeric QDs transversely bridged by CPs. Coaxial CPs/QDs hybrid NWs are generated by 1D growth of QDs‐dimeric seeds, enabling tracing of the CPs‐crystallization process via the QDs. Thus, well‐arranged QDs along the longitudinal axis of the NWs infer highly crystalline CPs with edge‐on orientation, as confirmed by electron tomography, UV–vis spectroscopy, and grazing‐incidence wide‐angle X‐ray scattering. This high cristallinity as well as the increased length of the resulting hybrid NWs in solution and the corresponding crystallite size in as‐cast film represent a significant improvement compared to the conventional “one‐pot addition method”. Moreover, although randomly QDs‐attached hybrids of P3HT homopolymer are produced by the solution‐biphase method, branched aggregates with micrometer‐long NW arms are generated from the crystal seeds containing multiple growth facets without precipitate, despite acetonitrile being a nonsolvent.     

Inkjet printed silver source/drain electrodes for low-cost polymer thin film transistors

Silver tracks for source/drain (S/D) electrodes in low-cost polymer thin film transistors (TFTs) have been realized through inkjet printing technique, using heavily n-doped silicon wafer with thermally grown silicon dioxide as the substrate and poly(3-hexylthiophene) (P3HT) as the channel material. Spin coating a layer of poly-4-vinylphenol (PVPh) onto the substrate was found to enhance the silver track uniformity and lower the cure temperature (from 300 to 210 °C). The surface roughness of the PVPh film was optimized to improve the device performance. The fabricated P3HT TFT with a channel length of 20 μm exhibited a saturation mobility of 3.5 × 10⁻2 cm²/V/s which was three times higher than that obtained in P3HT TFTs with gold S/D electrodes.     

Electrical characterization of polymer-based FETs fabricated by spin-coating poly(3-alkylthiophene)s

The current-voltage (I-V) characteristics of two different polymer thin-film transistors (TFTs), based on spin-coating of poly(3-hexylthiophene)-P3HT and poly(3-hexadecylthiophene)-P3HDT, are studied. A model is developed to interpret the results and to explain the differences between these two polymers. Various parameters of the semiconducting polymers, including bulk mobility, field-effect mobility, trap density, and unintentional dopant concentration are estimated. The model takes into account the domination of the bulk current over the channel current in the subthreshold regime as well as the effects of the depletion layer as parasitic resistances in series with the channel resistance. Furthermore, the effects of the films thickness on the electrical characteristics of these TFTs are discussed. Compared to the P3HT, the P3HDT-based TFT has a lower subthreshold slope, higher on current ratio, and higher field-effect mobility.     

High-performance n-channel thin-film transistors with acene-based semiconductors

Two acene-based semiconductors were investigated with respect to their performance as n-type materials in organic field-effect transistors. The partially fluorinated ditetracenes (Ditetracen is protected by copywrite through the Patent WO/2007/000268. The patent is property of the Dritte Patentportfolio Beteiligungsgesellschaft mbH & Co. KG.) (DT) were synthesized in a high yield with different degrees of fluorination, one with four and another with two fluorine substituents (named as DT-4F and DT-2F, respectively). Both materials exhibit high thermal stability, with decomposition temperatures above 500 °C. Since both materials are supposed to have a lowered LUMO level compared to the non-fluorinated parent DT, n-type operation in thin-film transistors (TFTs) with gold source and drain contacts was expected. TFTs based on DT-2F, however, showed weak ambipolar transport only, which demonstrates insufficient fluorination to switch from hole-dominated to electron-dominated transport. On the other hand, high performance n-type TFTs have been achieved from DT-4F, with electron mobilities up to 1.0 cm²/V s. This result indicates that fluorinated DT material can act as excellent n-type semiconductor for applications in complementary circuits. This is demonstrated in a complementary inverter stage using DT-4F-based TFTs as n-type transistor and a non-fluorinated DT derivative-based TFT as p-type transistor.     

Degradation Mechanism of Poly-Si TFTs Dynamically Operated in OFF Region

This letter reports the study of the reliability behavior of poly-Si thin-film transistors (TFTs) with the pulsed gate voltage lower than the threshold voltage. First, the equivalent circuit model for poly-Si TFT is proposed. Considering the voltage drop for each element in the circuit model during the OFF-region gate dynamic stress, it is proposed that the main voltage drop occurs at the source and drain junctions, which could in turn degrade the device during stress. Based on this assumption, the gated p-i-n device fabricated on the same glass with the identical process conditions is stressed and analyzed. The similarity between the capacitance curves of the TFTs and gated p-i-n devices after stress proves that the main reason for degradation of poly-Si TFTs under gate OFF region ac stress is the large voltage drop across the source and drain junctions.      

Performance and reliability of SLS ELA polysilicon TFTs fabricated with novel crystallization techniques

SLS ELA polysilicon TFTs fabricated in films crystallized with several novel techniques, yielding different film microstructure and texture, were investigated. The parameter statistics indicate that the TFT performance depends on film quality and asperities, in conjunction with the grain boundary trap density. The drain current transients, upon TFT switch from OFF to ON state, showed gate oxide polarization, related to film asperities and also confirmed the presence of extended defects in the TFTs of small mobilities. DC hot carrier stress was applied, indicating a reliability dependence on polysilicon structure and differences in degradation mechanisms for the various TFT technologies.     

Environmental effects on the electrical behavior of pentacene thin-film transistors with a poly(methyl methacrylate) gate insulator

The electrical properties of top-contact pentacene thin-film transistors (TFTs) with a poly(methyl methacrylate) (PMMA) gate dielectric were analyzed in air and vacuum environments. Compared to the vacuum case, the pentacene TFT in air exhibited lower drain currents and more pronounced shifts in the threshold voltage upon reversal of the gate voltage sweep direction, together with a decrease in the field-effect mobility. These characteristic variations were explained in terms of two distinctive actions of polar H₂O molecules in pentacene TFT. H₂O molecules were suggested to diffuse under the source and drain contacts and interrupt the charge injection into the pentacene film, whereas those that permeate at the pentacene/PMMA interface retard hole depletion in and around the TFT channel. The diffusion process was much slower than the permeation process. The degraded TFT characteristics in air could be recovered mostly by storing the device under vacuum, which suggests that the air instability of TFTs is due mainly to the physical adsorption of H₂O molecules within the pentacene film.     

低温多晶硅TFT技术的发展

本文综述低温多晶硅（LTPS）TFT技术的最新进展情况。该技术目前的研究前沿是：（1）制作高性能的TFT；（2）在柔性衬底上制作LTPS TFT；（3）驱动有机发光器件的TFT；（4）LTPS TFT的新应用。同时还展望了LTPS TFT技术的未来发展趋势。     

Effect of Mesoscale Crystalline Structure on the Field‐Effect Mobility of Regioregular Poly(3‐hexyl thiophene) in Thin‐Film Transistors

Regioregular poly(3‐hexyl thiophene) (RR P3HT) is drop‐cast to fabricate field‐effect transistor (FET) devices from different solvents with different boiling points and solubilities for RR P3HT, such as methylene chloride, toluene, tetrahydrofuran, and chloroform. A Petri dish is used to cover the solution, and it takes less than 30 min for the solvents to evaporate at room temperature. The mesoscale crystalline morphology of RR P3HT thin films can be manipulated from well‐dispersed nanofibrils to well‐developed spherulites by changing solution processing conditions. The morphological correlation with the charge‐carrier mobility in RR P3HT thin‐film transistor (TFT) devices is investigated. The TFT devices show charge‐carrier mobilities in the range of 10^–4 ～ 10^–2 cm² V^–1 s^–1 depending on the solvent used, although grazing‐incidence X‐ray diffraction (GIXD) reveals that all films develop the same π–π‐stacking orientation, where the <100>‐axis is normal to the polymer films. By combining results from atomic force microscopy (AFM) and GIXD, it is found that the morphological connectivity of crystalline nanofibrils and the <100>‐axis orientation distribution of the π–π‐stacking plane with respect to the film normal play important roles on the charge‐carrier mobility of RR P3HT for TFT applications.     

A high-voltage polysilicon TFT with multigate structures

An approach is proposed for obtaining a high-voltage thin-film transistor (TFT) with multigate structure where polysilicon TFTs are connected in series. A basic principle for high-voltage operation has been investigated in detail through calculations based on a model describing log I_DS-V_GS characteristics observed in a single-gate polysilicon TFT. It has been found that off-state (V_GS<0) operation of the polysilicon TFT causes a large increase of breakdown voltage of the multigate TFT with the result that a nearly equal fraction of drain voltage is applied across the region around each elemental TFT. The breakdown voltage of drain of the fabricated multigate TFT which has five elemental TFTs has been elevated up to 80 V     

Novel Twin Poly-Si Thin-Film Transistors EEPROM With Trigate Nanowire Structure

This letter demonstrates a novel twin poly-Si thinfilm transistor (TFT) electrical erasable PROM (EEPROM) that utilizes trigate nanowires (NWs). The NW TFT EEPROM has superior gate control because its trigate structure provides a higher memory window and program/erase (P/E) efficiency over those of a single-channel one. For endurance and retention, the memory window can be maintained at 1.5 V after $hbox{10}^{3}$ P/E cycles and 25% charge loss for ten years of NW twin poly-Si EEPROM. This investigation explores its feasibility in future active matrix liquid crystal display system-on-panel and 3-D stacked Flash memory applications.      

Highly Robust Bendable Oxide Thin‐Film Transistors on Polyimide Substrates via Mesh and Strip Patterning of Device Layers

Advancement in thin‐film transistor (TFT) technologies has extended to applications that can withstand extreme bending or folding. The changes of the performances of amorphous‐indium‐gallium‐zinc‐oxide (a‐IGZO) TFTs on polyimide substrate after application of extreme mechanical bending strain are studied. The TFT designs include mesh and strip patterned source/drain metal lines as well as strip patterned a‐IGZO semiconductor layer. The robustness of the a‐IGZO TFTs with the strain of 2.17% corresponding to the radius of 0.32 mm is tested and no crack generation even after 60 000 bending cycles is found. The split of source/drain electrodes and semiconductor layer can improve the mechanical bending stability of the TFTs. This can be possible by using conventional TFT manufacturing process so that this technology can be easily applied to build robust TFT array for foldable displays.     

Solubility‐Induced Ordered Polythiophene Precursors for High‐Performance Organic Thin‐Film Transistors

With the aim of enhancing the field‐effect mobility of self‐assembled regioregular poly(3‐hexylthiophene), P3HT, by promoting two‐dimensional molecular ordering, the organization of the P3HT in precursor solutions is transformed from random‐coil conformation to ordered aggregates by adding small amounts of the non‐solvent acetonitrile to the solutions prior to film formation. The ordering of the precursor in the solutions significantly increases the crystallinity of the P3HT thin films. It is found that with the appropriate acetonitrile concentration in the precursor solution, the resulting P3HT nanocrystals adopt a highly ordered molecular structure with a field‐effect mobility dramatically improved by a factor of approximately 20 depending on the P3HT concentration. This improvement is due to the change in the P3HT organization in the precursor solution from random‐coil conformation to an ordered aggregate structure as a result of the addition of acetonitrile. In the good solvent chloroform, the P3HT molecules are molecularly dissolved and adopt a random‐coil conformation, whereas upon the addition of acetonitrile, which is a non‐solvent for aromatic backbones and alkyl side chains, 1D or 2D aggregation of the P3HT molecules occurs depending on the P3HT concentration. This state minimizes the unfavorable interactions between the poorly soluble P3HT and the acetonitrile solvent, and maximizes the favorable π–π stacking interactions in the precursor solution, which improves the molecular ordering of the resulting P3HT thin film and enhances the field‐effect mobility without post‐treatment.     

Controlling organization of conjugated polymer films from binary solvent mixtures for high performance organic field-effect transistors

We investigate the effect of a binary solvent blend as a solvent for poly{[N,N′-bis(2-octyldodecyl)-1,4,5,8-naphthalenediimide-2,6-diyl]-alt-5,5′-(2,2′-bithiophene)} P(NDI2OD-T2) on the characteristics of n-channel organic field-effect transistors (OFETs). To make the binary solvent blend, the low-boiling-point non-solvent propylene glycol methyl ether acetate (PGMEA, b.p ∼146 °C) is added to the high-boiling-point good solvent 1,2-dichlorobenzene (O-DCB, b.p ∼180 °C) at various mixing ratio from 0 to 40 v%. UV–vis spectra of P(NDI2OD-T2) solution dissolved in the binary solvent clearly show the formation of polymer aggregates through a gradual red shift of the intramolecular charge transfer band with the addition of high concentrations of non-solvent PGMEA. Higher edge-on oriented crystallinity is observed for P(NDI2OD-T2) films spin-coated from the binary solvent with 5–10 v% PGMEA by out-of-order x-ray diffraction. P(NDI2OD-T2) films are applied as the active layer in top-gate/bottom-contact OFETs. Improved n-type field-effect mobility of the P(NDI2OD-T2) semiconducting layer up to 0.59 cm²/Vs was achieved for on-center spin coated films compared to 1.03 cm²/Vs for off-center (parallel alignment) spin-coated films respectively employing the binary solvent with 10 v% PGMEA.     

Comparative study of soluble naphthalene diimide derivatives bearing long alkyl chains as n-type organic thin-film transistor materials

In this study, several naphthalene tetracarboxylic acid diimide (NTCDI) derivatives substituted at the N and N′ positions with long normal alkyl chains of different lengths were evaluated as soluble n-type organic thin-film transistor (TFT) materials. NTCDI derivatives with diundecyl (NTCDI-C11), didodecyl (NTCDI-C12), and ditridecyl (NTCDI-C13) exhibited acceptable solubility in chloroform, and their TFTs showed typical n-type TFT performance with relatively high field effect electron mobility (～0.2 cm²/V s) after annealing at a workable temperature of 150 °C. Although NTCDI with dioctyl (NTCDI-C8) showed good solubility in chloroform, the TFT performance of this material was highly inferior to that of NTCDI-C11, NTCDI-C12, or NTCDI-C13. We could not anneal NTCDI-C8 thin films at workable temperatures in vacuo because of sublimation of the material from the substrates. In contrast, NTCDI with dipentadecyl (NTCDI-C15) and dioctadecyl (NTCDI-C18) exhibited both poor solubility for chloroform and poor TFT performance. In short, these compounds are not suitable as soluble n-type organic TFT materials.     

A Simple Spacer Technique to Fabricate Poly-Si TFTs With 50-nm Nanowire Channels

In this letter, polycrystalline-silicon thin-film transistors (poly-Si TFTs) with 50-nm nanowire (NW) channels, which are fabricated without advanced photolithography by using a sidewall spacer-formation technique, are proposed for the first time. Because the polygate electrode is perpendicularly across poly-Si NW channels to form a trigatelike structure, the proposed poly-Si NW TFT owns outstanding gate controllability. In summary, a simple and low-cost scheme is proposed to fabricate high-performance poly-Si NW TFT suitable for future display manufacturing and practical applications.