Design and implementation of circuit-switched network based on nanoscale quantum-dot cellular automata

Photonic Network Communications - Quantum-dot cellular automata (QCA) is a nanoscale technology to design digital circuits in nano-measure which acts based on electron’s interaction....     

Design of sequential circuits by quantum-dot cellular automata

This paper proposes a detailed design analysis of sequential circuits for quantum-dot cellular automata (QCA). This analysis encompasses flip-flop (FF) devices as well as circuits. Initially, a novel RS-type FF amenable to a QCA implementation is proposed. This FF extends a previous threshold-based configuration to QCA by taking into account the timing issues associated with the adiabatic switching of this technology. The characterization of a D-type FF as a device consisting of an embedded wire is also presented. Unique timing constraints in QCA sequential logic design are identified and investigated. An algorithm for assigning appropriate clocking zones to a QCA sequential circuit is proposed. A technique referred to as stretching is used in the algorithm to ensure timing and delay matching. This algorithm relies on a topological sorting and enumeration step to consistently traversing only once the edges of the graph representation of the QCA sequential circuit. Examples of QCA sequential circuits are provided.     

An efficient design and implementation of Vedic multiplier in quantum-dot cellular automata

Telecommunication Systems - The Quantum-Dot Cellular Automata (QCA) is an incipient nanotechnology in contrast to the CMOS technology with appealing features like low power consumption, high speed...     

Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing

Design of parity preserving logic based on emerging nanotechnology is very limited due to present technological limitation in tackling its high error rate. In this work, Quantum-dot cellular automata (QCA), a potential alternative to CMOS, is investigated for designing easily testable logic circuit. A novel self-testable logic structure referred to as the testable-QCA (t-QCA), using parity preserving logic, is proposed. Design flexibility of t-QCA then evaluated through synthesis of standard functions. The programmability feature of t-QCA is utilized to implement an ALU, realizing six important functions. Although the parity preservation property of t-QCA enables concurrent detection of permanent as well as the transient faults, an augmented test logic circuit (TC) using QCA primitives has been introduced to cover the cell defects in nanotechnology. Experimental results establish the efficiency of the proposed design that outperforms the existing technologies in terms of design cost and test overhead. The achievement of 100% stuck-at fault coverage and the 100% fault coverage for single missing/additional cell defects in QCA layout of the t-QCA gate, address the reliability issues of QCA nano-circuit design.     

Layout design of manufacturable quantum-dot cellular automata

Quantum-dot cellular automaton (QCA) is an emergent technology that is not hindered by quantum effects that limit the scaling of CMOS technology, but instead employs them to perform computation. However, this brings its own impediments, such as the influence of the thermodynamic effects. Beside that, QCA has to be coupled with CMOS circuitry of different size features to enable clocking. We discussed all these facts and devised a floorplan which would facilitate manufacturability. Based on it we developed the process of QCA layout design and defined the design rules that must be considered in order to ensure correct operation. These instructions enable the automatization of designing a QCA circuit layout.     

Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata

Quantum-dot cellular automata is one of the candidate technologies used in Nano scale computer design and a promising replacement for conventional CMOS circuits in the near future. Since memory is one of the significant components of any digital system, designing a high speed and well-optimized QCA random access memory (RAM) is a remarkable subject. In this paper, a new robust five-input majority gate is first presented, which is appropriate for implementation of simple and efficient QCA circuits in single layer. By employing this structure, a novel RAM cell architecture with set and reset ability is proposed. This architecture has a simple and robust structure that helps achieving minimal area, as well as reduction in hardware requirements and clocking zone numbers. Functional correctness of the presented structures is proved by using QCADesigner tool. Simulation results confirm efficiency and usefulness of the proposed architectures vis-à-vis state-of-the-art.     

Design of thermometer code-to-gray code converter circuit in quantum-dot cellular automata for nano-computing network

Photonic Network Communications - This article proposes the thermometer code converter, which eliminates the requirement of binary code converter to generate gray codes in different digital...     

Design and comparison of new fault-tolerant majority gate based on quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is increasingly valued by researchers because of its nanoscale size and very low power consumption.However,in the manufacture of nanoscale devices prone to various forms of defects,which will affect the subsequent circuits design.Therefore,fault-tolerant QCA architectures have become a new research direction.The purpose of this paper is to build a novel fault-tolerant three-input majority gate based on normal cells.Compared with the previous structures,the majority gate shows high fault tolerance under single-cell and double-cell omission defects.In order to examine the functionality of the proposed structure,some physical proofs under single cell missing defects are provided.Besides,two new fault-tolerant decoders are constructed based on the proposed majority gate.In order to fully demonstrate the performance of the proposed decoder,the previous decoders were thoroughly compared in terms of fault tolerance,area and delay.The result shows that the proposed design has a good fault tolerance characteristic,while the performance in other aspects is also quite good.     

Analytical method for cell displacement defect quantum-dot cellular automata primitive

Quantum-dot cellular automata (QCA) is an emerging computational paradigm which can overcome scaling limitations of the existing complementary metal oxide semiconductor (CMOS) technology. The existence of defects cannot be ignored, considering the fabrication of QCA devices at the molecular level where it could alter the functionality. Therefore, defects in QCA devices need to be analyzed. So far, the simulation-based displacement defect analysis has been presented in the literature, which results in an increased demand in the corresponding mathematical model. In this paper, the displacement defect analysis of the QCA main primitive, majority voter (MV), is presented and carried out both in simulation and mathematics, where the kink energy based mathematical model is applied. The results demonstrate that this model is valid for the displacement defect in QCA MV.     

Novel single-trit comparator circuits in ternary quantum-dot cellular automata

Analog Integrated Circuits and Signal Processing - Today, with the continuation of the reduction of the dimensions of transistors, the thickness of the gate is so small that it causes the leakage...     

Analysis of missing and additional cell defects in sequential quantum-dot cellular automata

The defect characterization of sequential devices and circuits, implemented by molecular quantum-dot cellular automata (QCA), is analyzed in this paper. A RS-type flip–flop is first introduced; this flip–flop takes into account the timing issues associated with the adiabatic switching of this technology and its requirements. It is then shown that a D-type flip–flop can be constructed with an embedded QCA wire which extends over multiple clocking zones. The logic-level characterization of both flip–flop devices is provided. A single additional and missing cell defect model is assumed for molecular implementation. For sequential circuits, defect characterization is pursued. It is shown that defects affect the functionality of basic QCA devices, resulting mostly in unwanted inversion and majority voter acting as a wire at logic level. In this paper, it is shown that a device-level characterization of the defects and faults can be consistently extended to a circuit-level analysis.     

Design and simulation of sequential circuits in quantum-dot cellular automata: Falling edge-triggered flip-flop and counter study

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology, with extremely small feature size and ultralow power consumption comparing with transistor-based technology. Anteriority, basic level-triggered flip-flop designs based on QCA implementation were examined. In this paper, we utilize the unique QCA characteristics and clock zones to design falling edge-triggered J-K flip-flop that is stable and practical. Simulation with the QCADesigner simulator is performed to verify the functionality of the proposed falling edge-triggered flip-flop. This paper also explores the design of counters. Synchronous counters are designed with several different bit sizes and simulation results demonstrate the validity of them.     

A novel FPGA-programmable switch matrix interconnection element in quantum-dot cellular automata

The Quantum-dot cellular automata (QCA) is a novel nanotechnology, promising extra low-power, extremely dense and very high-speed structure for the construction of logical circuits at a nanoscale. In this paper, initially previous works on QCA-based FPGA’s routing elements are investigated, and then an efficient, symmetric and reliable QCA programmable switch matrix (PSM) interconnection element is introduced. This element has a simple structure and offers a complete routing capability. It is implemented using a bottom-up design approach that starts from a dense and high-speed 2:1 multiplexer and utilise it to build the target PSM interconnection element. In this study, simulations of the proposed circuits are carried out using QCAdesigner, a layout and simulation tool for QCA circuits. The results demonstrate high efficiency of the proposed designs in QCA-based FPGA routing.     

Parity generator and parity checker in the modified trinary number system using savart plate and spatial light modulator

The parity generators and the checkers are the most important circuits in communication systems. With the development of multi-valued logic (MVL), the proposed system with parity generators and checkers is the most required using the recently developed optoelectronic technology in the modified trinary number (MTN) system. This system also meets up the tremendous needs of speeds by exploiting the savart plates and spatial light modulators (SLM) in the optical tree architecture (OTA).     

Novel RAM cell designs based on inherent capabilities of quantum-dot cellular automata

Quantum Cellular Automata (QCA) is a novel and attractive method which enables designing and implementing high-performance and low-power consumption digital circuits at nano-scale. Since memory is one of the most applicable basic units in digital circuits, having a fast and optimized QCA-based memory cell is remarkable. Although there are some QCA structures for a memory cell in the literature, however, QCA characteristics may be used in designing a more optimized memory cell than blindly modeling CMOS logics in QCA. In this paper, two improved structures have been proposed for a loop-based Random Access Memory (RAM) cell. In the proposed methods, the inherent capabilities of QCA, such as the programmability of majority gate and the clocking mechanism have been considered. The first proposed method enjoys smaller number of cells and the wasted area has been reduced compared to traditional loop-based RAM cell. For the second proposed method, the memory access time has been duplicated in presence of smaller number of cells. Irregular placement of QCA cells in a QCA layout makes its realization troublesome. So, we have proposed alternative versions of the proposed methods that exploit regularity of clock zones in design and have compared them to each other. QCA designer has been employed for simulation of the proposed designs and proving their validity.     

A new design of fault-tolerant digital comparator based on quantum-dot cellular automata

Analog Integrated Circuits and Signal Processing - Quantum-dot cellular automata (QCA) is a new nanoscale development for the future of digital systems. It has been gained a lot of attention since...     

A new sign detection design for the residue number system based on quantum-dot cellular automata

Photonic Network Communications - Sign detection has a wide application in digital fixed-point signal processing; however, it seems hard to conduct it in residue number systems (RNSs) based on...     

Operation of a quantum-dot cellular automata (QCA) shift register and analysis of errors

Quantum-dot cellular automata (QCA) is a digital logic architecture that uses single electrons in arrays of quantum dots to perform binary operations. A QCA latch is an elementary building block which can be used to build shift registers and logic devices for clocked QCA architectures. We discuss the operation of a QCA latch and a shift register and present an analysis of the types and properties of errors encountered in their operation.     

正弦信号发生器的设计与实现

为精确地输出正弦波、调幅波、调频波、PSK,ASK等信号及保证信号的高可靠性,设计出一种新型的正弦信号发生器.该正弦信号发生器以可编程逻辑器件CPLD和单片机AT89S52为基础,采用数字频率合成DDS技术实现频率合成功能,结合高速D/A器件AD9713使得输出频率维持在1k～10MHz范围内,步进为100Hz,且通过对CPLD采用相应的数字控制算法实现调频FM,调幅AM和健控PSK,ASK数字调制功能.测试结果表明,设计的正弦信号发生器输出信号稳定度优于10~-4,在频率范围内50Ω的负载上输出正弦波电压幅度稳定在6±0.6V,波形无明显失真,系统的整体性能良好.     

基于元胞自动机的高速公路收费设计

文章在事故预防、吞吐量、成本等方面分析特定收费广场设计的性能,并运用主成分分析法确定公路收费站的评价模型。在建立评价模型的基础上,利用元胞自动机模型对收费亭数量以及形状等方面进行优化。