Building ultra-low-power high-temperature digital circuits in standard high-performance SOI technology

For ultra-low-power applications, digital integrated circuits may operate at low frequency to reduce dynamic power consumption. At high temperature, the power consumption of such circuits is completely dominated by static power dissipation due to leakage currents. In this contribution, we propose a new logic style, namely ultra-low-power (ULP) logic style which achieves negative V_gs self-biasing, to benefit from the small area and low dynamic power of high-performance deep-submicron SOI technologies while keeping ultra-low leakage, even at high temperature. In 0.13 μm partially-depleted SOI CMOS technology, the static power consumption at 200 °C is reduced by nearly three orders of magnitude at the expense of increased delay and area.     

115 Gbit/s downstream and 10 Gbit/s upstream TWDM-PON together with 11.25 Gbit/s wireless signal utilizing OFDM-QAM modulation

In this work, we propose and investigate a 115 Gbit/s (4 × 28.75 Gbit/s) downstream and 10 Gbit/s upstream time- and wavelength-division-multiplexing passive optical network (TWDM-PON) together with 11.25 Gbit/s wireless broadcasting signal using multi-band orthogonal-frequency-division-multiplexing (OFDM) modulation within 10 GHz bandwidth. Here, to compensate the power fading and chromatic dispersion in the higher frequency, we utilize a −0.7 chirp parameter Mach–Zehnder modulator (MZM) for the OFDM signal. Hence, negative power penalties of −0.3 and −0.4 dB in the downstream and broadcasting wireless signals; and power penalty of 0.3 dB in the upstream signal are measured at the bit error rate (BER) of 3.8 × 10⁻³ after 20 km standard single mode fiber transmission without dispersion compensation.     

A 0.33 V 2.5 μW cross-point data-aware write structure,read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS

Conventional data-aware structure SRAMs consume unnecessary dynamic power during the read phase due to the read-half-select issue. In this paper, a 9T-based read-half-select disturb-free SRAM architecture with the cross-point data-aware write strategy is proposed. Based on the proposed write-half-select and read-half-select disturb-free strategy, our 9T bitcell structure improves the read and write SNM by 2.5X and 2.4X compared to traditional bitcells. Furthermore, the proposed strategy and 9T bitcell structure can reduce the read power dissipation on bitline of the SRAM array by 5.14X compared with traditional SRAMs. Based on the proposed architecture, a 16Kb SRAM is fabricated in a 130 nm CMOS which is fully functional from 1.2 V down to 0.33 V. The minimal energy per cycle is 11.8pJ at 0.35 V. The power consumption at 0.33 V is 2.5 µW with 175 kHz. The proposed SRAM has 1.5X and 4.2X less total power and leakage power than other works.     

On the effect of channel spacing,launch power,and regenerator placement on the design of mixed-line-rate optical networks

Due to the increasing heterogeneity and the growing volume of traffic, telecom backbone networks are going through significant innovations. Wavelength-division multiplexed (WDM) optical networks can now cost-effectively support the growing heterogeneity of traffic demands by having mixed line rates (MLR) over different wavelength channels.The coexistence of wavelength channels with different line rates, e.g., 10/40/100 Gbps, in the same fiber brings up various design issues: in this study, we focus on (1) choice of channel spacing; (2) choice of launch power; and (3) regenerator placement. Channel spacing affects the signal quality in terms of bit-error rate (BER), and hence affects the maximum reach of lightpaths, which is a function of line rates. Various approaches to set an opportunistic width of the channel spacing can be considered, viz., (i) uniform fixed channel spacing specified by the ITU-T grid (typically 50 GHz); (ii) different channel spacing for different line rates; or (iii) optimal value of channel spacing for all line rates that leads to minimum cost.The launch optical power of a signal is another important parameter that affects the network cost. Adjacent channels on different line rates, especially 10 Gbps and 100 Gbps, may exhibit serious degradation of signal quality and optical reach for both the channels due to cross-phase modulation (XPM) between them. Launch power plays a role in such a scenario as it governs the BER by affecting both the signal power and the noise power due to XPM. Moreover, intelligent choice of launch powers on different line rates can significantly reduce the number of regenerators required in the network. The tradeoff between placement of regenerators and choice of launch power is an important problem to address for MLR network design.In this work, we investigate the effects of channel spacing and launch optical power by evaluating the cost of a MLR network for different values of these parameters. We also study the interplay between regenerator placement and launch power. Our results show that (a) it is possible to identify optimal values of channel spacing for a minimum-cost MLR network design, and (b) controlling the power of 10 Gbps and 100 Gbps channels shows maximum sensitivity to the network cost.     

Economic and system impact of hybrid Raman–EDFA amplification in a 40 × 40 Gbps optical transmission network with DPSK modulation

Demands of modern high-bandwidth services drive the need to constantly improve existing optical amplification technology beyond its current bounds. In this paper, we demonstrate a hybrid broadband amplification scheme which is capable of improving the system performance of a wavelength-division-multiplexed (WDM) network. We present the study of optical signals with differential-phase-shift keying (DPSK) modulation at 40 Gbps and its transmission in a 50-GHz spaced, 40-channel WDM system over an 80-km link with hybrid optical amplification. A comparison of the system and cost impacts of a Raman-only amplification scheme with two hybrid Raman–erbium doped fiber amplifier schemes (Hybrids I and II) is performed. It is shown that one of the proposed hybrid schemes (Hybrid II) outperforms the other by (i) improving the tolerance to signal input power by 17 dB and (ii) increasing the system reach by 55 km for input signal power of 5 dBm, for a bit error rate (BER) performance of 10⁻¹².     

Experimental demonstration of variable weight SAC-OCDMA system for QoS differentiation

In this paper the experimental and simulation results of variable-weight spectral amplitude coding optical code division multiple access (VW-SAC-OCDMA) system is demonstrated. In the proposed system, three users with weights of 6, 4 and 2 each operating at data rate of 1.25 Gb/s represent video, data and voice services, respectively. Results show that for back-to-back system minimum average power of −20 dBm per chip is required to maintain the acceptable performance. Transmission up to 60 km of fiber is demonstrated. Using mathematical approximation the capacity of VW-SAC-OCDMA system is demonstrated.     

A power-efficient reference buffer with wide swing for switched-capacitor ADC

A level-shifter-aided CMOS reference voltage buffer with wide swing for high-speed high-resolution switched-capacitor ADC is proposed. It adopts a level shifter for wide swing and a NMOS-only branch circuit for low power. High PSRR (power supply rejection ratio) is guaranteed by the proposed architecture. The proposed reference buffer is integrated in a 14-bit 150 MSps low-power pipelined ADC with the amplification phase of only 2.5 ns. With the input of 2.4 MHz and 2 Vp-p, the measurement of the fabricated ADC shows that the SNDR is 71.3 dB and the SFDR is 93.6 dBc. And the power consumption of the reference buffer is 17 mW from a 1.3 V power supply.     

A nesting ranging algorithm for a Hybrid WDM/TDM PON with colorless Reflective-ONUs under different distances OLT-ONUs

To reduce costs and cumbersome laser provisioning at the Optical Network Unit (ONU) user level in an access Passive Optical Network (PON), the use of a Reflective-ONU (R-ONU) is a good choice for up-data transmission. An optical carrier is sent by the Optical Line Terminal (OLT) at the Central Office, and a device at the ONU modulates the carrier with the upstream data. This allows all ONUs to be equal and colorless, without a light source in a Hybrid WDM/TDM architecture. A Dynamic Bandwidth Allocation is placed at the OLT, managing the lasers and photodetectors shared by all R-ONUs. The OLT laser and photodetector employed in an up-data transmission must be tuned for each ONU and a particular Round Trip Time (RTT), which is twice the propagation time from OLT to ONU. When an R-ONU is served by a laser, the photodetector must also be available after the RTT to demodulate the up-data. We propose a novel nesting ranging algorithm to deal with large different distances OLT–ONUs avoiding collisions and minimizing the delay under Priority Queuing with Quality of Service (QoS).

Improving GBW product on CMOS operational transconductance amplifiers by interleaved feedforward paths

This paper presents two Operational Transconductance Amplifier (OTA) compensation schemes for multistage topologies. The solutions are based on interleaved feedforward paths that cancel a non-dominant pole similarly to the zero nulling resistor technique with the advantage of avoiding resistors. Both schemes are designed in 90 nm CMOS process, the first one obtains 71 dB of DC gain, a gain bandwidth product (GBW) of 720 MHz with 360 μW of power consumption. The second proposed scheme obtains a similar DC gain and doubles the former proposed OTA GBW at the expense of 2.2 mW of power consumption for high speed applications. The compensation schemes are theoretically analyzed and the design guidelines are presented. The results of post layout simulations and corner analysis validate the new solutions.     

Performance analysis of ONU-wavelength grouping schemes for efficient scheduling in long reach-PONs

Long Reach PONs (LR-PON) were proposed to extend the benefits of Passive Optical Networks (PON) to more users and to a larger area. This paper considers a Dynamic Bandwidth Allocation (DBA) based on a hybrid combination of Time Division Multiplexing (TDM) and Wavelength Division Multiplexing (WDM). The time complexity of the DBA algorithm is typically O(n log n), where n denotes the number of ONUs. Since the maximum number of supported ONUs in an LR-PON can be as high as 2048, the computation time required for computing a schedule will be very high and directly impacts the overall network performance. In this paper, we have presented a grouping strategy to reduce the computation requirements. The number of ONUs is split into mutually exclusive groups with the OLT scheduling each group independently and in parallel. With the static grouping strategy every user is assigned to a group and the assignment of wavelength resources is fixed. However, with non-uniform loads, we observed that static grouping was not found to be suitable as the delay variation was significant across the groups. To address this gap, we introduce the concept of dynamic grouping and define three dynamic grouping heuristics that adapt to the current network load conditions and (re)allocate the ONUs and wavelength resources suitably. The proposed schemes have been compared in terms of delay variation and wavelength utilization. Of the three heuristics, ONU to Least Loaded wavelength group (OLL) and Least Wavelength Resources (LWR) heuristics balance the packet delay across ONUs assigned to different groups and Proportional Wavelength Usage (PWU) heuristic reduces power consumption by allocating fewer wavelength resources.     

Fast adaptive OFDM-PON over single fiber loopback transmission using dynamic rate adaptation-based algorithm for channel performance improvement

In this paper, we propose a novel fast adaptive approach that was applied to an OFDM-PON 20-km single fiber loopback transmission system to improve channel performance in term of stabilized BER below 2 × 10⁻³ and higher throughput beyond 10 Gb/s. The upstream transmission is performed through light source-seeded modulation using 1-GHz RSOA at the ONU. Experimental results indicated that the dynamic rate adaptation algorithm based on greedy Levin–Campello could be an effective solution to mitigate channel instability and data rate degradation caused by the Rayleigh back scattering effect and inefficient resource subcarrier allocation.     

Structural,optical and dielectric properties of HfSiO films prepared by co-evaporation method

HfSiO dielectric films were prepared on Si substrate by the co-evaporation method. The chemical composition, crystalline temperature, optical and electrical properties of the compound film were investigated. X-ray photoelectron spectroscopy analysis illustrated that the atom ratio of Hf to Si was about 4:1 and Hf–Si–O bonds appeared in the film. The X-ray diffraction analysis revealed that the crystalline temperature of the film was higher than 850 °C. Optical measurements showed that the refractive index was 1.82 at 550 nm wavelengths and the optical band gap was about 5.88 eV. Electrical measurements demonstrated that the dielectric constant and a fixed charge density were 18.1 and 1.95×10¹² cm⁻² respectively. In addition, an improved leakage current of 7.81 μA/cm² at the gate bias of −3 V was achieved for the annealed HfSiO film.     

Electrical characterization of MFeOS gate stacks for ferroelectric FETs

We investigated the electrical characterization of metal–ferroelectric–oxide semiconductor (MFeOS) structures for nonvolatile memory applications. Al/PZT/Si and Al/PZT/SiO₂/Si capacitors were fabricated using lead zirconate titanate (PZT; 35:65) as the ferroelectric layer. The maximum C–V memory window was 6 V for metal–ferroelectric semiconductor (MFeS) structures and 2.95 and 6.25 V for MFeOS capacitors with a buffer layer of 2.5 and 5 nm, respectively. Comparative data reveal a higher dielectric strength and lower leakage characteristic for an MFeOS structure with a 5-nm SiO₂ buffer layer compared to an MFeS structure. We also observed that the leakage characteristic was influenced by the annealing conditions.     

Leakage reduction through optimization of regular layout parameters

Regular layouts that follow restrictive design rules are essential to robust CMOS design in order to alleviate many manufacturing induced effects, such as the effect of non-rectangular gate (NRG) due to sub-wavelength lithograph. NRG dramatically increases the leakage current by more than 15X compared to that of ideal physical layout. To mitigate such a penalty, we developed a technique to optimize regular layout through restrictive design rule parameters and to benchmark post-lithography circuit performance. We propose a procedure to systematically optimize key layout parameters in regular layout to minimize the leakage energy with minimal over head to active energy, circuit speed and area. The proposed layout optimization technique is demonstrated with a 65 nm technology and projected for 45 nm and 32 nm technology nodes. Experimental results show that more than 70% reduction in leakage can be achieved with area penalty of ～10% and 9–12% overhead on circuit speed and active energy.     

Wavelength channel minimization-based energy-aware mechanism in a multichannel EPON

We propose an energy-aware mechanism (EAM) applicable to the multichannel Ethernet Passive Optical Network that can minimize the number of wavelength channels used and save energy. Wavelength channel minimization is processed by collecting the information such as request message, allocated grant, and start time of each optical network unit (ONU) transmission in the previously elapsed scheduling cycles and comparing it with the buffer occupancy and packet delay conditions of the ONUs required by the user’s quality-of-service requirement. They are exchanged between the optical line terminal (OLT) and the ONUs via the multipoint control protocol. In this way, at the beginning of each scheduling cycle, the ONU’s buffer occupancy and packet delay conditions can be evaluated, and then, the OLT decides the smallest number of wavelength channels to be used in the current scheduling cycle. By turning off the OLT receivers corresponding to the unused wavelength channels, the OLT can save energy. The performance of the proposed EAM was evaluated through simulations using nonjoint off-line dynamic bandwidth allocation and dynamic wavelength assignment algorithms. The results showed that the OLT receivers’ power consumption could be reduced by 48 % on average.     

Low complexity PAPR reduction techniques for clipping and quantization noise mitigation in direct-detection O-OFDM systems

We present different distortionless peak-to-average power ratio (PAPR) reduction techniques that can be easily applied, without any symmetry restriction, in direct-detection (DD) optical orthogonal frequency division multiplexing (O-OFDM) systems based on the fast Hartley transform (FHT). The performance of DD O-OFDM systems is limited by the constraints on system components such as digital-to-analog converter (DAC), analog-to-digital converter (ADC), the Mach–Zehnder modulator (MZM) and electrical amplifiers. In this paper, in order to relax the constraints on these components, we propose to symmetrically clip the transmitted signal and apply low complexity (LC) distortionless PAPR reduction schemes able to mitigate, at the same time, PAPR, quantization and clipping noise. We demonstrate that, applying LC-selective mapping (SLM) without any additional transform block, the PAPR reduction is $1.5\text{dB}$ with only one additional FHT block using LC-partial transmit sequence (PTS) with random partitions; up to $3.1\text{dB}$ reduction is obtained. Moreover, the sensitivity performance and the power efficiency are enhanced. In fact, applying LC PAPR reduction techniques with one additional transform block and a 6 bit DAC resolution, the required receiver power for 8 dB clipping level and for a ${10}^{-3}\text{BER}$ is reduced by $5.1\text{dB}$.     

A new type of low power read circuit in EEPROM for UHF RFID

A novel low power read circuit without reference in 1 k-bits electrically erasable and programmable (EEPROM) for UHF RFID is designed and implemented in SMIC 0.18 μm EEPROM process. The read power consumption is optimized using a pre-charge sense amplifier. To improve the performance of the read circuit, a self-detect circuit, a read control logic and a feedback scheme are adopted, combined with a special time sequence. For a power supply voltage of 1 V, an average power consumption of 1.6 μA for the read operation of the EEPROM can be achieved when the read clock frequency is 640 kHz. What is more, with a 110 °C temperature change, the read power consumption variation is as low as 12%. The die size of the EEPROM is 0.15 mm², where the read circuit occupies 0.0125 mm².     

Suppression of optical beat interference-noise in orthogonal frequency division multiple access-passive optical network link using self-homodyne balanced detection

A new technique, which reduces optical beat interference (OBI) noise in orthogonal frequency division multiple access-passive optical network (OFDMA-PON) links, is proposed. A self-homodyne balanced detection, which uses a single laser for the optical line terminal (OLT) as well as for the optical network unit (ONU), reduces OBI noise and also improves the signal to noise ratio (SNR) of the discrete multi-tone (DMT) signal. The proposed scheme is verified by transmitting quadrature phase shift keying (QPSK)-modulated DMT signal over a 20-km single mode fiber. The optical signal to noise ratio (OSNR), that is required for BER of 10⁻⁵, is reduced by 2 dB in the balanced detection compared with a single channel due to the cancellation of OBI noise in conjunction with the local laser.     

EPON中基于NIOS的ONU设计

提出一种基于ALTERA公司的NIOS嵌入式微处理器的ONU(光网络单元)设计方案.通过将NIOS软核处理器、自定义逻辑模块、存储器和I/O集成到单块低成本的FPGA上,组成一个SOPC(片上可编程系统),实现以太网无源光网络中的ONU功能.与采用套片加软件来实现ONU的方案相比,该方案降低了系统的成本,复杂性和功耗.     

A charge-pump and comparator based power-efficient pipelined ADC technique

A charge-pump and comparator based technique is presented for power-efficient pipelined analog-to-digital conversion. The technique takes advantage of a passive charge pump to implement the core function of residue voltage amplification and exploits a comparator-controlled charging circuit to buffer the residue voltage to the next stage. Unlike the conventional buffer circuit using source followers, no voltage headroom is sacrificed in this voltage buffering scheme. The comparator overshoot due to comparator delay is minimized by a self-cancellation scheme. The proposed pipelined ADC technique uses only capacitors, comparators and current sources with digital calibration to achieve low power consumption. Designed and fabricated in a 0.18 μm CMOS technology, a proof-of-concept ADC has measured 39.1 dB SNDR (6.2-bit ENOB) at 25 MS/s while consuming 3.5 mW from a 1.8 V supply.