The effects of boron penetration on p+ polysilicon gatedPMOS devices

The penetration of boron into and through the gate oxides of PMOS devices which employ p⁺ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V_FB , increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF₂ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi₂ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO ₂/Si interface     

Suppression of boron penetration in p+ polysilicon gateP-MOSFETs using low-temperature gate-oxide N2O anneal

It has been reported that high-temperature (~1100°C) N₂ O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900~950°C) N₂O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO₂ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60~110 Å gate oxides, a certain amount of nitrogen (~2.2%) incorporated near the Si/SiO₂ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate     

Oxide thickness effect on boron diffusion in thin oxide p+ Si gate technology

Based on a network defect model for the diffusion of B in SiO₂ we propose that B diffuses via a peroxy linkage defect whose concentration in the oxide changes under different processing conditions. We show that as the gate oxide is scaled below 80 Å in thickness, additional chemical processes act to increase B diffusivity and decrease its activation energy, both as a function of the distance from the Si/SiO₂ interface. For a 15 Å oxide, the B diffusivity at 900°C would increase by a factor of 24 relative to diffusion in a 100 Å oxide     

Fluorine diffusion on a polysilicon grain boundary network inrelation to boron penetration from P+ gates

The combined effect of boron penetration and fluorine transport from P⁺ polycrystalline gates on flat-band voltage is studied. The SIMS concentration depth profiles elucidate the effect of annealing temperature on the fluorine transport, which in turn affects the boron penetration induced change in flat-band voltage. The fluorine diffusion in the poly gate is dominated by grain boundary diffusion. The identification of this mechanism is supported by SIMS profiles and a simulation based on a new methodology of network diffusion     

Argon ion-implantation on polysilicon or amorphous-silicon forboron penetration suppression in p+ pMOSFET

In this paper, a technique to use Ar ion-implantation on the p⁺α-Si or poly-Si gate to suppress the boron penetration in p⁺ pMOSFET is proposed and demonstrated. An Ar-implantation of a dose over 5×10¹⁵ cm^-2 is shown to be able to sustain 900°C annealing for 30 min for the gate without having the underlying gate oxide quality degraded. It is believed to be due to gettering of fluorine, then consequently boron, by the bubble-like defects created by the Ar implantation in the p⁺ gate region to reduce the B penetration. Excellent electrical characteristics like dielectric breakdown (E_bd), interface state density (D_it), and charge-to-breakdown (Q_bd) on the gate oxide are obtained. The technique is compatible to the present CMOS process. The submicron pMOSFET fabricated by applying this technique exhibit better subthreshold characteristics and hot carrier immunity     

A novel dual p-/p+ poly gate CMOS VLSItechnology

A CMOS VLSI technology using p^- and p⁺ poly gates for NMOS and PMOS devices is presented. Due to the midgap work function of the p^- poly gate, the NMOS native threshold voltage is 0.7 V and, therefore, no additional threshold adjust implantation is required. The NMOS transistor is a surface-channel device with improved field-effect mobility and lower body effect due to the reduction in the channel doping concentration. In addition, the p ^- poly gate is shown to be compatible with p⁺ poly-gated surface-channel PMOS devices     

Device simulation of submicrometer gate p+-i-p+ diamond transistors

Two-dimensional device simulation of submicrometer gate diamond p ⁺-i-p⁺ transistors with a SiO₂ gate insulator was investigated using the MEDICI device simulation program. A large modulation of the source-to-drain current was obtained in the accumulation mode. The computed diamond device characteristics were equivalent or better than the simulation results of 6H-SiC MESFET's. It was concluded that the problems in diamond MESFET associated with the deep acceptor levels due to boron doping can be overcome in the p⁺ -i-p⁺ diamond FET's because of the hole injection and the space charge limited current     

Modeling boron diffusion in thin-oxide p+ Si gatetechnology

A network defect model suitable for use in process simulation is presented for the diffusion of B in SiO₂ and, in particular, B in the presence of F and H₂. We find that B diffuses via a peroxy linkage defect the concentration in the oxide of which changes under different processing conditions. From random walk theory it is possible then to calculate the resulting diffusion coefficients. These results are compared with measured diffusivities and empirical adjustments are made     

Oxynitride gate dielectrics for p+-polysilicon gate MOSdevices

Different oxynitride gate dielectrics (NH₃-nitrided, reoxidized NH₃-nitrided, N₂-annealed NH₃-nitrided, and N₂O grown oxides) are investigated for use in p⁺-polysilicon gate MOS devices. The comparison is based on flatband voltage shift as well as decrease in inversion capacitance. Results show that NH₃-nitrided and N ₂-annealed NH₃-nitrided oxides best suppress the boron penetration and, consequently, these two undesirable effects. These findings are explained on the basis of the distribution of nitrogen in various oxynitride dielectrics     

Suppression of boron penetration for p+ stacked poly-Sigates by using inductively coupled N2 plasma treatment

Nitridation of stacked poly-Si gates by inductively coupled N₂ plasma (ICNP) treatment has been shown to suppress boron penetration and improve gate oxide integrity. The ICNP treatments on the stacked poly-Si layers create nitrogen-rich layers not only between the stacked poly-Si layers but also in the gate oxide after post implant anneal, thus resulting in effective retardation of boron diffusion. In addition, positioning of ICNP treatment closer to gate oxides leads to higher nitrogen peaks in the gate oxide region, resulting in further suppression of boron penetration and improvement of gate oxide reliability     

A physical model for hole direct tunneling current in p+poly-gate pMOSFETs with ultrathin gate oxides

A model of the hole direct tunneling gate current accounting for heavy and light hole's subbands in the quantized inversion layer is built explicitly. This model comprises four key physical parameters: inversion layer charge density, hole impact frequency on SiO₂-Si interface, WKB transmission probability, and reflection correction factor. With the effective hole mass m_oxh =0.51 M_o for the parabolic dispersion relationship in the oxide, experimental reproduction without any parameter adjustment is consistently achieved in p⁺ poly-gate pMOSFETs with 1.23, 1.85, and 2.16 nm gate oxide thicknesses. The proposed model can thereby serve as a promising characterization means of direct tunnel oxides. In particular, it is calculated that the secondary subbands and beyond, although occupying few holes, indeed contribute substantially to the direct tunneling conduction due to effective lower barrier heights, and are prevailing over the first subbands for reducing the oxide field down below 1 MV/cm     

Modeling boron diffusion in ultrathin nitrided oxide p+Si gate technology

Based on a network defect model for the diffusion of B in SiO₂, we propose that B diffuses via a peroxy linkage defect (pld) whose concentration in the oxide changes under different processing conditions. We show that as N is added to the gate oxide (nitridation), N atoms compete with B atoms for activation through the diffusion-defect sites. The model predicts that nitridation is ineffective in stopping B penetration when BF₂ implants dope the polysilicon gate, as well as for the case of very thin gate dielectrics with B-implanted gates     

Avalanche multiplication noise characteristics in thin GaAs p+-i-n+ diodes

Avalanche noise measurements have been performed on a range of homojunction GaAs p⁺-i-n⁺ and n⁺-i-p ⁺ diodes with “i” region widths, ω from 2.61 to 0.05 μm. The results show that for ω⩽1 μm the dependence of excess noise factor F on multiplication does not follow the well-established continuous noise theory of McIntyre [1966]. Instead, a decreasing noise factor is observed as ω decreases for a constant multiplication. This reduction in F occurs for both electron and hole initiated multiplication in the thinner ω structures even though the ionization coefficient ratio is close to unity. The dead-space, the minimum distance a carrier must travel to gain the ionization threshold energy, becomes increasingly important in these thinner structures and largely accounts for the reduction in noise     

A Monte Carlo investigation of multiplication noise in thin p+-i-n+ GaAs avalanche photodiodes

A Monte Carlo (MC) model has been used to estimate the excess noise factor in thin p⁺-i-n⁺ GaAs avalanche photodiodes (APD's). Multiplication initiated both by pure electron and hole injection is studied for different lengths of multiplication region and for a range of electric fields. In each ease a reduction in excess noise factor is observed as the multiplication length decreases, in good agreement with recent experimental measurements. This low noise behavior results from the higher operating electric field needed in short devices, which causes the probability distribution function for both electron and hole ionization path lengths to change from the conventionally assumed exponential shape and to exhibit a strong dead space effect. In turn this reduces the probability of higher order ionization events and narrows the probability distribution for multiplication. In addition, our simulations suggest that fur a given overall multiplication, electron initiated multiplication in short devices has inherently reduced noise, despite the higher feedback from hole ionization, compared to long devices     

Thin-film SOI CMOS transistors with p+-polysilicon gates

A comparison is given of the use of p⁺-polysilicon and n⁺-polysilicon as the gate material for high-performance CMOS processes in fully depleted, thin SOI (silicon on insulator) films. Experimental devices on Simox substrates are compared with numerical simulations. It is found that n-channel transistors with p-poly gates require lower channel doping levels than their n-poly counterparts, leading to higher gains and easier control of the threshold voltage. The lower electric fields in the p-poly transistor also result in improved drain breakdown characteristics. Control of the subthreshold and punch-through characteristics of the p-poly device requires the use of very thin films when there is significant fixed positive charge at the interface with the buried oxide     

Highly suppressed boron penetration in NO-nitrided SiO2for p+-polysilicon gated MOS device applications

In this paper, we demonstrate the superior diffusion barrier properties of NO-nitrided SiO₂ in suppressing boron penetration for p⁺-polysilicon gated MOS devices. Boron penetration effects have been studied in terms of flatband voltage shift, decrease in inversion capacitance (due to polysilicon depletion effect), impact on interface state density, and charge-to-breakdown. Results show that NO-nitrided SiO₂, as compared to conventional thermal SiO₂, exhibits much higher resistance to boron penetration, and therefore, is very attractive for surface channel PMOS technology     

Submicrometer thin gate oxide P-channel transistors with P+polysilicon gates for VLSI applications

Submicrometer p-channel transistors have been fabricated using thin (150 Å) gate oxide and p+ polysilicon gates. Favorable device characteristics have been achieved for L(eff) as low as 0.4 µm. P+ gate was formed under different processing conditions. Data showed negligible boron penetration through the thin oxide. Two-dimensional simulations demonstrated the advantages of p+ poly in reducing short channel effects. Experimental results from three device lots with different processing conditions showed good subthreshold slope and low leakage current, even for low threshold voltages. VTversus L(eff) showed much less threshold drop than was seen using n+ poly. Device characteristics were robust with respect to processing variations.     

Effective crosstalk isolation through p+ Si substrateswith semi-insulating porous Si

Through-the-wafer porous Si (PS) trenches have been used to provide radio frequency (RF) isolation in Si because of their semi-insulating property. Reduction of crosstalk by 70 dB at 2 GHz and 45 dB at 8 GRz is demonstrated between Al pads with 800 μm separation on p⁺Si. Crosstalk suppression increases linearly with increasing PS width to beyond 320 μm. This suppression is degraded by one order of magnitude when the Si underneath the PS trenches remains and serves as a residual path for crosstalk. These results show that PS is an excellent candidate for RF isolation in modern VLSI technology     

Low avalanche noise characteristics in thin InP p+-i-n+ diodes with electron initiated multiplication

We have performed electron initiated avalanche noise measurements on a range of homojunction InP p⁺-i-n⁺ diodes with “i” region widths, w ranging from 2.40 to 0.24 μm. In contrast to McIntyre's noise model a significant reduction in the excess noise factor is observed with decreasing w at a constant multiplication in spite of α, the electron ionization coefficient being less than β, the hole ionization coefficient. In the w=0.24 μm structure an effective β/α ratio of approximately 0.4 is deduced from the excess noise factor even when electrons initiate multiplication, suggesting that hole initiated multiplication is not always necessary for the lowest avalanche noise in InP-based avalanche photodiodes     

Polyoxides grown on n+ polysilicon

The polarity asymmetry on the electrical characteristics of the oxides grown on n⁺ polysilicon (polyoxides) was investigated in terms of the oxidation process, the doping level of the lower polysilicon layer, the oxidation temperature and the oxide thickness. It was found that the thin polyoxide prepared by using a low-temperature wafer loading and N₂ pre-annealing process, has a smoother polyoxide/polysilicon interface and exhibits a lower oxide tunneling current, a higher dielectric breakdown field when the top electrode is positively biased, a lower electron trapping rate and a larger charge-to-breakdown than does the normal polyoxide. The polarity asymmetry is also strongly dependent on the doping level of the lower polysilicon layer, the oxidation temperature and the oxide thickness. It was found that only the thinner polyoxides (⩽240 Å) grown on the heavily-doped polysilicon film (30 Ω/sq) by using the higher-temperature oxidation process (⩾950°C) conduct a less oxide tunneling current when the top electrode is positively biased